ABSTRACT Title of Dissertation: THERMAL ISOLATION OF HIGH POWER DEVICES IN HETEROGENEOUS INTEGRATION Michael Christopher Fish, Doctor of Philosophy, 2017 Dissertation directed by: Professor F. Patrick McCluskey Department of Mechanical Engineering Heterogeneous integration (HI) technologies present an important development in the pursuit of higher performance and reduced size, weight, power and cost of electronic systems (SWAP-C). HI systems, however, pose additional challenges for thermal management due to the disparate operating conditions of the devices. If the thermal coupling between devices can be reduced through a strategy of thermal isolation, then the SWAP-C of the accompanying thermal solution can also be reduced. This is in contrast to the alternative scenario of cooling the entire package to the maximum reliable temperature of the most sensitive devices. This isolation strategy must be implemented without a significant increase in device interconnect distances. A counter-intuitive approach is to seek packaging materials of low thermal conductivity – e.g. glass – and enhance them with arrays of metallic through-layer vias. This dissertation describes the first ever demonstration of integrating such via-enhanced interposers with microfluidic cooling, a thermal solution key to the high power applications for which HI was developed. Among the interposers tested, the best performing were shown to exhibit lower thermal coupling than bulk silicon in selective regions, validating their ability to provide thermal isolation. In the course of the study, the via-enhanced interposer is modeled as a thermal metamaterial with desirable, highly-anisotropic properties. Missing from the supporting literature is an accurate treatment of these interposers under such novel environments as microfluidic cooling. This dissertation identifies a new phenomenon, thermal microspreading, which governs how heat couples into a conductive via array from its surroundings. Both finite element analysis (FEA) and a new analytic solution of the associated boundary value problem (BVP) are used to develop a model for describing microspreading. This improves the ability to correctly predict the thermal behavior of via-enhanced interposers under diverse conditions. THERMAL ISOLATION OF HIGH POWER DEVICES IN HETEROGENEOUS INTEGRATION By Michael Christopher Fish Dissertation submitted to the Faculty of the Graduate School of the University of Maryland, College Park in partial fulfillment of the requirements for the degree of Doctor of Philosophy 2017 Advisory Committee: Professor Patrick McCluskey, Chair Professor Avram Bar-Cohen Professor Michael Ohadi Professor Bao Yang Professor Ankur Srivastava, Dean’s Representative ©Copyright by Michael Christopher Fish 2017 ii For my wife and family, For keeping this process moving with patient anticipation iii Acknowledgements This dissertation, the final product of a long but rewarding endeavor, would not be possible without the mentorship, support, contributions, and listening ears of so many people. Foremost, I want to thank my advisors, Dr. Avram Bar-Cohen and Dr. Patrick McCluskey. Dr. Bar-Cohen, for challenging me to articulate and defend my ideas, and pushing me to provide something with a lasting impact. Dr. McCluskey, for the warm candor and advice on navigating academia, and the encouragement to explore on my own. I’d also like to thank AFRL and DARPA for the support that made this project possible. I want to thank my two lab partners Mike Manno and Sevket Yuruker. Mike, for showing me the ins and outs of ANSYS and patiently hearing out my thought experiments. Sevket, for all day conversations on just about anything, and a new perspective on it all. And to other labmates – Frank Robinson, Caleb Holloway, Darin Sharar, David Squiller, and David Deisenroth: thank you for the insights, support, and good times. Finally, thank you to my family. Special thanks to Meredith for encouraging me through this long journey. Thanks to my parents for setting me up to succeed and cheering me on. Thank you to Ariadne for timing things just right. iv CONTENTS List of Figures ........................................................................................................ vi List of Tables ...........................................................................................................x 1.0 Summary .......................................................................................................1 2.0 Introduction ...................................................................................................3 3.0 Literature Review ..........................................................................................6 3.1 Heterogeneous Systems ...............................................................................7 3.2 Fabrication of Via Arrays ..........................................................................10 3.3 Reliability of Via Arrays ............................................................................11 3.4 Modeling of Thermal Via Arrays – Top-down Approaches ......................12 3.5 Modeling of Thermal Via Arrays – Bottom-up Approaches .....................15 3.6 Experimental Characterization of Via Arrays ............................................16 3.7 Thermal Constriction Resistance ...............................................................17 3.8 Summary of Literature ...............................................................................20 4.0 Thermal Isolation Modeling ........................................................................23 Case Study: Thermal Isolation of Heterogeneously Integrated Systems ...23 Creating a Compact Thermal Model..........................................................30 4.2.1 Reduction of Parameters ................................................................... 32 4.2.2 Analytic Treatment of Thermal Constriction .................................... 36 4.2.3 Results of Finite Element Analysis ................................................... 41 4.2.4 Analysis – Visualizing the Design Space .......................................... 46 5.0 Microgap Cooling of Thermal Via Arrays ..................................................52 Microgap Cooler and Flow Loop Design ..................................................55 Microgap Cooling Results .........................................................................62 5.2.1 Chip Temperature Rise ...................................................................... 64 5.2.2 Raw Profile Analysis ......................................................................... 72 5.2.3 Spatial Temperature Profiles ............................................................. 76 Conjugate Heat Transfer Modeling ...........................................................81 Upstream Microgap Experiment ................................................................84 6.0 Modeling Thermal Microspreading Resistance in Via Arrays ....................89 Effect of Boundary Conditions on Array Vertical Thermal Resistance ....92 v Outcome of FEA – Convection Boundaries ..............................................95 Surface Films and Material Interfaces .....................................................100 Extension to Axisymmetric Via Cells ......................................................105 Chapter Summary ....................................................................................111 7.0 Analytic Model of Microspreading in Via Array Unit Cells .....................114 Isoflux Boundary for Coaxial Unit Cells .................................................114 Special Case: Perfect Thermal Interface ..................................................126 Generalization: Upper Surface Convection Boundary ............................127 Discussion of Analytic Solutions .............................................................134 8.0 Future Work and Recommendations .........................................................149 9.0 Summary and Contributions ......................................................................152 Appendix A – Supplemental Case Study Models ................................................154 Appendix B – Microcooler Design Drawing .......................................................158 Appendix C – Derivation of Analytical Series Solution ......................................159 The Solutions 𝛩1,𝑟(𝜌, 𝜁) and 𝛩2,𝑟(𝜌, 𝜁) .......................................................... 159 The Solution 𝛩1,𝑧(𝜌, 𝜁) ................................................................................... 160 The solution 𝛩2,𝑧(𝜌, 𝜁) ................................................................................... 162 The coupling coefficients 𝐴𝑛 and 𝐶𝑛 .............................................................. 166 Limiting Case: ℎ → ∞ .................................................................................... 168 Temperature Solution for 𝐻𝑓 .......................................................................... 171 References ............................................................................................................178 vi LIST OF FIGURES Figure Page Figure 1: DAHI integration approaches. Images from left to right from NGAS, HRL, and Raytheon ................................................................................................................ 8 Figure 2: Side view of a top-down via unit cell, vertical conductivity ............................. 14 Figure 3: Layout for HI Case Study .................................................................................. 26 Figure 4: Array Parameters for Vias ................................................................................. 26 Figure 5: Rotated view of HI case study system showing input power and underside cooling. Vertical scale exaggerated. .......................................................................... 27 Figure 6: System in package with glass interposer, thermal via array, and differential cooling......................................................................................................................... 29 Figure 7: System in package with a silicon interposer, thermal via array, and differential cooling......................................................................................................................... 29 Figure 8: Axisymmetric constriction model for anisotropic interposer. ........................... 36 Figure 9: Oscillations in temperature components for low 𝑘𝑟 interposers. ...................... 39 Figure 10: Thermal coupling function for two interposers using values described in Figure 8, with 𝑘𝑧 = 150 W/m-K and ℎ ∗ = 30,000 W/m2-K. Hot spot is isoflux (Equation (23)). The solid curve corresponds to an interposer with 𝑘𝑟 = 1.5 W/m-K, while the dashed 𝑘𝑟 = 150 W/m-K. ........................................................................... 41 Figure 11: Interposer surface temperature for isoflux spot with underside cooling ℎ∗= 30,000 W/m2-K as a function of radial distance and 𝑘𝑟. ..................................... 44 Figure 12: Interposer surface temperature for an isoflux with underside cooling ℎ∗= 100,000 W/m2-K as a function of radial distance and 𝑘𝑟. .................................. 44 Figure 13: Interposer surface temperature for isothermal spot with cooling ℎ∗= 30,000 W/m2-K as a function of radial distance and 𝑘𝑟 ...................................... 45 Figure 14: Interposer surface temperature for isothermal spot with cooling ℎ∗= 100,000 W/m2-K as a function of radial distance and 𝑘𝑟 .................................... 45 Figure 15: Interposer thermal resistance with respect to hotspot centroid for the four cases shown in Figs. 5-8. ...................................................................................................... 46 Figure 16: Finding minimum device separation for a given Θ𝐶 , 𝑄𝑎 ∕ 𝑄𝑀, and thermal coupling function 𝑅(𝑟). .............................................................................................. 49 Figure 17: Process map of creating compact thermal model from a heterogeneously integrated system ........................................................................................................ 51 Figure 18: Glass wafer division into 16 test coupons. “A” coupons have uniform surface pads over arrays while “B” coupons have individually terminated vias. Right: Close- up view of a coupon, detailing the four identical via arrays ....................................... 55 Figure 19: Design drawing for copper microgap cooler manifold ................................... 56 Figure 20: Side view of mounted sample. a) Clamping Bracket, b) Interposer Sample, c) Copper Manifold, d) Thermal Via Array, e) O-ring Standoff. ............................... 57 Figure 21: Sample dicing layout compatible with microgap cooler testing .................... 58 vii Figure 22: Diagram of single-phase flow loop. ................................................................ 60 Figure 23: Microgap differential pressure as a function of measured flowrate. .............. 60 Figure 24: Laser heating of samples with single phase water flow. a) Glass sample, 200 ccm flowrate. b) Glass sample, 2 ccm flowrate. c) Si sample, 200 ccm flowrate. d) Si sample, 2 ccm flowrate....................................................................................... 62 Figure 25: Thermal test chiplet mounted on a via array sample. The chiplet dimensions are 2 mm x 4.5 mm, and the serpentine dimensions are 1.6 mm x 1.85 mm. The pads at the lower edge of the image are for voltage sensing across the inner third of the Pt serpentine. ............................................................................................................... 62 Figure 26: Thermal test chip mounted on interposer sample A1, describing typical IR field of view. .......................................................................................................... 66 Figure 27: Platinum serpentine resistance calibration with constant temperature coefficient of resistance. ............................................................................................. 68 Figure 28: Temperature rise for three interposer samples. Hollow markers designate temperature rise at the chiplet edge as determined by IR thermography. Solid markers designate the average chiplet surface temperature as determined by Pt serpentine resistance. .............................................................................................. 69 Figure 29: 1W scaled temperature rise data for each interposer, as determined by IR thermography at chiplet edge. ..................................................................................... 70 Figure 30: Subtracted IR image of powered chiplet on GL A1 interposer. Pixel brightness corresponds to temperature rise between powered and unpowered condition. Red lines indicate where spatial temperature profiles are extracted. ........ 74 Figure 31: Aggregated raw profile data from sample GL A1 under 0.83 cm3/s of water flow. Data from within the chiplet and points corresponding to copper via locations are excluded. ............................................................................................................... 74 Figure 32: Comparison of the 𝜆2 parameter of each interposer subjected to varying flowrate. Error bars are not shown; error in flowrate is ±0.11 cm3/s, error in 𝜆2 is 3%. ..................................................................................................................................... 80 Figure 33: Comparison of spatial thermal profiles for each interposer under identical flow conditions. Temperature rise normalized by heater power. Estimated error in temperature rise is ±5.1%, uniform across each sample, plus limits in camera resolution at individual pixels of ±0.1K. Estimated error in aligning profiles at chip edge is ±11µm. ............................................................................................................ 81 Figure 34: Simulated temperature rise in chip and interposer for sample GL A3 ............ 83 Figure 35: Wall heat flux at fluid-interposer boundary. The downstream region of negative heat flux is highlighted with the dashed enclosure. Right: plotting only contours of negative heat flux. .................................................................................... 83 Figure 36: Silicon 1W comparison ................................................................................... 84 Figure 37: Heater chiplet positioning for revised microgap resting. Sample B3, water flow from left to right. ................................................................................................ 86 Figure 38: Upstream interposer temperature rise per watt of heater power. Estimated error in temperature rise is ±5.1%, uniform across each sample, plus limits in camera viii resolution at individual pixels of ±0.1K. Estimated error in aligning profiles at chip edge is ±11µm. ............................................................................................................ 87 Figure 39: Via unit cells used in Chapter 0. (a) Cu-glass unit cell used to investigate convection boundary conditions. (b) Cu-glass unit cell used to investigate contacting films (dark grey volume). ........................................................................................... 91 Figure 40: Heat flux vectors at a vertical cross-section of a unit cell. The top and bottom faces of the cell have isoflux boundary conditions of the same magnitude. The mid- plane contains an isotherm, as evidenced by the parallel flux vectors there. Units are in W/m2 ....................................................................................................................... 95 Figure 41: Heat flux vectors resulting from isothermal cell boundary condtions. Results obtained along a path through the via center and parallel to the cell upper and lower surfaces (e.g. a horizontal subselection from the cross-section in Figure 40). Units W/m2.................................................................................................................. 95 Figure 42: TXV array keff,z as computed by FEA ............................................................. 97 Figure 43: Via cell total thermal resistance, calculated from keff,z data ............................ 98 Figure 44: Microspreading resistance of thick TXV substrates. Each point is the intercept of the linear asymptote for data sets of the type in Figure 43 (there were three not included for clarity). The line connecting the points is the correlation given by Eq. (6). ........................................................................................................................ 99 Figure 45: Evolution of keff,z of a TXV array as an adhered film increases in thickness. Film conductivity is 10 and 40 W/m-K, and substrate thickness is 200 µm. ........... 101 Figure 46: keff,z versus contacting material thermal conductivity for different substrate/cell thicknesses .......................................................................................... 102 Figure 47: Micro Spreading resistance versus contacting material conductivity. Each point is obtained from FEM results in Figure 46. The line connecting the points is the correlation given by Eq. (7). ..................................................................................... 103 Figure 48: Maximum cell spreading resistance as a function of Non-Dimensional via diameter and conductivity ......................................................................................... 107 Figure 49: Value of the discount factor, f, for all 1200 axisymmetric cells. The points that fall farthest from the curve are those cells with the smallest via diameters. Circles correspond to the convection boundary condition, while diamonds correspond to film contact. ...................................................................................................................... 110 Figure 50: Detail view of data in Fig. 12, with ±15% bounds on 𝜁 plotted. Cells with 𝑑/𝑃∗ < 0.18 are excluded. ........................................................................................ 111 Figure 51: Schematic of Boundary Value Problem ........................................................ 115 Figure 52: Microspreading Subproblem Decomposition ................................................ 119 Figure 53: Total cell thermal resistance (in K/W) for isoflux boundary cells computed using series solution. Uses fixed cell diameter 2𝑏 = 2/𝜋 ∙100µm, length 400 µm, substrate conductivity 1 W/m-K, and via-substrate interface ℎ = 50,000 W/m2-K . 124 Figure 54: Isoflux cell spreading resistance component (in K/W) for conditions plotted in Figure 53. .................................................................................................................. 124 Figure 55: Spreading resistance for a TSV-like system with varying interface conductance............................................................................................................... 125 ix Figure 56: Bounding surface formed by isothermal boundary condition via cells ......... 137 Figure 57: Areal resistance summation rule for isoflux cells with independent flux tubes ................................................................................................................................... 139 Figure 58: Bounding surface formed by via cells with isoflux upper surface boundaries and zero interfacial conductance ............................................................................... 141 Figure 59: Representation of cell resistance parameter space using zero-interface conductance cells. Adjusting parameter 𝐻 from 0 to infinity sweeps the middle surface from the upper isoflux bounding surface to the lower isothermal one. In this example, 𝐻 = 4......................................................................................................... 144 Figure 60: Series solution results plotted against isothermal and isoflux parametric bounding surfaces. Three series plotted are those from Figure 53, with an additional series representing a shortened unit cell with 𝐿 = 100𝜇𝑚, 𝑘𝑣 = 400 W/m-K, and other parameters maintained at values from Figure 53. ............................................ 145 Figure 61: Temperature field in isoflux boundary via cell due only to microspreading resistance for a cell 400 µm long. The former isoflux surface is at 𝜁 = 0, and the central cell axis at 𝜌 = 0. 𝑘𝑣 = 400 W/m-K, 𝑘𝑠 = 1 W/m-K, 𝑞′′ = 50 W/cm 2. The via-substrate interface is located at 𝜌 = 2𝑏/2𝑎 = 𝑃∗/𝑑 = 112.8𝜇𝑚/20𝜇𝑚 = 0.177. ................................................................................................................................... 147 Figure 62: Temperature field in isoflux boundary via cell due only to microspreading resistance for a cell 100 µm long. Other parameters maintained as described in Figure 61. .................................................................................................................. 147 Figure 63: SoC with uniform cooling and no vias .......................................................... 154 Figure 64: SoC with uniform cooling and copper via array ........................................... 154 Figure 65: SoC with differential cooling and copper via array ...................................... 155 Figure 66: SiP with no vias and uniform cooling ........................................................... 156 Figure 67: SiP with copper vias and uniform cooling .................................................... 156 Figure 68: SiP with no vias and differential cooling ...................................................... 156 Figure 69: SiP with copper vias and differential cooling ............................................... 156 Figure 70: Enlarged view of Figure 60 ........................................................................... 177 x LIST OF TABLES Table Page Table 1: Base-Equivalent Cooling and Pumping Cost of Single-Phase Water Microcoolers ................................................................................................................25 Table 2: Material Properties for HI Case Study.................................................................28 Table 3: Via Array Design of Experiments .......................................................................54 Table 4: Fitting Parameters for Silicon Interposer .............................................................78 Table 5: Fitting Parameters for Interposer GL A1: Padless, 100 µm Pitch, Aligned ........78 Table 6: Fitting Parameters for Interposer GL B1: Pad, 100 µm Pitch, Aligned ..............78 Table 7: Fitting Parameters for Interposer GL A2: Padless, 200 µm Pitch, Aligned ........78 Table 8: Fitting Parameters for Interposer GL A3: Padless, 100 µm Pitch, Close- Packed ..........................................................................................................................79 Table 9: Upstream Two-Term Fitting Coefficients ...........................................................87 Table 10: Cell parameters used in axisymmetric micro-spreading survey .....................106 Table 11: Correlation parameters for convection boundaries .........................................108 Table 12: Correlation parameters for material contact boundaries .................................108 Table 13: Chiplet Temperature Rise for 200 µm and 100 µm Interposers ......................157 1 1.0 SUMMARY The challenges of thermally isolating heterogeneously integrated components from one another is investigated. Due to the disparate thermal properties of the components, where some dissipate large amounts of power but withstand high operating temperatures while others are sensitive, low-power devices, thermal isolation of the devices can provide a means of managing the individual temperatures of each device type with a targeted, differential cooling approach. This differential cooler can be designed so that it requires less fluid pumping power than a cooler that must cool the entire electronic system to the safe operating temperature of the most sensitive devices. With the ability to specify the degree of isolation, important tradeoffs between device temperature rise and minimum device separation (and interconnect length) can then be made. After examining several heterogeneous integration approaches, it was determined that a segregated chiplet approach offered the most promising avenue for thermal isolation efforts. Incorporating thermal via-enhanced glass interposers as the carrier for the heterogeneous chiplets provides necessary lateral thermal resistance to heat flow while providing a conductive path from the high-power components to underside cooling solutions. Substantial modeling efforts and an experimental survey of such via-enhanced glass interposers demonstrated the principles of isolation in these HI systems. Also explored is the integration of these interposers with single-phase embedded microfluidic cooling, an effort not yet represented in the literature. This experimental portion of this thesis – demonstrating the microfluidic integration – concludes that high power, heterogeneously-integrated 2.5D interposer- based systems are particularly amenable to thermal isolation efforts. Thermal isolation can bring the most benefit when there is a wide disparity in allowable device temperature 2 rise, not just in absolute device operating temperature. This means it is a particularly attractive option when inlet coolant temperatures are high. In such cases, thermal isolation can reduce the size of thermal “keep out” zones created by high power devices (areas in the package or die that have temperatures too high to reliable place sensitive devices), while allowing the optional implementation of a power-saving differential embedded cooler. The microgap experiments successfully demonstrate a reduction in thermal keep out distance for devices that can only tolerate a thermal coupling constant of 0.24 K/W or less. To address shortcomings in current effective conductivity literature, this thesis introduces the concept of microspreading resistance as a component of the thermal behavior of arrays of conductive vias. It provides recommendations for mitigating microspreading when it is undesirable, and a formalism for incorporating it into existing equivalent thermal conductivity models of via arrays. Microspreading resistance is analyzed using both finite element modeling (FEM) and a direct solution of Laplace’s equation within a via-enhanced interposer unit cell. Via-substrate systems that are covered range from high conductivity contrast copper-in-glass, to through-silicon vias (TSVs) possessing an interfacial oxide between via and substrate. 3 2.0 INTRODUCTION Fundamental physical considerations limit the useful feature size of transistors and other microelectronic devices that constitute modern electronic products. Whether these limitations stem from the underlying nanophysics (e.g. electron tunneling) or from more familiar obstacles (e.g. diffraction limit of lithographic processes), size reduction and accompanying performance gains from the further miniaturization of transistors cannot continue indefinitely. Fortunately, there is considerable room for improvement in the interconnection and packaging of these products. By migrating components traditionally placed in separate packages – processors and memory, or amplifiers and their controllers – into the same package or even on the same die, significant gains can be realized. A promising paradigms for this migration is heterogeneous integration (HI). This technology seeks to disrupt the traditional approach of a board of discrete, two- dimensional packages which must necessarily communicate with each other through long, high resistance, limited-bandwidth interconnects. HI seeks to fabricate each component or device within a package in its optimal semiconductor material – e.g. silicon, InP, or gallium nitride – colloquially referred to as “the best junction for the function” approach. In this way economical, highly mature (and hence low feature size) silicon CMOS circuitry can be used to control high performance III-V semiconductor transistors, amplifiers, and radio frequency devices in a hybrid, single-package circuit. Such systems can be expected to be smaller, lower in total power dissipation, and have better performance than those relying on components housed in separate packages. The thermal management of such HI electronic packages is poorly understood and presents additional challenges in the development of HI technology. Devices fabricated 4 in different semiconductors have different thermal limits. Moreover, HI’s greatest strength is in integrating components that have very different purposes and performance requirements, resulting in components which differ dramatically in power output and maximum operating temperature. A uniform cooling approach must then seek to cool the entire package at the heat flux of the highest dissipation device and to the operating temperature of the most sensitive device, often resulting in an oversized thermal solution that may well negate any size, weight, and required power advantages gained from employing heterogeneous integration. In analyzing the thermal characteristics of these high density packages, considerable attention is paid to the role of through-layer vias (TXVs) in conducting heat between layers of material and/or active chips. Just as TXVs provide a conductive pathway for electrical signaling, they can also be relied upon for heat transfer. This work seeks to contribute to the development of these technologies by enhancing the understanding of the impacts and possible advantages offered by arrays of TXVs to the thermal management of these systems TXV arrays and their host substrates can be treated as a composite material, an approach taken by equivalent thermal conductivity methods. During the course of modeling thermal isolation in HI systems, this work investigates current limitations of equivalent thermal conductivity approaches for TXV arrays, identifies a new property of the arrays – microspreading resistance – that remedies the primary limitation, and conducts a series of experimental procedures capable of measuring the microspreading resistance of different arrays. This microspreading-augmented equivalent thermal 5 conductivity theory is used to analyze the thermal isolation of heterogeneously integrated high power amplifier chips and their control logic on via-enhanced glass interposers. To accompany this analysis, an HI system is experimentally characterized. This system simulates the spatially variable power dissipations of an HI system using thermal test chiplets hosted on a microgap cooled interposer. The resulting interposer surface temperatures are measured using infrared thermography. With this measurement, the demonstration also validates the microspreading-aware thermal models, as well as highlighting the reduction in size of thermal “keep out” zones of sensitive devices compared to a bulk silicon interposer. These keep out zones are areas within the package where temperatures exceed the safe operating limits of sensitive control logic device. Lowering temperatures in areas throughout the package below this threshold will shrink these zones. 6 3.0 LITERATURE REVIEW There are four main points of focus for this literature review. First, an overview of heterogeneous integration will outline the various approaches used to create electronic systems that incorporate devices of different semiconductor materials or of widely disparate thermal characteristics. As will be seen, many approaches pursue the “intimate” integration of CMOS and III-V devices, and while these achieve the shortest interconnect lengths, they also result in the spatial intermixing of the disparate devices leading to very poor prospects for thermal isolation. “Chiplet-on-carrier” approaches segregate the disparate devices into individual chiplets, using either an active CMOS carrier chip or a passive interposer to host the chiplets. This approach has the best prospects for successful thermal isolation, with some promising results being shown using via-enhanced glass interposers. The next point of focus (covered over two sections) will be on fabrication and reliability of through-layer vias and via arrays. Much of the literature in this area is generated from the 3D-IC community, but as the majority of HI approaches use through- layer vias for interconnection and thermal via arrays have been identified as useful tool for providing low resistance thermal paths while assuring a high degree of thermal isolation, these publications will provide valuable background material. Reliability and manufacturing concerns will place constraints on feasible implementations of via arrays within the thermally-isolating glass interposer. The third portion of this chapter (three sections) will present publications that model and/or measure the thermal properties of via arrays. Most models seek to treat the array of vias as a composite material, essentially smearing the vias and substrate into a homogeneous, anisotropic medium. The manner in which the anisotropic conductivity is 7 obtained is categorized into two camps. One, the top-down approach, extracts these properties from detailed finite element models of via array unit cells. Because these cells are highly tailored to the arrays they represent, this approach tends to be very empirical in its conclusions, with results that are often applicable only to particular array being modeled. The other approach, bottom-up, adopts a physics-driven viewpoint and restricts itself to analytic models on simplified cells. The conclusions of this approach are more general, attempting to predict the effective conductivities of a variety of array geometries and materials. Following the discussion of array thermal modeling will be a presentation of publications dealing with experimental approaches. The last section of the literature review will introduce the topic of thermal constriction resistance. Also known as thermal spreading resistance, this phenomenon and its body of literature will factor into both of the thrusts of this work. In defining the concept of microspreading, many parallels will be drawn to the more canonical spreading resistance problem, and it will be argued that under particular conditions they collapse to the same model. Additionally, thermal constriction will appear in the thermal isolation application, where microspreading must be confronted in the approximation of the interposer as an equivalent medium, and which once homogenized becomes the anisotropic domain of a thermal spreading analysis driven by the heated amplifier footprint. 3.1 Heterogeneous Systems While the motivations and approach to any HI implementation vary from application to application, an excellent area to start is with DARPA’s Diverse Accessible Heterogeneous Integration (DAHI) program [1] . DAHI seeks to integrate mature, high- 8 density CMOS control circuitry with wide bandgap III-V devices (InP and GaN) to achieve smaller and lighter high-performance radio frequency systems. Performers in the program that embody particular approaches include Northrop Grumman Aerospace Systems (NGAS) [2, 3], Raytheon [4, 5], MIT Lincoln Labs [6], and HRL Laboratories [7]. The three primary approach styles are shown in Figure 1. Figure 1: DAHI integration approaches. Images from left to right from NGAS, HRL, and Raytheon Raytheon uses an approach where individual transistors of either InP or GaN are interleaved as needed between CMOS devices fabricated on custom silicon-on-insulator (SOI) wafers. This is done by etching a “window” through the upper layer of silicon and oxide to access an underlying layer of germanium (for InP) or <111> silicon (for GaN). These layers provide the necessary lattice parameters for the low-defect epitaxial growth of the desired III-V semiconductor. After wide bandgap device fabrication, the heterogeneous devices are on the same planar active surface and are assembled into circuits using typical multilayer interconnects. MIT uses a similar approach, creating what they call a “hybrid wafer” where selective etching can expose lattice matched layers for epitaxial growth. NGAS HRL Raytheon 9 HRL uses a wafer-to-wafer approach where III-V devices are fabricated on dedicated wafers, resulting in wafer for each heterogeneous device type in addition to the base CMOS wafer. Each of the two or more wafers are patterned with an array of metal “heterogeneous interconnects” (HICs) that correspond to mating HICs on the other wafers. The wafers are then bonded together, with the HICs completing the electrical interconnection between the heterogeneous devices. In this way there is an increased degree of verticality compared to the selective epitaxy approach embodied by Raytheon and MIT. Northrop Grumman has selected a micrometer scale integration approach where GaN and InP devices are fabricated on individual wafers which are then diced into chiplets. These are then placed on a CMOS carrier chiplet, interconnected with several HICs on each chiplet in a manner similar to the wafer-level approach. While this approach creates the largest degree of segregation between the III-V and CMOS devices, the authors point out that it allows a decoupled line yield, as devices from each semiconductor process can be tested before heterogeneous integration. From a thermal point of view, this approach is also the most amenable to thermal isolation efforts since the disparate devices are contained within their own chiplets rather than more widely dispersed. Some thermal modeling of the NGAS design is performed by Harris, et al. [8]. Modeling chiplets that contain single GaN high electron mobility transistors (HEMT) or InP heterojunction bipolar transistor (HBT), they find that the transistor temperature rise is about 145 °C for GaN and less than a degree for InP. They do not report CMOS temperature rise in the vicinity of the GaN chiplets. 10 To observe an existing treatment of thermal isolation on an HI system one must look outside the DAHI program. Cho, et al. [9] considered the thermal isolation of a microprocessor from temperature sensitive memory modules in a mobile electronics application. Normally mounted on a silicon interposer, these two chips have a high degree of thermal “cross talk.” Through finite element modeling, the authors found that using a glass interposer would provide a higher degree of thermal isolation between the two chips, with thermal vias helping to provide a conductive path through the thickness of the interposer for dissipated heat. The authors have since published experimental results for thermal behavior of thermal via arrays in glass interposers [10, 11], but have not yet experimentally demonstrated the isolation effect between two thermally disparate components. Such a demonstration is one chief aim of this project. 3.2 Fabrication of Via Arrays Given the choice of relying on thermal via arrays for managing the temperature rise of the high power components in this dissertation’s HI application, it is important to survey the methods used to fabricate these arrays. Since the literature for fabrication of vias in silicon is much more mature [10], this review will restrict itself to fabrication in glass substrates. Tummala, et al. [12], provides a brief overview of hole formation methods; they include electric discharge, laser ablation, and “photo-via” formation in photosensitive glass. Limits on the minimum hole diameter for each method are driven by the thickness of the glass substrate used. In the authors’ overview, holes as small as 20 µm diameter in 100 µm thick glass wafers were achieved using electric discharge, 10 µm diameter in 30 µm thick glass by excimer laser ablation, and 14 µm holes in UV- sensitive glass (thickness not stated). Sukumaran, et al [13], provides additional detail on 11 laser ablation methods and possible applications for 15 µm diameter vias in 30 µm glass. They were also able to demonstrate copper redistribution layers (RDL) of 4 µm line width at a pitch of 10 µm Corning Glass [14, 15] uses proprietary methods to fabricate holes down to 20 µm in 100 µm thick glass. One advantage the company claims is the ability to manufacture 300 mm diameter glass wafers with a falling film technique that results in a very low average roughness without the need for polishing. This helps to limit the possible size of surface flaws in the glass substrate, one of the failure mechanisms for stress or fatigue induced brittle fracture. Discussions with Corning elicited a recommendation for a minimum via pitch-to-diameter ratio of 2:1. The filling of the via holes with conductive material generally follows a process of electroless copper seed layer deposition, followed by electroplating copper. The target copper thickness on the insides of the via holes is typically 6-8 µm [12, 13]. It can be difficult to completely fill via holes with copper without build up at the hole entrance leading to choking at the entrance and a resulting void in the body of the via. 3.3 Reliability of Via Arrays Also important for the eventual application of via arrays for thermal isolation is their reliability under thermomechanical stress. Due to the CTE mismatch between substrate and hole metallization, vias can fail - due to a variety of factors intrinsic to the array and substrate – prior to failures of the larger system. Because publications on glass via array reliability are sparse, several works on reliability in through-silicon vias are included in this section. 12 Tong, et al. [16], derive analytical relations for the hoop stress in a silicon substrate based on two-dimensional plane stress and plane strain approximations. While the stress from a single TSV does not depend on TSV diameter (since the larger CTE induced strain from larger vias is exactly offset by the larger circumference available to absorb that strain), the pitch of adjacent TSVs does play a significant role. This is because the stress fields of nearby TSVs could overlap, creating high stress regions along the lattice vectors of the array. Suhir [17] pursues a similar treatment, while also suggesting the use a compliant strain buffer layer at the interface of the via and silicon to reduce the stresses at the interface. Kumar, et al. [18], provides an example of an investigation into the effects of the thermal strain generated in the direction along the via axis. When a copper via is heated, since it expands relative to silicon (or glass), the via will tend to extrude up and out of its hole. Under particular conditions the via can creep at the via/substrate interface, resulting in the extrusion becoming permanent even upon return to the original temperatures. Concluding this section, mention is made of Demir, et al. [19], who performed accelerated lifetime testing of through-glass vias. Formed by excimer laser in 180 µm thick glass, the 60 µm diameter conformal (plated) vias were subjected to -55°C to 125 °C temperature cycling, as well as an electrical bias test for electromigration. The only failures the authors found they attribute to plating process defects. 3.4 Modeling of Thermal Via Arrays – Top-down Approaches Top-down thermal modeling approaches for via arrays are characterized by the sectioning of the array into representative unit cells, and applying a finite element approach to these unit cells to extract effective behavior. Since FEM is being used, these 13 unit cells often contain as much detail as possible with regards to the via construction, presence of interfacial layers, and sometimes materials or interconnections above or below the via array substrate. This level of detail increases the fidelity of the model for the array being considered, but as a result requires a fresh effort to design and mesh the unit cell for each new application. One of the earlier examples of this modeling approach is exhibited by Chein, et al. [20]. The authors calculate an equivalent thermal conductivity for their TSV arrays by applying equal input and output heat fluxes at opposite cell faces to create first a cross- plane (along-via-axis) heat flow then an in-plane flow (perpendicular to the via axis). For their cross-plane models, the authors apply 500 W/m-K “buffer blocks” to the top and bottom surface, on the outside of which the heat flux boundary conditions are applied; see Figure 2. This is done to “smooth the heat flow” as it enters and exits the cell. Since the authors compute their effective conductivity in this case using a 2 µm slice of the model at the cell midplane, far from the buffer blocks, they argue that the exact nature of the blocks does not impact the result, while allowing them to handle the non-planar surface presented by the via pads overlying the wafer surface. Relatively unique among top-down approaches, the authors then proceed to model a survey of 500 different cells composed of different via diameters, lengths, pitch, and oxide thicknesses, presenting empirical equations determined by curve fitting the data. 14 Figure 2: Side view of a top-down via unit cell, vertical conductivity Cho, et al. [9], adopt this approach – complete with buffer blocks – to determine effective conductivity for via arrays in glass interposers and compare them against via arrays in silicon. Recognizing that vias formed in glass frequently have a larger entrance diameter than exit diameter, they model their glass vias using a conical copper cross- section. As the authors are interested in a specific application, they constrain their interest to a single array arrangement for glass and for silicon. A final example of a top-down approach is the treatment by Santos, et al. [21], of lateral thermal blockage due to TSV arrays. These authors are interested in the deleterious effect of the oxide layer present between copper vias and their silicon matrix on lateral effective conductivity. They find that despite the high conductivity of copper, the oxide layer prevents easy conduction through the via, resulting in a lower lateral effective conductivity than bulk silicon, creating a lateral thermal bottleneck that leads to higher device temperatures. 15 A frequent relationship between via parameters and array effective conductivity in the through-substrate (𝑧) direction found in the literature is the rule-of- mixtures: 𝑘𝑒𝑓𝑓,𝑧 = 𝜙𝑣𝑘𝑣 + 𝜙𝑜𝑥𝑘𝑜𝑥 + (1 − 𝜙𝑣 − 𝜙𝑜𝑥)𝑘𝑠 (1) where 𝑣, 𝑜𝑥, and 𝑠 subscripts correspond to the via, interfacial oxide (when present), and substrate, 𝜙 is the (areal) fill fraction, and 𝑘 the material thermal conductivity. As will be discussed in Chapters 0 and 0, this relation does not always represent the appropriate effective conductivity of the array. 3.5 Modeling of Thermal Via Arrays – Bottom-up Approaches Contrasted with top-down models, bottom-up approaches rely on simplified array unit cells and attempt to construct physics-based relations for vertical and/or effective thermal conductivity. They are often more concerned with determining the general behavior of cells as a function of array parameters than focusing on one specific array in a particular application. Since they rely on simplified cells and other assumptions, along with the greater generality there can be a loss in accuracy compared to a more detailed, application-specific model. An early example of a bottom-up approach is in Lee, et al. [22], a treatment of conformal vias in printed circuit boards. The authors use a thermal constriction treatment to derive the effective vertical conductivity, treating the organic board material as a volume with zero thermal conductivity. The thermal constriction then exists from the pads of the individual vias to the hollow cylinder of the via barrel. Li [23] performs an analysis on solder filled plated through-holes in PCB, using an analysis that relies on series and parallel thermal resistances for each material in the through-hole unit cell. 16 Liu, et al. [24], analytically treats the lateral effective conductivity of a through- silicon via array. Identifying the interfacial oxide as an important factor, they segment the unit cell into five regions, four comprised of solely silicon away from the via, and one a square-sectioned region just containing the cylindrical via. They neglect the contribution of the silicon in the corners of this sections and derive an expression for the resistance across the oxide and copper via. This is assembled back into the larger cell using series and parallel resistances. They then calibrate their model using FEM. A last example is provided by Zhang, et al. [25], in their modeling of TSV arrays. While they use a cross-section-based rule-of-mixtures to compute vertical conductivity (a typical assumption), the work is notable in their use of the Maxwell-Eucken Equation (described in [26]) for estimating lateral conductivity. They point out that this is equivalent to assuming the vias can be treated as spherical inclusions suspended in a silicon matrix. 3.6 Experimental Characterization of Via Arrays In a similar vein to reliability publications, thermal experiments on via arrays in glass are limited, while there is much more literature available for arrays in silicon and other systems that behave in a similar manner (PTH in PCB, ball grid arrays, etc.). The primary focus is on the possible methods that can be used to evaluate the thermal characteristics of arrays. A first notable work is that done by Yamaji, et al. [27], using a laser flash technique to measure the thermal resistance between stacked silicon die. The authors claim an accurate measurement of the resistance of an underfilled bond between two silicon samples, but are unable to detect a significant (relative to uncertainty) change 17 when the silicon is equipped with a copper via array that does not penetrate into the underfill. They do detect a change when gold microbumps are inserted between the die in the underfill region, but had particular difficulty in applying laser flash to the “heterogeneous specimens” presented by the gold/underfill medium. Matsumoto and Taira [28] measured the thermal resistance of a C4 solder bump array joining two silicon surfaces using a steady state ASTM-style thermal interface test. While their measurements are on a C4 array of 100 µm ball at a 200 µm pitch, they include in their modeling a variety of ball sizes, with and without underfill. They note in their modeling that assuming a homogenized interfacial layer using a rule-of-mixtures for the solder and air or underfill results in an underprediction of the layer resistance. A final publication, by Cho, et al. [11], evaluates the effective vertical conductivity of conformal via arrays in glass substrates. The measurements are performed using IR thermography on samples heated from below, and corrected with an estimated loss through the exposed upper surface through convection and radiation. The authors note significant discrepancies between experimental results and FEM calculations done along the lines of Chien, et al. [20] for the samples that have the largest vias and pitch dimensions. The authors attribute this to poor copper plating alignment in those samples, although the absence of a microspreading resistance in Chein’s methodology may provide an alternative explanation. 3.7 Thermal Constriction Resistance Thermal constriction resistance – also called spreading resistance – is a phenomenon that arises when heat is introduced into a material through a localized zone or “hotspot”. Very early treatments on the subject by Mikic [29] and Yovanovich [30] 18 were motivated by investigations into the underpinnings of the thermal contact resistance between material surfaces with defined surface roughness. While the underlying geometric problem exists in other fields, these authors laid the foundation for the concepts and terminology used to determine the rate of heat transfer through such configurations. The essential treatment of the subject is well described by a comprehensive review by Yovanovich [31]. The temperature rise of a localized hotspot on the surface of an infinite half-space can be related to the flux introduced at that spot with a thermal resistance 𝑅𝑇. When reducing the half-space to a finite volume, e.g. the base of a finned heatsink or a thin thermal spreader, it is convenient to decompose this total resistance into a one-dimensional resistance defined by the dimensions of the volume, 𝑅1𝐷, and a spreading resistance, 𝑅𝑆, that accounts for the constriction effect produced by the spot. If the spot area is allowed to fill the entire area of the material surface, 𝑅𝑆 goes to 0. Thus, 𝑅𝑇 = 𝑅1𝐷 + 𝑅𝑆 where 𝑅1𝐷 = 𝐿 𝑘𝐴𝑣𝑜𝑙 + 1 ℎ𝐴𝑣𝑜𝑙 (2) Muzychka et. al. [32] investigated thermal constriction resistance in orthotropic heat spreaders. One method they use to simplify the system to be solved is to mathematically transform one or more spatial coordinates in order to recover an isotropic heat spreader from an inherently anisotropic medium. In the interposers considered in this project, where 𝑘𝑧 > 𝑘𝑥𝑦, the appropriate coordinate transform would result in a system that is either stretched laterally or compressed vertically. For this dissertation’s purposes, the lateral transformation better facilitates comparisons between interposers 19 with comparable vertical conductivity but with contrasting lateral conductivities. Thus, the lateral coordinate, 𝑥, is transformed: ?̅? = 𝑥 √𝑘𝑥/𝑘𝑧 (3) In systems with complex geometry – like the HI case study system – this transformation can lead to an issue. Isotropic components like the bulk of the amplifier chiplet and its die attach layers become anisotropic. To rectify this, the heat introduced through these components is modeled as an idealized hotspot with a specified flux profile. Negus et. al. [33] note that using equivalent circular hotspots with radii 𝑎 = √𝐴𝑠 𝜋⁄ (with 𝐴𝑠 the area of the hotspot) introduces acceptably low error. Leveraging the work of Yovanovich [30], a flux profile of the form 𝑓(𝑢) = 𝑄 2𝜋𝑎2 (1 − 𝑢2)𝜇 (4) can be used, where 𝑢 = 𝑥/𝑎 is the relative position from center (at the chip- interposer interface), 𝑄 the total heat rate in W, and 𝜇 is the flux shape parameter. For an isoflux profile 𝜇 = 0 is used, while for a profile that produces an isothermal interface 𝜇 = −1/2. The FEM derived profiles for both example interposers lie between these theoretical profiles. Yovanovich et.al. [31] note that the isothermal interface condition provides a lower bound for computing the thermal constriction resistance (and thus average chip temperature), while the isoflux interface provides a upper bound, citing an 8% maximum discrepancy between the two for systems with circular hotspots. Song et. al. [34] provide very simple, approximate, closed-form expressions for constriction resistances based on both average and maximum hotspot temperatures for circular hotspots with constant flux. Their expression for dimensionless constriction 20 resistance, 𝜓 = √𝜋𝑘𝑎𝑅𝑐 is: and 𝜓𝑎𝑣𝑒 = 1 2 (1 − 𝜖)3/2𝜑𝑐 (5) 𝜓𝑚𝑎𝑥 = 1 √𝜋 (1 − 𝜖) 𝜑𝑐 (6) where 𝜑𝑐 = 𝐵𝑖 tanh(𝛿𝑐𝜏) + 𝛿𝑐 𝐵𝑖 + 𝛿𝑐 tanh (𝛿𝑐𝜏) and 𝛿𝑐 = 𝜋 + 1 √𝜋 𝜖 𝐵𝑖 = ℎ𝑏 𝑘 𝜖 = 𝑎/𝑏 𝜏 = 𝑡/𝑏 They assert that these correlations agree with full analytical solutions “to within 10% for the range of parameters commonly found in microelectronics applications,” though changed dimensions and material sets in the past few decades necessitate a re- evaluation of that statement. Since for this discussion the hot chip is assumed to be far from the edges of the interposer, multiplying 𝜑𝑐 by 𝜖/𝜖 and taking the limit as 𝑏 → ∞ results in with 𝜓𝑎𝑣𝑒 = √𝜋 2 𝜓𝑚𝑎𝑥 = 1 2 𝜑𝑐 (7) 𝜑𝑐 = ℎ𝑎 𝑘 tanh ( 𝑡 √𝜋𝑎 ) + 1 √𝜋 ℎ𝑎 𝑘 + 1 √𝜋 tanh ( 𝑡 √𝜋𝑎 ) (8) 3.8 Summary of Literature HI manufacturing and design techniques have been recognized as an important development in advancing the performance of next-generation systems. Also understood is a need to address the thermal management issues that arise due to the disparate thermal operating conditions of the heterogeneous devices. Thermal-via arrays – and in particular 21 arrays in low-conductivity substrates – have be identified as one possible component of a thermal isolation strategy that attends to these heterogeneous thermal conditions. Modeling of the thermal interactions both within these arrays and with their surroundings is done both numerically, through FEM, and analytically using first principles. FEM approaches tend to be top-down, in that they capture significant detail about given array features and provide effective properties, but often do not provide direct insight into how variation of those features affects resulting properties. Analytical approaches are more difficult to construct and require simplification of the array unit cell, but as bottom-up approaches they can identify important trends and non-dimensional groupings that enhance understanding of the array behavior. The conduction that occurs as heat enters the via array and substrate from a device footprint has close connection with the theory of thermal constriction resistance. This area of study has a substantial body of analytical models that describe the geometric penalty associated with conduction across an abrupt change in cross section, such as the one created by a small footprint device bonded to a larger area interposer. This can provide a method of modeling the impact of tuning various effective properties of the via- enhanced interposer. Additionally, at the scale of each via a similar geometric constriction occurs. In fact, in the limit of zero substrate conductivity the local conduction reduces to these classic constriction resistance solutions. Missing from the literature is the generalization to the case of non-zero substrate conductivity, which is provided in this thesis. Finally, absent from the literature is a definitive demonstration of a via-enhanced low-conductivity interposer outperforming widely available bulk silicon. Demonstrating 22 a practical interposer leveraging thermal isolation to reduce sensitive device temperature is the primary experimental aim of this dissertation. 23 4.0 THERMAL ISOLATION MODELING This chapter describes the modeling work in support of this dissertatation. The first subchapter introduces the case study that forms the basis of the HI thermal isolation application. The system considered is modeled using FEA, including the detail of individual thermal vias. The second subchapter concerns finite element modeling of individual via unit cells, initially undertaken as a top-down, equivalent thermal conductivity approach. It is here that microspreading resistance is identified, defined, and analyzed. The third subchapter describes an analytical model of microspreading resistance, where the unit cell vertical resistance boundary value problem is outlined and solved. The final subchapter models the anisotropic thermal constriction problem associated with the original thermal isolation application. It distills the multitude of parameters that describe the system into the minimal set necessary to distinguish substantially different incarnations of the isolation problem, providing a compact parameterization of the available design space. Case Study: Thermal Isolation of Heterogeneously Integrated Systems The anchor point of this project is a numerical case study on the feasibility of a via-enhanced low-conductivity interposer for a high power heterogeneous system. As described in the literature review, a major advantage of heterogeneous electronic systems is the ability to design a composite device where the individual constituent components are fabricated in the semiconductor best suited to them. The prototypical example for our case study is a power amplifier fabricated in gallium nitride with silicon CMOS control logic. The fast switching HEMTs in the GaN dissipate substantially more heat than the lower power CMOS components, leading to considerable spatial variation in dissipated 24 power throughout the package. The GaN components can also tolerate higher operating temperatures (as high as 250 °C, compared with 70 °C for commercial CMOS) without suffering performance or reliability degradation. Without a strategy of thermally isolating the different components, heat generated in the GaN will diffuse into the silicon, necessitating a cooling solution that essentially cools the entire package to temperatures near the maximum safe temperature of the CMOS logic. The ability to isolate components with different thermal requirements with a via enhanced low-k interposer was demonstrated for a consumer electronics application [9]. The case study in this project examined whether such an approach could work for the much higher heat loads associated with HI amplifier systems, and more importantly its amenability to integration with microfluidic cooling. It proposed a new “differential” cooling strategy, where a baseline fluid cooling approach would be applied to the underside of the interposer, except in high power regions where a more intensive cooling solution would be implemented. The study considers a fluid microgap cooler as this baseline, and a manifold-fed microchannel cooler as the aggressive, site-specific solution. As discussed in the last chapter, there are many approaches to heterogeneous integration. An approach where the amplifier and control logic are fabricated on one contiguous silicon substrate was discarded after initial finite elements models demonstrated the difficulty of thermally isolating the devices with such a strategy.1 The additional thermal pathway traveling laterally through the silicon substrate meant that regardless of the interposer or underside cooling strategy, maintaining substantially different temperatures in the amplifier and logic was unfeasible. Thus, a chiplet based 1 See Appendix A for images of supplemental case study models. 25 system became the focus of the study. The final system configuration chosen is shown in Figure 3. Two amplifier chiplets of GaN on silicon flank a central silicon CMOS chip. All three are mounted on a glass interposer, the thickness of which is 200 µm. A copper via array is inserted in the volume underneath the amplifiers, and convection boundaries applied to simulate the fluid cooling; a high convection coefficient of 30,000 W/m2-K is applied under the arrays to represent the heat removal capability of the microchannel cooler while the remaining microgap region is set to 3,000 W/m2-K. These value were chosen based on published effective base heater transfer coefficient for single-phase microcoolers in literature. Table 1 summarizes representative performance of single-phase water microchannel and microgap coolers (and provides references for each). It demonstrates that microchannel coolers offer substantially higher base-equivalent heat transfer, owing to the much higher wetted surface area. This comes at the cost of higher pumping power as well as more complex architecture and fabrication. Table 1: Base-Equivalent Cooling and Pumping Cost of Single-Phase Water Microcoolers Microchannel Coolers Microgap Coolers ℎ [W/m2-K] Areal Pump Power [W/cm2] ℎ [W/m2-K] Areal Pump Power [W/cm2] 115,000 [35] 0.04 15,400 [36] 0.0011 182,000 [37] 0.1 24,000 [36] 0.133 417,000 [37] 10 26 Figure 4 provides the dimensions of the via array and Figure 5 presents a rotated view of the system, providing the chiplet power dissipation and convection coefficients used. Dimensions and power dissipation for the amplifier chiplets are representative of GaN on SiC monolithic microwave integrated circuits (MMICs) [38-40]. To analyze this system, a quarter-symmetry finite element model was constructed using the commercially available FE software package ANSYS [41], with heat flux applied to the free surface of the chiplets such that the total heat entering each chip matched the target dissipation, and convection boundaries communicating with a fluid of Figure 3: Layout for HI Case Study Figure 4: Array Parameters for Vias Chiplet Thickness Interposer 10.4 W 100 mW Microchannel 30,000 W/m2-K Microgap 3,000 W/m2-K Amplifier CMOS Amplifier Microchannel 10.4 W 27 reference temperature zero applied to the underside. In meshing the model, very fine element sizes were required in and around the copper vias. After performing a mesh convergence study, the resulting mesh contained just over 300,000 high-order hexahedral elements. Within the individual vias, zone refinement resulted in elements of nominal dimensions of 10 µm x 10 µm in cross section, with 16 µm height along the thickness of the substrate. Far from the via array, elements possessed cross sectional dimension of 125 µm square, with a 16 µm height. For material properties a temperature independent conductivity was assumed to expedite initial modeling; the values used are presented in Table 2. Figure 5: Rotated view of HI case study system showing input power and underside cooling. Vertical scale exaggerated. Several variations on this model were investigated, where the thickness of the interposer was varied, the site specific cooling was set to microgap values, or the via array removed. All these changes had the expected effect: thinner interposers provided better isolation due to a lower lateral cross section and removing the high cooling coefficient and/or vias dramatically increased the temperature of the amplifier.2 Figure 3 and Figure 4 show simulation results for the baseline 200 µm glass interposer with vias 2 Demonstration of thinner case study interposers is presented in Appendix A. 10.4 W 100 mW Microchannel 30,000 W/m2-K Microgap 3,000 W/m2-K Amplifier CMOS Amplifier Microchannel 10.4 W 28 and differential cooling compared against the results for the same systems where the glass has been replaced with silicon. In the model using glass, the amplifier peak temperature rise (relative to the fluid) reached 113 K, while the CMOS temperature rose on average only 5 K. With silicon, however, the amplifier temperature increase fell to 56 K, while the CMOS average rise increased to as high as 40 K. Given the assumed safe operating temperatures of 250 °C for the amplifier and 70 °C for the CMOS, the silicon interposer would limit the coolant temperature to 30 °C while the glass interposer would allow a coolant temperature of 60 °C. Since the ultimate sink for the dissipated heat is the local ambient, tolerating high coolant temperatures at the interposer enables reductions in the size and power consumption of the systems responsible for rejecting the coolant heat to the environment: e.g. radiators on automobiles and spacecraft can be reduced in size. Alternatively the coolant loop responsible for the HI system may also be responsible for cooling other systems, such as the engine on an automobile or aircraft, that causes an elevated coolant temperature. Table 2: Material Properties for HI Case Study Material Thermal Conductivity Silicon 150 W/m-K Glass 1 W/m-K Copper 400 W/m-K Sintered silver die attach 200 W/m-K Silver metallization 401 W/m-K 29 Figure 6: System in package with glass interposer, thermal via array, and differential cooling Figure 7: System in package with a silicon interposer, thermal via array, and differential cooling The case study identified what is simultaneously the challenge and advantage of this low-k interposer approach: The interposer constrains the heat dissipated by the high- power components to a small footprint within the package. This creates a local hotspot on the underside of the interposer, where the large temperature difference from the fluid drives the convective heat removal. The approach relies on this difference to compensate for the effective loss of heat removal area since the footprint over which the significant heat removal occurs is reduced. The challenge then is to balance the constraining of dissipated heat with the available convection coefficient for a particular cooling solution. Complicating this classic heat transfer problem is that constraining this heat to a small area is the main objective of the thermal isolation. Thus, constrain the heat to too small 30 an area and the available ℎ𝐴 will lead the amplifier temperature to rise above allowable levels. Fortunately, since the other regions of the interposer need very modest heat removal rates, a more economical cooling solution can be employed for regions far from the hotspot. In order to better explore ways to optimize the design of the interposer and site- specific cooling system, modeling efforts turned to equivalent conductivity methods to simplify the finite element models of the system. In this way, rather than needing to adjust and refine a very fine mesh for each geometry or array parameter change, the equivalent conductivity could simply be altered. It is this type of analysis that is presented in Chapter 4.2. However, in order to determine the appropriate equivalent conductivity to use, modeling at the array unit cell level must to be performed. As will be shown in Chapter 0, the interaction of the convection boundary on the underside of the interposer leads to cell responses not well handled by existing equivalent conductivity methods. Creating a Compact Thermal Model As may be inferred from Figure 5, there are a multitude of parameters necessary to describe even a simple HI system. The dimensions, locations, power outputs, and safe operating temperature of the individual components; the dimensions and material properties of the interposer as well as the particulars of the TXV array; the conductance of the embedded cooler; and even details concerning the method of die attach all play a role in the reliable operation of the system. Of value is a simplified model of the system, where the large parameter space is reduced to a minimal set of important factors. Ideally, this model will be able to clearly 31 illustrate the design tradeoffs available within an application. It will also highlight that the interplay between increasing isolation leading to decreasing effective cooler footprint is a result of the underlying heat transfer mechanism: that of a thermal constriction problem. By analyzing the simplified model in the context of thermal constriction, the parametric space described by the input design parameters can be linked to the response of the interposer and its hosted devices. This chapter will first introduce the simplified system representing a high power central chip giving rise to a temperature field across the interposer. This central source is referred to as the amplifier (subscript “amp”) in reference to the GaN HEMT device in the case study of Chapter 4.1, but it could represent the highest power device in any heterogeneous system (e.g. the processor in an integrated microprocessor/memory system-in-package). The temperature sensitive devices are referred to as CMOS in reference to the silicon control logic devices of the case study, but again this is a generic term of convenience for the components that represent the strictest operating temperature limitation (e.g. the volatile memory in the alternate example). The second section describes the analytic treatment of the simplified model using solutions developed in the literature for thermal constriction resistance. Confronting the anisotropy of the interposer requires a transformation of coordinates. A discussion of the required number of terms in a finite series approximation of the solution is provided, noting that for the geometry of the particular model studied, high interposer anisotropy requires more and more terms for the temperature field to converge. The third section analyzes the same system using FEM, and presents results of a model survey across varying interposer anisotropy for four cases: low underside 32 convection with an isoflux hotspot, high underside convection with isoflux hotspot, low underside convection with isothermal hotspot, and high underside convection with isothermal hotspot. The fourth section discusses how the interposer temperature field (computed by either thermal constriction solutions or FEM) can be used to analyze design tradeoffs inherent in choosing interposer effective properties. It demonstrates how the limiting thermal operating characteristics of the two classes of heterogeneous devices can be used to define a single metric Θ𝑐 that describes how thermally “tight” the system is – that is, the degree to which the heterogeneous devices need to be isolated. This, coupled with the power dissipation of the central chip and the thermal coupling function belonging to the interposer describe the available parameters that are balanced in the thermal isolation of the two chips. 4.2.1 Reduction of Parameters Firstly, the via-enhanced interposer will be homogenized according to procedures typical of the literature [9, 11, 20, 21, 42].3 This is assumed to result in an orthotropic material, with effective conductivities 𝑘𝑟 and 𝑘𝑧 in the in-plane (lateral) and through- plane (vertical) directions, respectively. These properties will be assumed to persist across the entire extent of the interposer; whether to omit vias in particular regions of an actual application (either for engineering or cost-related reasons) can be assessed retroactively analogously to section I-C. To create consistency across different manifestations of the constriction problem, these conductivities will be assumed to be independent of temperature. 3 More detail of this process – including the novel inclusion of microspreading resistance – is presented in Chapters 0 and 0. 33 The effective properties of the via array can also be adjusted to take into account via microspreading resistance. This skin-effect can be modeled as a planar thermal resistance within the compact model, and its development is described in Chapters 0 and 0. These resistances (which are associated with the individual via unit cell and carry units of K/W) can be converted to areal surface resistance (thermal impedance) by multiplying by the cell cross sectional area, e.g. 𝑃2, where 𝑃 is the pitch of an aligned via array. Independent microspreading resistances can be associated with the interposer underside, 𝑅𝑙, and with the upper interface with a heated chip, 𝑅𝑢. Because the power dissipation of the central chip (e.g. amplifier) is orders of magnitude larger than the sensitive devices (e.g. CMOS), the waste heat from the CMOS will be neglected. Geometric effects due to the presence of the CMOS chiplet will be ignored by removing the CMOS and its die attach, instead assuming that temperatures in the CMOS will be tightly correlated to local surface temperatures on the bare interposer. The underside cooling will be assumed uniform as outlined in Section I-C. Furthermore any lower microspreading resistance can be combined with underside cooling coefficient to form an effective conductance by ℎ∗ = [ 1 ℎ + 𝑃2𝑅𝑙] −1 . (9) Because 𝑅𝑙 depends on ℎ and other details of the cooler, as well as the particular via array chosen, it is this ℎ∗ which will be held fixed, with the understanding that the actual cooler ℎ may need to be increased to compensate for microspreading. The next step is to circularize the system. For systems where the heat source (amplifier) dimensions are less than half the substrate lateral dimensions, the discrepancy between thermal constriction resistances calculated for rectangular vs circular systems is 34 negligible [43]. This is an assumption that the amplifier chip is in the center of its area of influence. Referring to Fig. 1, by symmetry each amplifier sees an adiabatic boundary at the midplane separating them. Within each half interposer, the amplifier chiplets are indeed eccentrically located. While this means that edge effects will come into play at differing points, treating them as centrally located reduces the complexity of the model. (There do exist extensive treatments on eccentric and/or rectangular thermal constriction systems; see [44] for example) The circularization is done by treating the amplifier and interposer as disks with effective radii 𝑎 = √ 𝐴𝑎𝑚𝑝 𝜋⁄  (10) and 𝑏 = √ 𝐴𝑖𝑛𝑡 𝜋⁄ , (11) respectively, located about a common axis of symmetry. For the purposes of evaluating required device separation this change is more problematic, since for highly isolated systems these distances are very close to the edge of the amplifier. This reduction in geometry will lose some positional information, e.g. separation will need to be greater at an edge midpoint vs. a corner of a rectangular heat source. However, since the assumption that the homogenized via array is circularly orthotropic creates similar issues, in reality not much more is lost when considering distances that are already on the scale of the via array. As with all of the simplifications being made in this section, the resulting model will point to promising design choices that must be validated with a detailed, hi-fidelity analysis. The final simplification is the replacement of the amplifier chiplet itself with a hotspot of equal radius and total output power. In order to relate the peak amplifier temperature with the temperature of the hotspot centroid, details concerning the amplifier 35 thickness, material, die attach, and upper spreading resistance, 𝑅𝑢, will be subsumed into a single resistance, 𝑅𝑎 ∗ . This resistance relates the temperature difference between the amplifier peak and the hotspot centroid to the amplifier output power. An example calculation for a top-dissipating, rigid die attach chiplet is 𝐴𝑎𝑚𝑝𝑅𝑎 ∗ =∑ 𝑡𝑖 𝑘𝑖 𝑖 + 𝑃2𝑅𝑢 (12) where the summation is across the chiplet substrate and various die attach layers, and 𝑡𝑖 and 𝑘𝑖 are the thicknesses and conductivities of the layers. A more general procedure to calculate 𝑅𝑎 ∗ will be omitted; it is often in the range of 0.2 – 1 K/W for typical applications, and can be obtained as detailed in Chapters 0 and 0. The exact flux distribution to use across the hotspot also depends on the same features used to define 𝑅𝑎 ∗ . If a thick chiplet with a conductive substrate is attached with a high-resistance attach, the chip will be encouraged to thermalize laterally prior to conducting into the interposer. This will lead to an isothermal spot, where the heat flux entering the interposer near the edge of the amplifier is greater than at the center. Conversely, a very thin, flip-chip mounted amplifier with low attach resistance will immediately dissipate the majority of its heat into the interposer; if the power map of the amplifier is uniform, the hotspot will be isoflux. Rather than focus on the details of determining the exact flux profile, this analysis will consider first an isoflux and then an isothermal spot and present them as limiting cases that bound the majority of profiles seen in practice. After all these simplifications, the geometry of the simplified system to be analyzed is given in Figure 8. This is the system as it will be modeled using thermal constriction solutions and FEM, with convection to a zero fluid temperature and either an 36 isoflux spot of 500 W/cm2 (25 W total) or an isothermal spot of 1 °C relative to the fluid and total heat rate measured. Two effective cooler conductances, ℎ∗, are chosen: 30,000 W/m2-K and 100,000 W/m2-K. Within these four scenarios, 𝑎, 𝑏, and interposer thickness 𝑡 are fixed at the values in Figure 8, and 𝑘𝑧 held constant at 150 W/m-K. 𝑘𝑟 is allowed to vary from 0.1 W/m-K to 1000 W/m-K. In this way the model provides results that can be ascribed to such diverse interposers as silicon (isotropic 150 W/m-K), a via-enhanced glass (𝑘𝑟 in the vicinity of 1 – 2.5 W/m-K, 𝑘𝑧 = 150 W/m-K: quite high, but eventually obtainable with a close-packed copper via array with diameter-to-pitch ratio of 0.65), and finally – as a point of comparison – a hypothetical spreader with very high lateral conductivity. Figure 8: Axisymmetric constriction model for anisotropic interposer. 4.2.2 Analytic Treatment of Thermal Constriction A substantial body of literature has been published on the analytical solution to the thermal constriction problem. Originally motivated by investigations into thermal contact resistance between surfaces with a known roughness [29, 45], it has expanded to include applications such as finned heat exchanger baseplates, thermal spreaders for small area heat dissipation, and electronics components on PCBs [22]. Solutions have been obtained for both two-dimensional rectangular and axisymmetric systems, as well as 1.26 mm 2.82 mm 200 µm C L h 37 three dimensional rectangular systems [44, 46]. An excellent review of much of the work concerning axisymmetric systems is provided by Yovanovich, et al., [31]. For dealing with the homogenized interposer in this application, an extension to systems containing an orthotropic layer is provided by Muzychka, et al.,[32]. It takes advantage of a coordinate transform that results in an equivalent problem within an isotropic medium. (The following is a synthesis of the notation used in [31] and [32].) The transform is on the vertical coordinate, and is 𝑧̅ = 𝑧 √𝑘𝑧 𝑘𝑟⁄ , (13) 𝑡𝑒𝑓𝑓 = 𝑡 √𝑘𝑧 𝑘𝑟⁄ , (14) and 𝑘𝑒𝑓𝑓 = √𝑘𝑟𝑘𝑧 . (15) where 𝑧 is the transformed vertical coordinate, 𝑡𝑒𝑓𝑓 is the effective interposer thickness, and 𝑘𝑒𝑓𝑓 is the effective (isotropic) interposer conductivity. Since for this application the peak amplifier temperature (which has been defined with respect to the hotspot centroid temperature) is of interest, the interposer resistance to be defined is with respect to the Δ𝑇 between the hotspot centroid and the fluid. Since the interposer edges are adiabatic, this is given by Δ𝑇𝑐 = 𝑄 𝜋𝑏𝑘𝑒𝑓𝑓 ∑ 2𝐽1(𝛿𝑛𝜖)𝜑𝑛 𝜖 𝛿𝑛2 𝐽0 2(𝛿𝑛) ∞ 𝑛=0  (16) for isoflux spots and Δ𝑇𝑐 = 𝑄 𝜋𝑏𝑘𝑒𝑓𝑓 ∑ sin(𝛿𝑛𝜖)𝜑𝑛 𝜖 𝛿𝑛2 𝐽0 2(𝛿𝑛) ∞ 𝑛=0  (17) 38 for isothermal spots. Key quantities are the relative spot radius 𝜖 = 𝑎/𝑏, total spot power 𝑄, and the end cooling function 𝜑𝑛 = 𝛿𝑛 + 𝐵𝑖 tanh(𝛿𝑛𝜏) 𝐵𝑖 + 𝛿𝑛 tanh(𝛿𝑛𝜏) , (18) where 𝐵𝑖 = ℎ∗𝑏/𝑘𝑒𝑓𝑓 and 𝜏 = 𝑡𝑒𝑓𝑓/𝑏. 𝐽0 and 𝐽1 are Bessel functions of the first kind with order zero and one, respectively, and the eigenvalues, 𝛿𝑛 are the roots of 𝐽1(𝛿) = 0. The first root is 𝛿0 = 0; in computing the first term in the summations (16,(17), employing the limit as 𝛿1 → 0 + will yield the correct result. This term is related to the one-dimensional resistance of the interposer, and can be obtained using Δ𝑇𝑐,0 = 𝑄 [ 𝑡𝑒𝑓𝑓 𝜋𝑏2𝑘𝑒𝑓𝑓 + 1 𝜋𝑏2ℎ∗ ] . (19) Thus the eigenvalues for 𝑛 = 1, 2, … are the positive roots of 𝐽1(𝛿). The results of this summation gives way to the constriction resistance, given by 𝑅𝑐 = Δ𝑇𝑐/𝑄 . (20) This resistance calculation was performed for the system parameters described in Figure 8, the results of which compared favorably to the FEM-based calculation, described and presented in Section 4.2.3. Including 6 terms resulted in agreement with FEM to within 1% for many values of 𝑘𝑟. However, for the lowest values of 𝑘𝑟 (as 𝑘𝑒𝑓𝑓 and 𝜏 tend to zero), more and more summation terms are needed to reach a satisfactory convergence. For example, with 𝑘𝑟 = 1, a value representative of the via-enhanced glass interposers, 33 terms are necessary to reach 1% agreement. This issue is highlighted in Fig. 4. The first two data sets are the magnitudes (absolute value) of each of the 𝑛 centroid temperature components of an isoflux spot for 39 𝑘𝑟 = 0.1 and 10 W/m-K, respectively. The terms in sequences for all 𝑘𝑟 oscillate around zero, but after an initial number of terms, Fig. 4 shows that a hundred-fold reduction in lateral conductivity leads to a ten-fold increase in the magnitude of this oscillation. The second two sets plotted are each a 30-term moving average of the respective temperature summations. The reduction in oscillation corroborates the observed fact that a moving average at end of a running total of temperature components can speed convergence to the anticipated centroid temperature. Figure 9: Oscillations in temperature components for low 𝒌𝒓 interposers. Finally, the temperature profile across the top surface of the interposer can be obtained by introducing the radial eigenfunction, 𝐽0(𝛿𝑛 𝑟 𝑏 ) into the centroid temperature summations, resulting in Δ𝑇(𝑟) = 𝑄 𝜋𝑏𝑘𝑒𝑓𝑓 ∑ 2𝐽1(𝛿𝑛𝜖)𝜑𝑛 𝜖 𝛿𝑛2 𝐽0 2(𝛿𝑛) ∞ 𝑛=0 𝐽0(𝛿𝑛 𝑟 𝑏 ) (21) for isoflux spots and 40 Δ𝑇(𝑟) = 𝑄 𝜋𝑏𝑘𝑒𝑓𝑓 ∑ sin(𝛿𝑛𝜖)𝜑𝑛 𝜖 𝛿𝑛2 𝐽0 2(𝛿𝑛) ∞ 𝑛=0 𝐽0(𝛿𝑛 𝑟 𝑏 ) (22) for isothermal spots. That these reduce to the centroid temperature at 𝑟 = 0 follows from the fact that 𝐽0(0) = 1. These allow a definition of a thermal coupling coefficient for each point on the interposer surface. By dividing Equations (21) or (22) by 𝑄, one obtains a “thermal coupling” function that provides the local interposer surface temperature rise per watt of central chip power. This function, 𝑅(𝑟), encapsulates the response driven by the intrinsic parameters of the interposer/cooler system. For isoflux spots the thermal coupling function is 𝑅(𝑟) = 1 𝜋𝑏𝑘𝑒𝑓𝑓 ∑ 2𝐽1(𝛿𝑛𝜖)𝜑𝑛 𝜖 𝛿𝑛2 𝐽0 2(𝛿𝑛) ∞ 𝑛=0 𝐽0 (𝛿𝑛 𝑟 𝑏 ) , (23) and for isothermal, 𝑅(𝑟) = 𝑄 𝜋𝑏𝑘𝑒𝑓𝑓 ∑ sin(𝛿𝑛𝜖)𝜑𝑛 𝜖 𝛿𝑛2 𝐽0 2(𝛿𝑛) ∞ 𝑛=0 𝐽0 (𝛿𝑛 𝑟 𝑏 ) . (24) Plotted in Figure 10 are two example thermal coupling functions for two interposers of different radial effective conductivity. The first (solid) represents a via- enhanced glass interposer, with 𝑘𝑟 = 1.5 W/m-K, and the second (dashed) represents silicon with 𝑘𝑟 = 150 W/m-K. Both have 𝑘𝑧 = 150 W/m-K (meaning the glass via fill factor would need to be very high, ~42% with 400 W/m-K vias). The curve for glass is a 45 term approximation, and for silicon, 30 terms. The centroid resistance 𝑅𝑐 is much higher for the anisotropic glass, at 7.0 K/W, while for silicon it is much lower at 3.6 K/W. This is due to the silicon allowing 41 significant lateral conduction, such that the coupling function (and thus temperature rise) carries to the edge of the interposer. The glass, however, sees a rapid extinction in the influence of the central chip, and drops below that of the silicon by 1.38 mm from the centroid, or at a separation distance of 0.18 mm. Figure 10: Thermal coupling function for two interposers using values described in Figure 8, with 𝒌𝒛 = 𝟏𝟓𝟎 W/m-K and 𝒉 ∗ = 30,000 W/m2-K. Hot spot is isoflux (Equation (23)). The solid curve corresponds to an interposer with 𝒌𝒓 = 1.5 W/m- K, while the dashed 𝒌𝒓 = 150 W/m-K. 4.2.3 Results of Finite Element Analysis Both as a method of checking the thermal constriction solutions and recognizing that for highly anisotropic, and very thin interposers many series terms are required, finite element analysis was also performed on the system shown in Fig. 3. The 2D, axisymmetric FE model uses 141,100 high-order (8-node) quadrilateral elements having a nominal edge dimension of 2 µm. This number was verified as acceptable by 𝑎 = 1.26 mm 42 performing a mesh convergence study using 1.5 and 1 µm element sizes and observing no significant change in calculated temperatures. As mentioned in Section 4.2.14.2.2, for isoflux spots a uniform flux of 500 W/cm2 was introduced at the hotspot on the upper interposer surface, and the surface temperature profile recorded. The calculated 𝑅𝑐 is then the ratio of centroid temperature and total spot flux (25 W) as described in Equation (20). For isothermal spots, a constant temperature of 1 °C was specified along the spot boundary, the resulting surface temperatures recorded, and the normal component of heat flux at locations on the lower interposer surface recorded. (Measuring flux on the underside of the interposer as opposed to at the spot avoids any singular behavior near the spot edge.) Temperatures and heat fluxes were measured along a path containing 600 points (i.e. every 4.7 µm). Heat flux for the isothermal spot cases was integrated (with weight 2𝜋𝑟) to obtain the total hotspot power 𝑄, resulting in 𝑅𝑐 = 1°C/𝑄. Figures Figure 11 through Figure 14 show plots of surface temperature across the radius of the interposer as a function of radial conductivity. Figure 11 and Figure 12 show isoflux-spot cases, using ℎ∗ = 30,000 and 100,000 W/m-K, respectively. As radial conductivity is increased, the fixed input heat spreads further laterally, reducing the centroid temperature while increasing temperatures outside the hotspot. Figure 13 and Figure 14 show the isothermal-spot cases, with the same ℎ∗ as in Figure 11 and Figure 12, respectively. The edge of the hotspot is much more apparent. Additionally, with increasing lateral conductivity, the temperature-fixed hotspot is able to accommodate progressively more input heat due to spreading, leading to rising interposer temperatures outside the hotspot. 43 Plotted in Figure 15 is the interposer centroid thermal resistance, 𝑅𝑐, for all four cases as function of radial conductivity. Note that the functional dependences for the isoflux spots mimic the centroid temperature present in Figure 11 and Figure 12 – a simple result of the definition of 𝑅𝑐. This highlights that 𝑅𝑐 is the intrinsic property of the interposer system; it does not depend on the magnitude of the hotspot power used (since conductivities have been held independent of temperature). The relations plotted in Figure 15 can be used to alternate between cases where the total spot power are fixed, as in Figure 11 and Figure 12, and where the centroid temperature is fixed, as in Figure 13 and Figure 14. The former transformation essentially normalizes by the centroid temperature, while the latter “un-normalizes” them. This importance of the centroid resistance 𝑅(0) = 𝑅𝑐 is further discussed in the next section, Section 4.2.4. A final comment on Figure 15 is the fact that the resistances for the two types of spot converge as 𝑘𝑟 → 0, since in such a situation heat is being constrained entirely under the footprint of the hotspot. This results in a one dimensional flux tube whose resistance must equal 𝑅1𝐷 = 𝑡 𝜋𝑎2𝑘𝑧 + 1 𝜋𝑎2ℎ∗  (25) 44 Figure 11: Interposer surface temperature for isoflux spot with underside cooling 𝒉∗= 30,000 W/m2-K as a function of radial distance and 𝒌𝒓. Figure 12: Interposer surface temperature for an isoflux with underside cooling 𝒉∗= 100,000 W/m2-K as a function of radial distance and 𝒌𝒓. 45 Figure 13: Interposer surface temperature for isothermal spot with cooling 𝒉∗= 30,000 W/m2-K as a function of radial distance and 𝒌𝒓 Figure 14: Interposer surface temperature for isothermal spot with cooling 𝒉∗= 100,000 W/m2-K as a function of radial distance and 𝒌𝒓 46 Figure 15: Interposer thermal resistance with respect to hotspot centroid for the four cases shown in Figs. 5-8. 4.2.4 Analysis – Visualizing the Design Space The overarching goal of this compact constriction model is to reduce the number of parameters needed to distinguish effectively inequivalent HI subsystems (consisting of a single high-power component). In Section 4.2.1, the geometric and material parameters were condensed into a compact constriction model. The discussion in Sections 4.2.2 and 4.2.3 show that the desired object of interest is a thermal coupling function that describes the temperature rise at any location on the interposer in response to unit power dissipation at the central chip. What remains to be incorporated are the operating parameters of the devices the interposer will host. The possible parameters of interest are the central and sensitive device dissipations, 𝑄𝑎 and 𝑄𝑐𝑚𝑜𝑠, their maximum operating temperatures, 𝑇𝑎𝑚𝑝,𝑀 and 𝑇𝑐𝑚𝑜𝑠,𝑀, and the coolant temperature 𝑇𝑓. The first simplification comes from assuming the CMOS 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 200 400 600 800 1000 R es is ta n ce ( K /W ) Radial Conductivity (W/m-K) Interposer Thermal Resistance, w.r.t. Centroid Isoflux, h = 30,000 Isothermal, h = 30,000 Isoflux, h = 100,000 Isothermal, h = 100,000 47 dissipation is zero, justifiable in cases where both the self-heating of the CMOS and its effect on the amplifier are negligible. Next, rather than work with the absolute maximum operating temperatures, the delta with respect to the coolant will be considered: Δ𝑇𝑎𝑚𝑝,𝑀 = 𝑇𝑎𝑚𝑝,𝑀 − 𝑇𝑓 (26) and Δ𝑇𝑐𝑚𝑜𝑠,𝑀 = 𝑇𝑐𝑚𝑜𝑠,𝑀 − 𝑇𝑓 (27) Two constraints that must be satisfied can be constructed from these parameters by introducing the thermal coupling function. The amplifier must remain below its allowable temperature rise, meaning 𝑄𝑎[𝑅(0) + 𝑅𝑎] = Δ𝑇𝑎𝑚𝑝 ≤ Δ𝑇𝑎𝑚𝑝,𝑀 , (28) where 𝑅𝑎 is the resistance of the amplifier and its attach, from Equation (12). The corresponding limit must be observed for the CMOS: Δ𝑇𝑐𝑚𝑜𝑠 = 𝑄𝑎𝑅(𝑟) ≤ Δ𝑇𝑐𝑚𝑜𝑠,𝑀 . (29) Since the central chip power 𝑄𝑎 is driving both responses, it would be convenient to combine these constraints. This can be done by dividing the inequality in (186) by the equality in (185) to obtain 𝑅(𝑟) 𝑅(0) + 𝑅𝑎∗ ≤ Δ𝑇𝑐𝑚𝑜𝑠,𝑀 Δ𝑇𝑎𝑚𝑝 . (30) Equation (30) ensures the CMOS temperature constraint is met. Recognizing that for a particular thermal coupling function, the maximum power that can be dissipated is 𝑄𝑀 = Δ𝑇𝑎𝑚𝑝,𝑀 𝑅(0) + 𝑅𝑎∗ , (31) and follows the ratio 48 𝑄𝑎 𝑄𝑀 = Δ𝑇𝑎𝑚𝑝 Δ𝑇𝑎𝑚𝑝,𝑀 , (32) the amplifier temperature constraint can be made explicit at the cost of reintroducing 𝑄𝑎: 𝑅(𝑟) 𝑅(0) + 𝑅𝑎∗ ≤ Δ𝑇𝑐𝑚𝑜𝑠,𝑀 Δ𝑇𝑎𝑚𝑝,𝑀 𝑄𝑀 𝑄𝑎 = Θ𝑐 𝑄𝑎 𝑄𝑀⁄ , (33) where Θ𝑐 = 𝑇𝑐𝑚𝑜𝑠,𝑀 − 𝑇𝑓 𝑇𝑎𝑚𝑝,𝑀 − 𝑇𝑓 . (34) Although the development of Equation (33) is somewhat roundabout, it quantifies a very basic intuition of how the HI system must trade off various design considerations. Θ𝑐 operates as a constraint metric that captures how “tight” the thermal isolation need is. Low values of Θ𝑐 represent highly constrained systems, where safe operating temperatures of the low-power and high-power components are widely disparate and/or the coolant must be run hot, close to the sensitive device maximum. High values, approaching 0.5 or even 1, represent very forgiving systems. 𝑄𝑎 ∕ 𝑄𝑀 provides a mechanism for de-rating the central chiplet below the maximum disspation permissible with a given interposer and cooler. It is important to keep in mind that unlike Θ𝑐, which is dictated by the externally obtained specifications of the devices and ambient temperature, 𝑄𝑀 depends on 𝑅(0), and thus the particulars of the interposer and cooler. Finally 𝑅(𝑟) 𝑅(0)+𝑅𝑎 ∗ , a conveniently normalized form of the thermal coupling function, provides a method for determining the minimum separation distance between the amplifier and CMOS. Since 𝑅(𝑠) is decreasing, if for a given Θ𝑐 and 𝑄𝑎 𝑄𝑀⁄ Equation (33) can be satisfied somewhere on the interposer, there will be a minimum value of 𝑠 = 49 𝑆, that yields the equality. A diagram of this process is shown in Figure 16. A cutoff is determined by the ratio of Θ𝑐 to 𝑄𝑎 𝑄𝑀⁄ – in the figure it is about 0.12. This would be a very thermally tight system: if 𝑄𝑎 𝑄𝑀⁄ is set to 1 (no de-rating), an example system with this metric could be a wide bandgap amplifier with 𝑇𝑀 = 200 °C, at commercial of the shelf (COTS) chip with 𝑇𝑀 = 85 °C, both being cooled by a fluid at 𝑇𝑓 = 70 °C. 4 Figure 16: Finding minimum device separation for a given 𝚯𝑪, 𝑸𝒂 ∕ 𝑸𝑴, and thermal coupling function 𝑹(𝒓). Summarizing the rules embodied by Equations (31), (33), and (34) in plain language, if the sensitive device is overheating, design options available are: 1. Substitute a more robust device and/or lower the coolant temperature, increasing Θ𝑐 and “loosening” the system. 2. Move it further from the central chip by increasing 𝑠, which decreases 𝑅(𝑟) 3. De-rate the central chip, decreasing 𝑄𝑎 4. Engineer an interposer/cooler system with a more favorable 𝑅(𝑟) 4 For some thermal coupling functions, the edge of the circularized interposer would be reached some extreme cutoffs are met. 50 Clearly strategy four is the primary focus of this thesis. As demonstrated in Sections 4.2.2 and 4.2.3, some possible improvements will reduce 𝑅(𝑟) across the entire interposer, such as increasing the underside cooler conductance, or the interposer vertical conductivity. Others, such as modifying 𝑘𝑟 or interposer thickness may alter the distribution of 𝑅(𝑟), for example increasing its value near 𝑅(0) while decreasing it where sensitive devices are to be placed. Concluding this chapter is a process map – Figure 17 – that diagrams the development of the compact model from the wide array of HI system parameters to be analyzed. Parameters describing the (possibly via-enhanced) interposer are first used to create a simplified, homogenized thermal constriction model. While the approaches in the effective conductivity literature can be used to determine 𝑘𝑟 and 𝑘𝑧, it will be shown in Chapters 0 and 0 that a naïve application of the rule-of-mixtures (Equation (1)) without regard to the boundaries of the interposer via array will neglect to account for microspreading resistances. Once known, proper accounting of these resistances can be done by developing an effective cooler conductance ℎ∗ (Equation (9)) and a central chip effective junction-to-interposer resistance 𝑅∗ (Equation (12)). Solving the thermal constriction problem yields the thermal coupling function for the system. Meanwhile, the “external” parameters of the device thermal requirements, along with the ambient (coolant) temperature, create the thermal constraints placed on the system. Knowledge of 𝑅(0) is necessary to define a maximum central chip dissipation, 𝑄𝑀. The interplay between the constraints and the normalized thermal coupling function determine the minimum device separation. 51 Figure 17: Process map of creating compact thermal model from a heterogeneously integrated system 52 5.0 MICROGAP COOLING OF THERMAL VIA ARRAYS This introductory section of this chapter describes a set of experiments that aim to validate the modeling of the thermal isolation case study and demonstrate the principles described by the compact constriction system model. This section also introduces the design of the via array samples and the industry partners contracted to fabricate them. The second section, 5.1, describes the design, fabrication, and characterization of a single-phase water microgap cooler. This microgap is used to supply coolant to the underside of the via-array interposer samples as well to reference interposers of bulk silicon. The mounted interposers are equipped with resistive thermal test chips and the surface temperature rise is measured using IR thermography. The details and results of these measurements are presented in section 5.2. Measurements are performed in the downstream regions of the interposer surfaces, as these represent the worst-case temperature distribution, with higher expected temperatures compared to upstream or cross-stream interposer regions. A conjugate finite-volume model of the chip-heated, microgap-cooled interposers was created and is described in section 5.3. It suggests that there are differences in the fluid thermal boundary layers created in via-enhanced glass versus silicon interposer microgap experiments. These differences suggest that the relative upstream performance of glass interposers with respect to the silicon may differ from the relative performance obtained in the downstream direction. In section 5.4, an upstream-focused experiment is performed and a crossover distance is determined where the via-enhanced glass interposer temperature falls below that of the silicon reference. This demonstrates that 53 under appropriate circumstances these interposers can be used for thermal isolation applications. Via-Enhanced Glass Sample Design A design of experiments of via array samples is contained in Table 3 and diagrammed in Figure 18. Two 15 cm diameter glass wafers, 400 µm thick, are each patterned into 16 test coupons. In each coupon, four 5 mm by 5 mm via arrays are created with the array characteristics contained in the table. In addition to the table- defined parameters, half of the array samples (designated “A”) are terminated with uniform 12 µm copper pads connecting all vias within the 25 mm2 footprint. The other arrays have vias individually terminated at the surface of the wafer. Based on the design of experiments, there are 16 test coupons for various experimental objectives, with two coupons of each type for redundancy. The through-holes for the vias were created with an excimer laser drilling technique by Corning Glass as a subcontractor under the via fill performer, Samtec. Samtec’s fabrication technique entirely fills vias using a copper frit paste, with an advertised fill conductivity of at least 300 W/m-K. This approach was recommended by the fabrication contractors based on coefficient of thermal expansion (CTE) compatibility between the via fill and the glass substrate. Fill techniques using higher conductivity plated copper (as solicited from alternate manufacturers) were suitable only for producing conformal vias, with a metal film lining the interior surface of the via hole. This would fail to produce the fluid-tight system required for microgap cooling. 54 Based on design rules required by Corning Glass, via diameter-to-pitch ratio could not exceed 0.5 [47]. This current limitation restricts the quantity of conductive fill that can be placed as vias within the glass. Corning acknowledged that this spacing restriction is not absolute, and that further advances in manufacturing can lead to closer via spacing, especially within localized, small footprint areas. Given the resulting maximum available via fill factor of 22.6%, the maximum vertical effective conductivity of the samples as predicted by rule-of-mixtures, Equation (1), is 68.5 W/m-K when using 𝑘𝑣= 300 W/m-K. For in-planed effective conductivity, use of Rayleigh’s formula for arrays of cylindrical inclusions (as presented in [48]), 𝑘𝑒𝑓𝑓,𝑥 = 1 + 2𝜙 𝐶1 − 𝜙 + 𝐶2(0.30584𝜙4 + 0.013363𝜙8) (35) where 𝐶1 = 𝑘𝑣 + 𝑘𝑠 𝑘𝑣 − 𝑘𝑠 and 𝐶2 = 𝑘𝑣 − 𝑘𝑠 𝑘𝑣 + 𝑘𝑠 , predicts a value of 1.578 W/m-K for a via of 300 W/m-K with a fill of 22.6%. This value is not particularly sensitive to further increases in 𝑘𝑣: when increased to 400 W/m-K the effective conductivity rises to 1.580 W/m-K. Table 3: Via Array Design of Experiments 55 Figure 18: Glass wafer division into 16 test coupons. “A” coupons have uniform surface pads over arrays while “B” coupons have individually terminated vias. Right: Close-up view of a coupon, detailing the four identical via arrays Microgap Cooler and Flow Loop Design To investigate the feasibility of integrating embedded cooling approaches with a via-enhanced interposer, a single phase microgap cooler was designed and fabricated. Because the cooler is intended to be reusable, it was determined that the most economical fabrication approach is to mill the cooler out of a small block of copper. The challenge is the small size of the cooler module: since the target gap footprint is 5 mm x 10 mm, the cooler module itself was designed at 10 mm x 20 mm. In actually, due to the need for space for the inlet and outlet plenums, the gap footprint was reduced to 5 mm x 8 mm. The cooler design drawing overlaid with a diagram of the fluid flow path is given in Figure 19. 56 Figure 19: Design drawing for copper microgap cooler manifold Copper was chosen for the cooler after consideration of its corrosion resistance and machinability. The primary feature of the cooler is the microgap surface, where surface finish and depth tolerance are much more important than in other features of the cooler. While metal edge-build up on the cutting tool could be an issue with the softer materials, the deep, narrow cut for the plenums would be more challenging in a hard material like stainless steel. The nominal gap height of 200 µm was chosen based on the experience of Kim [] with water-based microgaps: smaller gaps lead to increased heat transfer, but below 200 µm entrained gas bubbles can become trapped within the microgap. In practice, the standoff created by the o-ring seal results in a gap height larger than 200 µm. Measured by shim gauges and by photographic inspection, this additional standoff is measured at 50 µm. This standoff is visible in Figure 20. Given that changing samples requires 57 disassembly and recompression of the o-ring seal, the final gap height is estimated at 250±25 µm. Inlet/outlet temperatures are monitored with type T inline thermocouples (standard limits of error ±1°C), and pressures are monitored by a Setra 0-50 psi differential pressure transducer (0.25% full-scale (FS) accuracy, or ±0.86 kPa). Flowrate is determined from a Brooks Instruments variable area glass tube flowmeter with a stated accuracy of 3% FS, which for the size of the tube used corresponds to ±0.11 cm3/s. The flowmeter also has a stated 0.25% FS repeatability. Figure 20: Side view of mounted sample. a) Clamping Bracket, b) Interposer Sample, c) Copper Manifold, d) Thermal Via Array, e) O-ring Standoff. a) b) c) d) e) 58 Samples – whether silicon or glass-via interposers – are installed on the cooler using two clamping brackets that hold the sample against the o-ring seat. The brackets are machined out of thin aluminum plate and fixed using small ID screws. As the o-ring seal in the cooler must encompass the gap as well as both plenums, the outer dimensions of the sample must match that of the microgap manifold, 10 mm x 20 mm. This sample footprint size could be cleanly diced from the parent glass wafer such that it contains two via arrays, as shown in Figure 21. However, due to limitations in providing electrical contacts to more than one thermal chiplet, samples were taken from the edge of a coupon such that it contains only one via array, allowing the array to be positioned at any location along the gap. Figure 21: Sample dicing layout compatible with microgap cooler testing Once the samples are mounted on the cooler manifold, the single phase water flow loop circulates the coolant through the microgap manifold as shown in Figure 22. Comprised of a single loop, it consists of a 6-liter chiller/heater with integrated centrifugal pump, the glass tube flowmeter with needle valve, two Type-T thermocouples 59 placed at the manifold inlet and outlet, a differential pressure gauge, the microgap manifold itself, and a return line to the chiller reservoir. For the final tests performed in at the end of this research program, a separate voltage-controlled gear pump was used to provide a higher flow rate through the loop. The chiller temperature setpoint is set to 25°C. This temperature is chosen to closely match the ambient laboratory temperature. Because lower fluid flowrates allow the fluid in the inlet line to more closely approach ambient from the chiller setpoint, the inlet thermocouple reading is used to define the microgap inlet fluid temperature, rather than the chiller setpoint. Because of the infeasibility of completely removing possible contaminants from the wetted surfaces of the chiller reservoir and submerged exchanger coil, the working fluid used is laboratory tap water (as opposed to distilled or de-ionized water). Fortunately, trace mineral impurities are not expected to have a significant impact on the thermal conductivity and specific heat of the water coolant, in contrast to two-phase cooling where impurities are of a significant concern due the effect on saturation temperature and contribution to fouling processes. With the microgap dimensions previously described and the flowrate available from the chiller pump, Reynold’s numbers up to 1600 are achieved. Water flow rate was adjusted to values between 0.067 and 3.67 cm3/s. With the voltage-controlled gear pump, flowrates of up to 20 cm3/s are obtainable (Re approaching 8,000). The pressure drop measured across the microgap manifold as a function of measured flow rate is presented in Figure 23. 60 Figure 22: Diagram of single-phase flow loop. Figure 23: Microgap differential pressure as a function of measured flowrate. With the initial flow tests complete, a set of preliminary cooling experiments were conducted. Shown in Figure 24 are IR images of 1 mm diameter 0.8 W laser spots focused on both uniform glass and silicon interposer samples (no vias present). All IR 0 2 4 6 8 10 12 14 16 18 20 0 0.5 1 1.5 2 2.5 3 3.5 P re ss u re D ro p [ k P a] Flowrate [cm3/s] Microgap P-V Curve 61 images are taken with a FLIR Silver MWIR camera, having a resolution of 512 x 640 pixels, and the operation of which is further detailed in section 5.2.2. While the images in Figure 24 are interesting in that they show that – as expected – temperature rise in the bulk glass interposer is higher than in silicon (and for low flow the influence of fluid carrying heat downstream can be observed), a drawback of the laser heating is immediately apparent. First, the focusing optics of the diode laser and available IR magnification lenses prevent the IR camera from being placed sufficiently near the spot to capture the temperature profile with a large number of pixels. This is particularly problematic when attempting to define the peak spot temperature, because when the pixel(s) encompassing this peak also measure lower, off-peak temperatures, the resulting average measurement is lower than the maximum value. The second problem is that the heated region is much harder to define as a result of the Gaussian beam profile. In actual application, these interposers will be subjected to discrete heat maps corresponding to the heterogeneous devices. In order to deal with this issue, thermal test chiplets were fabricated with patterned platinum serpentine heaters. One of these chiplets is shown in Figure 25. These heaters have the advantage of serving as both a heat source and temperature sensor: by monitoring the serpentine’s resistance, the average chiplet surface temperature can be deduced. These chiplets enable a high magnification lens with a short focal length to be used with the IR camera, since there are no associated laser optics. The camera can focus on a region of the interposer surface directly adjacent to the chip edge, and allow the Pt serpentine to monitor the chip surface temperature. 62 Figure 24: Laser heating of samples with single phase water flow. a) Glass sample, 200 ccm flowrate. b) Glass sample, 2 ccm flowrate. c) Si sample, 200 ccm flowrate. d) Si sample, 2 ccm flowrate. Figure 25: Thermal test chiplet mounted on a via array sample. The chiplet dimensions are 2 mm x 4.5 mm, and the serpentine dimensions are 1.6 mm x 1.85 mm. The pads at the lower edge of the image are for voltage sensing across the inner third of the Pt serpentine. Microgap Cooling Results With the shift from laser heating to thermal test chips, a detailed examination of interposer surface temperature was now possible. Describing the majority of the a) b) c) d) 63 microgap cooling tests, this section is divided into three parts. The first discusses the downstream temperature response of the test chip itself to changing interposers and water flow rates, as obtained by electrical measurements. The second introduces examples of the raw spatial data obtained using IR thermography and discusses how that data is evaluated and fit to an exponentially decaying curve. Finally, the third section compares the curve fitting parameters between experiments involving different interposers and flowrates. The same experimental procedure was maintained throughout measurement of the various samples. First, the chiller and pump are turned on and set to a full-open flow rate and allowed to run for 30 minutes to ensure the chiller reaches 25 °C setpoint. Meanwhile, a thermal test chip is placed on the sample surface, held in place by a layer of Artic Silver thermal grease (the effects of which are addressed in the next section). An electrical probe jig is lowered to make contact with the pads on the test chip, with continuity determined by passing a 1mA current through the chip and monitoring the measured sample electrical resistance. The IR camera is fitted with a barrel magnification attachment and installed in an aluminum frame fixture that supports the microgap test section and probe jig. This fixture is supported by a small tabletop optical breadboard with vibration dampening feet. Thus, the microgap with sample, probe jig, and IR camera are rigidly held in relation to one another, reducing the impact of vibration from the chiller, pump, and external sources on the repeatability of captured IR images. The frame also allows for coarse focus adjustment of the camera, and provides a degree of protection to the sample and thermal test chip5. 5 Due to the relatively hard tungsten probes of the probe jig, over the course of testing several test chiplets were rendered unusable due to damage at the contact pad sustained during testing and interchange of interposer samples. 64 With the camera focused on the region of interest, the desired water flowrate is set using the needle valve on the glass tube flowmeter. An “unpowered” reading and IR image are recorded using a low probe voltage of 1V (corresponding to <1mW of power), followed by powering the chip to 36V to reach a nominal chip power of 1 W. Conservative estimates of the system time constant can be arrived at by considering the heat capacity of the silicon chiplet, the capacity of glass in a 7.25mm x 7.25mm area (array footprint with a 2.25 mm additional buffer) and the resistance of a convection coefficient of strength 3,000 W/m2-K. This results in a lumped thermal capacitance of ~0.1 J/K, a convection resistance of 6.3 K/W, which taken with a resistance of 3.4 K/W for the thermal grease (see next section) results in an RC time constant on the order of 1s. Thus, by recording electrical readings and IR images 3-4 seconds after powering the chip, steady state operation can be ensured. Chip electrical and interposer IR measurements are taken at seven water flowrates on a reference silicon interposer as well as four via array samples (out of the eight types available from the wafer). The samples chosen for study form a set with sample A1 as a baseline (50 µm vias, 100 µm pitch aligned array, no pads). The other three samples B1, A2, A3 vary presence of pads, via pitch, and array alignment, respectively. 5.2.1 Chip Temperature Rise As discussed in Section 0, half of the glass samples used in this study were fabricated with two uniform 12 µm thick Cu frit pads extending across the footprint of the array (one each on the upper and lower interposer surface, respectively), connecting the ends of the thermal vias to each other. This pad is intended to function as a thermal 65 spreader, distributing the heat carried by each via over the glass portions of the array surface. Glass interposers without these pads are referred to as A-type and those with pads as B-type. Numbers within the sample name refer to array type described in Table 3. An image of GL A1 sample with mounted chip heater is shown in Figure 26. When testing with glass-via samples, the interposer is scribed such that the via array is located at one end of the microgap and spans the 5mm width of the gap surface. The test chip is placed in the center of the via array when there are no pads, and when a pad is present (B samples) the chip is placed on the edge of the pad to facilitate investigation of directed heat spreading and isolation. If the chip was instead placed in the center, the copper pad would subvert the intended isolation effect. During testing, a thermal test chip is adhered to the upper surface of the interposer using a silver impregnated thermal grease, Arctic Silver 5. The manufacturer provided conductivity is 8.7 W/m-K, but according to tests performed by Narumanchi, et. al. [49] the measured conductivity is 0.94±9 W/m-K. The thickness of the grease layer during and after compression against the sample using the electrical contact probes is estimated at less than 25 µm; a portion of this layer can be seen in Figure 26 at the lower edge of the via array, where the test chip has been moved upward into position. According to {{157 Narumanchi,S. 2008}}, this layer of grease would present a thermal resistance of about 31±3 mm2-K/W – the majority of the resistance between the Pt heater and the interposer. Fortunately, uncertainty in the magnitude of this resistance should have a negligible impact on the temperature rise of the interposer surface, since its influence is limited only to the additional temperature rise of the chip heater above that of the 66 interposer. This temperature rise ranges from 4 K per watt of heater power on the silicon interposer to 10 K/W for the via sample interposers. Figure 26: Thermal test chip mounted on interposer sample A1, describing typical IR field of view. With the sample and test chip installed in the Cu manifold, water from the chiller unit is circulated through the microgap (of which the interposer underside forms the heated surface being cooled). Electrical contact is made to the heater contact pads with tungsten probes and the resistance recorded. A DC power supply is then used to drive the heater, and the resulting current is used to monitor the changes in the resistance of the heater as well as calculate dissipated power. The uncertainty associated with the constant voltage power supply is 0.03%, while the accuracy of the current sensing digital multimeter is 0.0035% in DC mode. Fluctuation observed in the multimeter reading at Inlet Plenum Test Chiplet Thermal Grease Via Array IR Field of View 67 the fourth significant digit suggests an experimental uncertainty of 0.1%. An RSS analysis for the uncertainty in measured resistance, given by 𝛿𝑅 = √(𝛿𝑉)2 + (𝛿𝐼𝑚𝑒𝑡𝑒𝑟)2 + (𝛿𝐼𝑓𝑙𝑢𝑐) 2 (36) results in a calculated uncertainty of 0.11%. Measurements of dissipated heater power are also of the same uncertainty. The change of the Pt heater resistance with temperature, 𝑑𝑅/𝑑𝑇 is used to monitor the average heater temperature. This value of 𝑑𝑅/𝑑𝑇, 1.93 Ω/K, was obtained through separate measurements in a temperature controlled oven (monitored by Type T thermocouple), the results of which are shown in Figure 27. This would correspond to a temperature coefficient of resistance (TCR) of 0.00199 °C-1, only 51% of the bulk TCR of Pt (0.00392 °C-1). Although it is known that thin metal films can exhibit higher resistance and lower TCR than bulk metals [50], this discrepancy is larger than the ~15% that is attributable to surface and film morphology effects. The additional discrepancy is attributed to the lead and contact resistance resulting from the two-wire measurement technique used in the experiment. However, since the measured lead-contact-heater resistance does exhibit a high degree of linearity (R2 = 0.9998) over the temperature interval of interest, monitoring this resistance still provides a reliable temperature sensor. Given the uncertainty of measuring this resistance, the uncertainty of heater resistance- based temperature data is taken at 1.93(0.11%), or 0.21% for the heater as measured in the temperature controlled oven. Changes in contact resistance as samples are interchanged underneath the probe jib contributes to an observed uncertainty range of 2% in the unpowered heater resistance. Whether these changes in contact resistance also 68 affect 𝑑𝑅/𝑑𝑇 is unclear, but taking the conservative view that they contribute a 2% uncertainty in 𝑑𝑅/𝑑𝑇 suggests an overall uncertainty of 2.01% A comparison of the electrically-measured heater temperatures with IR-measured interposer temperature at the chiplet edge is made in Figure 28. The fact that the electrically measured heater temperature tracks well with the IR measurements (when including a fixed temperature drop through the thickness of the chiplet and grease layer, which varied between 4-10 K/W) gives confidence in the IR measurement procedure. Figure 27: Platinum serpentine resistance calibration with constant temperature coefficient of resistance. y = 1.9301x + 925.82 965 970 975 980 985 990 995 1000 1005 0 10 20 30 40 50 H ea te r R es is ta n ce [ O h m ] Heater Temperature [°C] Heater Resistance Calibration 69 Figure 28: Temperature rise for three interposer samples. Hollow markers designate temperature rise at the chiplet edge as determined by IR thermography. Solid markers designate the average chiplet surface temperature as determined by Pt serpentine resistance. The nominal chiplet dissipated power used was ~1W. Higher powered experiments were avoided in order to mitigate losses due to natural convection, which have been neglected in this study. This is justifiable as the Rayleigh number for the chiplet heater at a temperature 35 °C above ambient is on the order of 1, thus the dissipated electrical power of the Pt heater is assumed to be delivered in its entirety to the interposer. The average temperature rise of the Pt heater was determined for each of the silicon and glass interposers, as was the interposer surface temperature at the downstream edge of the chip using IR measurements. For each interposer, seven flow rates were set and the temperature rise due to the powered heater recorded. Because of the shift in resistance (and thus heater power with constant voltage) as heater temperature changes, these temperature measurements were normalized to 1W of heater power. Since the IR- based chip edge measurements (described in the next sections, 5.2.2 and 5.2.3) are less 0 5 10 15 20 25 30 35 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1 W S ca le d T em p er at u re R is e [K /W ] Water Flow Rate [cm3/s] Chip Heater and Edge Temperature Rise Silicon Silicon Chip Glass A1 Glass A1 Chip Glass B1 Glass B1 Chip 70 sensitive to the effects of the thermal grease, they are considered the primary data of interest. Plotted in Figure 29 is the test chip edge temperature rise for each interposer and flow rate. Unsurprisingly, the higher conductivity silicon interposer exhibited the lowest temperature rise at each flowrate. This was followed by the GL B1 interposer, with the GL A1 interposer exhibiting the highest temperature rise. As flowrate increases the temperature rise decreases as the stronger convection boundary on the interposer underside lowers the total chip-to-fluid thermal resistance. Figure 29: 1W scaled temperature rise data for each interposer, as determined by IR thermography at chiplet edge. Infrared Thermography. Although the chip active surface temperature rise (at the heater) above that of the fluid is an important component in characterizing the performance of the interposers, the primary goal is to investigate the temperature profile of the interposer upper surface in regions proximal to the chip. It is this location that 0 5 10 15 20 25 30 35 0 0.5 1 1.5 2 2.5 3 3.5 4 1 W S ca le d T em p er at u re R is e [K /W ] Water Flow Rate [cm3/s] Chip Edge Temperature Rise Silicon GL A1 GL B1 GL A2 GL A3 71 would be hosting additional chiplets and/or devices alongside the high-dissipation component(s). To capture this temperature profile, the FLIR Silver MWIR camera was outfitted with a 6.6 mm focal length barrel magnification lens attachment and used to observe the interposer in the vicinity of the test chip. To capture the worst-case temperature rise, a region downstream of the chip was selected. The detector array of the camera is 640 x 512 pixels, although the barrel attachment aperture is such that the corners of the array are unreliable. When focused on the sample, the field of view is approximately 3.6 mm in diameter. Calibrating against an image of the via array (with the known 100 µm via pitch) resulted in a ratio of 5.61±0.17 µm/pixel. Emissivity calibration of both the semiconductor grade glass and graphite-coated silicon are performed, resulting in a measured ε of 0.92±0.01 for glass and 0.74±0.03 for silicon. For silicon the graphite is deposited using an alcohol suspension spray; 3-4 coats are applied until the silicon no longer transmits IR radiation from a distant heat source, ensuring the coating is opaque. The emissivity calibration is performed by heating each sample in a temperature controlled oven, recording an IR image of the surface, and informing the camera driver software of the known temperature of the sample. The measured radiosity of the sample is used with the known temperature of the sample and the ambient room temperature to compute the surface emissivity. This calibration was performed at 40, 50, and 60 °C. Each image of the interposer surface with test chip powered was accompanied by an image with the chip powered at a lower 1V “off” level. This image was subtracted from the higher temperature image, providing an accurate pixel-by-pixel temperature rise. An example of these final images is shown in Figure 30. Because of the much lower 72 emissivity of the vias, Pt heater, and test chip surface, data from those pixels is considered unreliable. The Pt heater and test chip surface – being 400 µm above the interposer surface – are also out of focus when imaging the interposer. For the initial experiments, subtracted images are collected at each flow rate, along with inlet and outlet fluid temperature and electrical voltage and current readings. The temperature increase from fluid inlet to outlet was around 0.1 °C or less, as expected from an energy balance for 1W of chip power, and at the limit of the resolution of the thermocouple reader. For analysis, a set of five pathlines were drawn perpendicular to the test chip edge, starting from the interior of the chip and extending approximately 2.2 mm across the interposer. These parallel pathlines are about 75 µm apart, and clustered near the midpoint of the Pt heater. Data from these pathlines form the basis of the quantitative spatial results presented and analyzed in this study. 5.2.2 Raw Profile Analysis Surface temperature data is exported along five IR image pathlines extending along the interposer surface from the chiplet edge. An example of these pathlines applied over a subtracted IR image of an interposed with powered chiplet is shown in Figure 30. These data are analyzed according to three steps. First, the pixel coordinate location information is remapped to describe the perpendicular distance from the test chip edge. By starting the pathlines within the test chip image, the data from each pathline can be aligned using the cold-hot-cold appearance created by the low emissivity Pt serpentine. Although the chip edge is somewhat indistinct due to it being out of focus, making it unadvisable to assign individual pixels to the border of the test chip, the effective location of the edge can be inferred by measuring from an optical microscopy image with a larger 73 depth of focus. The uncertainty in the location of the chip edge is estimated at ±2 pixels, or ±11 µm. The chip edge is thus defined as the zero coordinate, with negative values lying inside the chip and positive values denoting distance along the interposer surface perpendicular to the chip edge. Figure 31 shows the data from one profile set after such a remapping. The two cold troughs around -57 and -82 pixels correspond to the first two switchbacks of the Pt heater. Of note is that the beginning of the temperature decay occurs some distance beyond the effective chip edge location. This could be ascribed to two reasons. The first is smearing of the chip edge due to lack of focus, although this could only account for a few pixels worth of discrepancy. The second is beading of the silver thermal grease at the joint of the chip and interposer. This bead has a different emissivity than the glass or coated silicon, and also has the tendency to scatter radiation originating from the side of the chip. At times this bead can extend as much as 300 µm from the edge of the chip. In subsequent experimental runs efforts were made to reduce the excess thermal grease, leading to smaller beads. Also visible in Figure 31 are discrete troughs associated with the Cu-frit thermal vias, superposed from the multiple data pathlines. 74 Figure 30: Subtracted IR image of powered chiplet on GL A1 interposer. Pixel brightness corresponds to temperature rise between powered and unpowered condition. Red lines indicate where spatial temperature profiles are extracted. Figure 31: Aggregated raw profile data from sample GL A1 under 0.83 cm3/s of water flow. Data from within the chiplet and points corresponding to copper via locations are excluded. 75 In curve fitting these temperature profiles, data from pixels within the chip, thermal grease bead, and thermal vias are excluded (marked as outliers). The five aligned profiles from each image were then aggregated and curve fit as a group. In choosing the appropriate function to fit to the experimental data, consideration of the modes of heat transfer within the system was undertaken. If transfer to the ambient from the interposer surface (through natural convection) is neglected, the interposer resembles a fluid cooled rectangular fin split down a midplane of symmetry. In long fins with Biot number ℎ𝑡/𝑘<0.1, the temperature distribution approaches the form 𝑇(𝑥) = 𝑇𝑏𝑎𝑠𝑒𝑒 −𝑀𝑥 + 𝑇𝑓 (37) where 𝑀2 = ℎ𝑃 𝑘𝐴𝑐 , where 𝑃 is the fin cross-sectional wetted perimeter and 𝐴𝑐 the cross-sectional area. For the interposer-as-fin analogy, where the interposer is much wider than its thickness, 𝑃/𝐴𝑐 is roughly 1. However, disrupting the analogy is both the fact that for the glass interposers the Biot number is on the order of 2-20 (depending on assumed fluid ℎ) and that heat is not entering the “base” of the fin uniformly over its cross section. Heat is instead introduced at the adiabatic midplane of the fin where the chiplet is hosted. Further complicating the analogy is that the fluid heat transfer coefficient is not necessarily constant as the thermal boundary layer develops in the downstream direction. Notwithstanding these issues, the fin analogy reasoning, a single term exponential was examined for goodness of fit. Typical R2 values obtained were ~0.95, and residual 76 plots contained well behaved bows. A two-term exponential decay fit was chosen next, producing R2 values in excess of 0.99.6 The equation for the curve fit is thus 𝐴1𝑒 −𝑥 𝜆1⁄ + 𝐴2𝑒 −𝑥 𝜆2⁄ (38) where 𝜆1 and 𝜆2 are the characteristic length constants, expressible in units of pixels or µm, and 𝐴1 and 𝐴2 are the magnitudes of each term, the sum of which represent the interposer temperature rise (w.r.t. the unpowered temperature) at the base of the heater chip edge. The four fitting parameters vary depending on the interposer and water flowrate used, as well as the heater power. That two exponential terms are necessary makes sense in the context of two length scales established by the presence of the central chip: near the chip the fin analogy does not hold and heat conducts both through the interposer thickness and laterally downstream. Far from the chip the analogy may be a more accurate depiction, although 𝜆2 may not directly correspond to 1/√𝑀 due to boundary layer and high-Biot number effects. If one was only interested in the interposer surface temperature rise at distances farther than 3𝜆1 (where the contribution of the first term has dropped to less than 5% of its value at the chip edge), a single term fit would be sufficient to fit IR temperature data subject to this distance restriction. However, while temperature sensitive devices are likely to be located at these distances from the central chip, such a fit would be unable to describe the temperature rise of the central chip itself. 5.2.3 Spatial Temperature Profiles Table 4 through 6 R2 values for silicon interposers were lower than corresponding fits in glass samples. This was due to both the small-scall irregularity of the graphite spray coating (compared to the polished glass) contributing to increased noise and to the lower temperature rise signal resulting from the higher silicon conductivity. 77 Table 8 list the fitting parameters for the five interposers tested, under varying water flow rates. Uncertainty in the flow and heater power are ±0.11 cm3/s and 0.21%, respectively. Not including fitting uncertainty, uncertainty in 𝐴1 and 𝐴2 originates from both uncertainty in any temperature rise bias introduced (across the entire image) by the IR camera emissivity calibration, as well as uncertainty in the location of the chiplet edge. The contribution due to the camera calibration is difficult to estimate, but for the chiplet edge uncertainty the derivative of Equation (38) leads to uncertainty estimates of 𝛿(𝐴1 + 𝐴2) = −( 𝐴1 𝜆1 + 𝐴2 𝜆2 ) 𝛿𝑥 (39) where it can be seen from typical values in Table 4 through Table 8 that the major contribution to chip edge temperature uncertainty stems from the 𝐴1 short scale decay term. The relative uncertainty in chip edge temperature due to this effect ranges from 3-8%. Combined using RSS analysis with an assumed 5% uncertainty due to camera calibration and the 0.21% uncertainty in heater power, the scaled IR chip edge temperature is estimated to be at most 9.4%. Not including fitting uncertainty, uncertainty in values for 𝜆1 and 𝜆2 are estimated at 3%, stemming from the procedure of converting image pixel distance into µm. Although the large quantity of pixels captured for each test mitigates the error introduced by individual pixel uncertainty, it should be mentioned that the individual uncertainty of each camera pixel is ±0.1K, not including calibration bias uncertainty. Because as the chip temperature increases as flow is restricted – leading to increased heater resistance and lower dissipated power – the 𝐴1 and 𝐴2 parameters have been normalized to 1W of heater power after this point in the analysis. Instead of interposer temperature rise, these normalized functions can be thought of as representing 78 experimentally obtained local thermal coupling constants, relating local temperature rise to central chip power. Table 4: Fitting Parameters for Silicon Interposer 𝐴1𝑒 −𝑥 𝜆1⁄ + 𝐴2𝑒 −𝑥 𝜆2⁄ Flow [cm3/s] A1 [K] 𝜆1 [μm] A2 [K] 𝜆2 [μm] Power [W] R 2 3.17 2.85 90.3 1.56 2787 1.32 0.9606 2.83 2.66 86.6 1.47 2413 1.31 0.9721 2.00 2.18 101.1 1.69 3016 1.30 0.9385 1.13 2.28 103.2 2.17 3946 1.30 0.9606 0.74 2.39 109.2 2.46 4649 1.30 0.9494 0.27 2.43 107.8 3.28 5083 1.30 0.9542 0.08 2.45 109.3 4.74 6594 1.29 0.9467 Table 5: Fitting Parameters for Interposer GL A1: Padless, 100 µm Pitch, Aligned 𝐴1𝑒 −𝑥 𝜆1⁄ + 𝐴2𝑒 −𝑥 𝜆2⁄ Flow [cm3/s] A1 [K] 𝜆1 [μm] A2 [K] 𝜆2 [μm] Power [W] R 2 3.68 11.24 169.6 3.09 942 0.883 0.9965 2.83 12.09 180.2 3.14 1115 0.882 0.9966 2.00 12.41 169.8 4.32 1066 0.882 0.9959 1.38 11.67 183.3 4.65 1345 0.881 0.9963 0.91 10.88 189.4 5.63 1747 0.880 0.9952 0.38 9.998 210.6 7.31 2346 0.878 0.9927 0.08 9.137 247.1 11.78 2584 0.872 0.9922 Table 6: Fitting Parameters for Interposer GL B1: Pad, 100 µm Pitch, Aligned 𝐴1𝑒 −𝑥 𝜆1⁄ + 𝐴2𝑒 −𝑥 𝜆2⁄ Flow [cm3/s] A1 [K] 𝜆1 [μm] A2 [K] 𝜆2 [μm] Power [W] R 2 3.33 11.75 117.2 5.05 1078 1.23 0.9983 2.83 11.72 114.1 5.11 1018 1.23 0.9979 2.00 11.54 119.3 5.39 1166 1.22 0.9977 1.21 11.61 123.7 5.91 1390 1.22 0.9966 0.74 11.25 128.6 6.53 1623 1.22 0.9968 0.27 10.95 135.3 7.91 1895 1.22 0.9992 0.08 10.00 154.0 11.22 2616 1.21 0.9952 Table 7: Fitting Parameters for Interposer GL A2: Padless, 200 µm Pitch, Aligned 𝐴1𝑒 −𝑥 𝜆1⁄ + 𝐴2𝑒 −𝑥 𝜆2⁄ Flow [cm3/s] A1 [K] 𝜆1 [μm] A2 [K] 𝜆2 [μm] Power [W] R 2 3.17 23.5 187.6 7.68 841 23.5 0.9969 2.65 23.5 187.6 7.68 841 23.5 0.9969 1.93 23.1 187.2 8.18 898 23.1 0.997 1.13 23.1 195.0 8.58 1137 23.1 0.9973 0.69 22.5 201.8 8.95 1452 22.5 0.997 0.27 21.7 206.6 10.8 1617 21.7 0.9968 0.08 19.9 223.0 14.1 1912 19.9 0.9966 79 Table 8: Fitting Parameters for Interposer GL A3: Padless, 100 µm Pitch, Close-Packed 𝐴1𝑒 −𝑥 𝜆1⁄ + 𝐴2𝑒 −𝑥 𝜆2⁄ Flow [cm3/s] A1 [K] 𝜆1 [μm] A2 [K] 𝜆2 [μm] Power [W] R 2 3.00 14.9 241.7 2.75 2043 14.9 0.9957 2.83 14.7 244.1 2.80 2046 14.7 0.9958 1.93 14.6 243.8 3.64 2153 14.6 0.9953 1.13 14.3 246.8 4.78 2437 14.3 0.9952 0.69 14.1 250.4 5.98 2861 14.1 0.995 0.27 13.0 253.6 7.95 2853 13.0 0.9954 0.08 11.7 265.6 12.6 2989 11.7 0.994 As described in Section 5.2.2, the two terms of the exponential fit represent two length scales, a short range one that dies out after on order 180-750 µm, and a long range one on the order of millimeters. Based on the long fin analogy, a reasonable theory is that the short range is dominated by higher-dimensional (both through-interposer and lateral) conduction with large vertical temperature gradients, while at long range (far from the chip) the temperature variation through the thickness of the interposer is less severe. At a first approximation, this long range behavior would resemble a fin exposed to a fluid stream, although as subsequent modeling will show the interaction of the microgap coolant with the interposer becomes particularly important. Focusing on the second term, which is sufficient for all but the shortest interconnect lengths, reveals that the glass interposers tested do have a rapid temperature extinction, as captured by lower profile length decay constants shown in Figure 32. However, this alone is not enough to ensure a region of lower target temperature on the interposer surface at a given distance, since surface temperature is dictated by 𝐴2 as well. In the downstream regions measured, the increase in 𝐴2 resulting from the lower conductivity of the glass samples offsets the gains resulting from low 𝜆2. The normalized measured temperature profiles for all five interposers, tested at 2.83 cm3/s flow7 are 7 The 2.65 cm3/s results for sample GL A2 are used due to lack of 2.83 cm3/min data for that sample. 80 plotted in Figure 33, along with the fitted curves obtained with parameters from Table 4 through Table 8 (with 𝐴1, 𝐴2 normalized by chip power). The figure shows that within the field of view of the IR camera, none of the glass interposers exhibit lower surface temperature rise than the silicon interposer. Figure 32: Comparison of the 𝝀𝟐 parameter of each interposer subjected to varying flowrate. Error bars are not shown; error in flowrate is ±0.11 cm3/s, error in 𝝀𝟐 is 3%. 81 Figure 33: Comparison of spatial thermal profiles for each interposer under identical flow conditions. Temperature rise normalized by heater power. Estimated error in temperature rise is ±5.1%, uniform across each sample, plus limits in camera resolution at individual pixels of ±0.1K. Estimated error in aligning profiles at chip edge is ±11µm. Conjugate Heat Transfer Modeling To better understand the interrelation between the water flow in the microgap and the temperature field in the interposer, a conjugate heat transfer model was built and investigated using the ANSYS Fluent CFD package [51]. A simplified geometry is used, consisting of a half-width fluid channel (2.5 mm) and interposer (5 mm), both 14 mm long. A silicon half-chip is placed with its centroid 5 mm from the inlet end of the system. The resistance due to thermal grease is ignored, idealizing the fact that it has little impact on the temperature field in the interposer after heat has left the chiplet. For Temperature Profile Comparison 1W Normalized 2.83 cm3/s Flow S ca le d T em p er at u re R is e [K /W ] 82 the glass interposer, an anisotropic conductivity with 𝑘𝑧 = 80 W/m-K and 𝑘𝑥 = 1 W/m- K, approximating the effective conductivities of the 22% fill factor sample GL A3. A uniform velocity of 2.83 m/s is imposed on the 2.5mm x 200 µm inlet, representing the 2.83 cm3/s flowrate through the full-width experimental system. The outlet is specified as a constant pressure, and 0.5W of heat is distributed evenly across the upper surface of the half-chip. Velocity symmetry is specified at the fluid mid-plane, and an adiabatic condition for the solid volumes. The coupled momentum and energy solutions converge to a three order of magnitude residual reduction after 80 iterations. Grid independence is established at a 20 µm grid spacing within the fluid, and a 40 µm spacing within solid the volumes. Since flow is laminar (Re≈1100) for this simulation, the SIMPLE finite volume solver is used. Shown in Figure 34 is the temperature field solution in the chip, interposer, and fluid. Of note is that even though the volume averaged water temperature rises less than 0.1 K from inlet to outlet, there is definite heated plume downstream of the chiplet that is reflected as an increase in interposer surface temperature in those regions. This is due to the laminar boundary layer redepositing heat picked up from the interposer beneath the chip and transferring it back to the interposer downstream. This is highlighted in Figure 35, showing the wall heat flux at the underside of the interposer, which changes sign only ~500 µm downstream of the chip. The wall heat transfer coefficient ranges from 26,900 to 21,000 within the chiplet footprint, at the upstream and downstream edges, respectively. 83 Figure 34: Simulated temperature rise in chip and interposer for sample GL A3 Figure 35: Wall heat flux at fluid-interposer boundary. The downstream region of negative heat flux is highlighted with the dashed enclosure. Right: plotting only contours of negative heat flux. This highly flow-direction dependent behavior is contrasted against the silicon interposer temperature field shown in Figure 36. Because of higher heat spreading in directions perpendicular to the flow direction, the impact of the downstream boundary layer is reduced. This suggests that in the downstream direction with laminar boundary layers, the flow mechanics create an additional disadvantage for via-enhanced low-k interposers when compared to silicon. 84 Figure 36: Silicon 1W comparison When deciding in which interposer regions to focus the IR measurements, the fact that areas downstream represent a worst case was given strong consideration. This means that the surface temperature rise (per unit chip power) at a given distance from the heated chip is maximum in the downstream case, and that the thermal coupling between a hosted device and the central chip separated by that distance is bounded by that maximum. But the experimental results revealed that the interposers tested could not outperform silicon in that surface location. The modeling suggests however, that simply focusing in other areas may reveal different behavior. Furthermore, by increasing flow to the point that a turbulent transition occurs, the thermal boundary layer can be disrupted, mitigating its heat trapping effect. Upstream Microgap Experiment Guided by the modeling results, a final set of tests is performed and reported here. Since the best performing via array type had the integrated spreading pads, the sample 85 selected was the previously untested B3. This sample has a slightly higher copper fill factor compared to B1 (22.6% vs 19.6%). Unfortunately, during the course of the prior testing many of the chip heaters became damaged, scratched, or chipped by the tungsten point probe tips. The few remaining chiplets were partial heaters resulting from dicing misalignment. The heater selected for this test (nominal resistance 460 Ω), and the modified position and orientation necessary to match the probe jig’s probe pattern is shown in Figure 37. Additionally, a higher flowrate gear pump is used to provide a water flow rate of 16.6 cm3/s in order to achieve turbulent flow within the gap. This means that this revised experiment is not directly comparable to the previous ones, and is instead designed to promote and observe a crossover distance where the glass interposer outperforms silicon. The same heater, chip location and flowrate are thus replicated on a new silicon interposer sample as well. A final modification to the experiment is made, in that the chiplet is driven at a higher power (3.32 W) when on the silicon interposer, to improve the magnitude of the temperature rise relative to the accuracy of the IR camera. At this power level the heater temperature rise is roughly comparable to that seen with 1W of power on the glass interposer, so the negligible natural convection assumption made earlier equally applies. 86 Figure 37: Heater chiplet positioning for revised microgap resting. Sample B3, water flow from left to right. The normalized upstream surface temperature rise for the two interposers is plotted in Figure 38. Here, the vertical axis is presented on a log scale to highlight the fact that the spatial temperature profiles do cross, at a distance of about 1.38 mm from the chip edge. The scaled temperature rise at that crossing point is about 0.24±0.013 K/W. Note that because the Si data is scaled down by a factor of 3.32, the noise in the tail region (where the log scale magnifies small differences in temperature) has also been scaled down. In the raw data, the pixel-to-pixel standard deviation is about 0.06K for both the silicon and the glass sample. The two-term exponential fitting coefficients are presented in Table 9. As before, the magnitudes of the terms (𝐴1 and 𝐴2) as reported here are un-normalized with respect to the heater power. Uncertainties in 𝜆1 and 𝜆2 are 3%, and uncertainties for 𝐴1 and 𝐴2 follow from Equation (39). 87 Figure 38: Upstream interposer temperature rise per watt of heater power. Estimated error in temperature rise is ±5.1%, uniform across each sample, plus limits in camera resolution at individual pixels of ±0.1K. Estimated error in aligning profiles at chip edge is ±11µm. Table 9: Upstream Two-Term Fitting Coefficients Sample A1 [K] 𝜆1 [μm] A2 [K] 𝜆2 [μm] Power [W] R 2 GL B3 16.1 113.2 7.70 401.6 1.04 0.9973 Silicon 9.8 42.4 2.90 1064.5 3.32 0.9947 This is the first experimental evidence of a via-enhanced low-k interposer outperforming silicon at distance scales appropriate for 2.5D heterogeneous integration applications. A temperature sensitive device located 1.37 mm upstream on either interposer will see a maximum thermal coupling of 0.24 K per watt of power dissipated at the central chip, and beyond that distance it will experience a reduced coupling when hosted on the enhanced glass than when hosted on silicon. This present breakeven value is quite low, which means it is relevant only for extremely disparate device thermal operating characteristics. 0.01 0.10 1.00 10.00 100.00 -200 200 600 1000 1400 1800 2200 S ca le d T em p er at u re R is e [K /W ] Distance From Chip Edge [µm] Scaled Temperature Rise, 1W B3, upstream Si, upstream 88 A crucial step to further improvement is increasing the through-substrate conductivity, 𝑘𝑧, of the enhanced glass interposers. With the current fill material and diameter-to-pitch ratio, the interposer 𝑘𝑧 is about 68 W/m-K based on a rule-of-mixtures estimate (not even taking into account microspreading resistance as described in Chapter 0). This is a far cry from the 150 W/m-K available to silicon for through-substrate conduction. Increasing 𝑘𝑧 will not only reduce both the power chip’s and sensitive device’s self heating thermal resistance, but will bring the breakeven distance closer to the power chip and increase the breakeven thermal coupling resistance. This will increase the available range of application to more types of HI systems, while allowing shorter interconnection lengths in all those via-enhanced low-k interposers are suited to. 89 6.0 MODELING THERMAL MICROSPREADING RESISTANCE IN VIA ARRAYS As noted in Chapter 0, fully detailed finite element models – incorporating individual thermal vias into the analysis – provide the best fidelity of the via array at the cost of cumbersome setup and extended meshing and simulation time. Replacing interposer regions equipped with via arrays with an equivalent homogeneous medium allows a more rapid assessment of the design and available tradeoffs inherent in a low-k interposer isolation approach. This homogenization is accomplished by extracting effective thermal conductivity properties from an array unit cell, as described in the literature review. Notable for the arrays investigated in this project, however, is the introduction of an additional thermal resistance to heat flow through the thickness of the interposer. This microspreading resistance is not treated in existing effective conductivity literature, and must be accounted for in order for a homogenized array to faithfully represent a fully detailed model. Though differing in various details of implementation for different configurations, the essential procedure for determining the vertical effective 𝑘 of a TXV unit cell remains the same. The lateral sides of the cell are insulated and heat is induced to flow through the cell in a vertical direction, aligned with the axis of the via. Because the ultimate thermal pathway through a thermal stack, including a TXV array, is usually down and out through a heat sink or PCB, a convenient convention is to assign “down” as the direction of heat flow through the cell. Because this Chapter is focused on the considerations and outcomes of this vertical analysis, the term “effective conductivity” will be understood to mean the property in this direction (i.e keff,z), unless otherwise specified. 90 This effective conductivity, keff,z is evaluated by determining the drop in average temperature between two horizontal reference surfaces in relation to the total heat flow between them. Then, considering the area of the surfaces and the distance separating them, the keff,z of the material between them is given by Fourier’s Law, i.e. 𝑘𝑒𝑓𝑓,𝑧 = 𝐿 𝐴 ?̇? ∆?̅? (40) where 𝐿 is the distance separating the reference surfaces, 𝐴 is their cross-sectional area (i.e. that of the unit cell), and ?̇? and ∆?̅? are the total heat and average temperature drop, respectively. These last two quantities are determined using ?̇? = ∫?̇?𝑢 ′′𝑑𝐴 𝐴 = ∫?̇?𝑙 ′′𝑑𝐴 𝐴 (41) ∆?̅? = ∫ 𝑇𝑢𝑑𝐴𝐴 − ∫ 𝑇𝑙𝑑𝐴𝐴 𝐴 (42) where ?̇?′′ is the heat flux normal to the surface in W/m2, 𝑇 is the temperature in K or °C, and the subscripts 𝑢 and 𝑙 refer to values at the upper and lower surfaces respectively. This framework can be applied to conical or tapered vias, as well as the cylindrical vias considered here. It is also applicable to vias with interfacial oxide, buffer, or isolation layers between the via material and the substrate. Shown in Figure 39 are examples of a via unit cells, with definitions of vertical (in the z-direction) and lateral (along x or y) directions. Also shown are the surfaces where convection or temperature boundary conditions are applied (red and blue). The upper and lower reference surfaces used in this Chapter (Equations (41)(42)), are always at the ends of the copper via; they 91 coincide with the red and blue in Figure 39(a), but in Figure 39(b) the upper surface is at the interface of the via and the grey volume representing a contacting film. Figure 39: Via unit cells used in Chapter 0. (a) Cu-glass unit cell used to investigate convection boundary conditions. (b) Cu-glass unit cell used to investigate contacting films (dark grey volume). By placing the reference surfaces at the planar interface between the TXV- enhanced substrate and any bond pads and surface oxide layers, the behavior of the entire length of the via portion of the unit cell can be captured in keff,z. The boundary conditions applied to the top and bottom faces of the unit cell, as well as the types and amount of material to include between the boundaries and the reference surfaces, should be driven by application. These choices affect how the heat flux is distributed as it enters the TXV array and, ultimately, the value of keff,z. Common choices in the surveyed literature result in reference surfaces that are at, or near, uniform temperature. For such boundary conditions, heat flow in a cylindrical via unit cell is one-dimensional. Under this situation, since flux lines do not cross laterally from one material to another, a rule-of-mixtures can be used to model keff,z, [23, 52]: (a) z (b) y x 92 𝑘𝑒𝑓𝑓,𝑧 = 𝜙𝑣𝑘𝑣 + 𝜙𝑜𝑥𝑘𝑜𝑥 + (1 − 𝜙𝑣 − 𝜙𝑜𝑥)𝑘𝑠 (43) where 𝑣, 𝑜𝑥, and 𝑠 subscripts correspond to the via, interfacial oxide, and substrate, 𝜙 is the (areal) fill fraction, and 𝑘 the material thermal conductivity. It will be shown, however, that this keff,z is the maximum value obtainable from a cylindrical TXV array, and that modeling choices that lead to non-isothermal reference surfaces may produce substantially lower effective conductivities. This is due to lateral heat spreading within the low conductivity substrate, even though the net heat flow is vertical and no heat leaves the sides of the cell. This lateral spreading is termed micro- spreading to distinguish it from common system level resistances that arise due to thermal constriction [29, 33, 46]. An example of this lateral heat spreading (leading to a micro-spreading resistance) is shown in Figure 40. As will be shown, this micro- spreading resistance behaves as a skin effect that acts in series with the inherent one- dimensional resistance of the cell. Because the intent of this article is to illustrate the effect that the choice of geometry, boundary conditions, and contacting materials can have on the keff,z of the TXV array, all material properties will be assumed to be independent of temperature. While this assumption can be relaxed at the cost of computational expense, this is a reasonable assumption for applications where the temperature difference across the array is small. Thus, the conductivity of the via and substrate at the expected average array temperature should be used when applying the results of this analysis to a particular system. Effect of Boundary Conditions on Array Vertical Thermal Resistance As power dissipation in electronic systems continues to increase, lower thermal resistance solutions including thinner chips, higher conductivity substrates, as well as 93 “inwardly-migrating” active thermal management measures [53] have proliferated. The close proximity of these active components to microfluidic coolers establishes a need for considering a broader range of thermal boundary conditions on the faces of the via unit cell, including constant heat flux and convective conductances, as well as isothermal conditions. Equation (44) provides an example of a convection condition: ℎ(𝑇𝑎 − 𝑇(𝑥, 𝑦)) = 𝑘(𝑥, 𝑦) 𝜕𝑇 𝜕𝑧 (𝑥, 𝑦) (44) where ℎ is the constant heat transfer coefficient in W/m2-K and 𝑇𝑎is the ambient fluid temperature. In this section, these boundary conditions will be applied directly to the TXV surface, meaning that no pads, surface oxides, or other materials are considered. The top and bottom faces of the unit cell are then the reference surfaces used to determine keff,z. Once boundary conditions are specified, changing the temperature of an isoflux boundary or the fluid temperature of a convection boundary causes ?̇? and ∆?̅? to change in constant proportion, since material properties are assumed temperature independent. In this way keff,z is independent of choice of reference temperature. Thus, convection boundary conditions can be seen as a continuum linking isothermal boundaries and isoflux ones. As ℎ → ∞ the boundary becomes isothermal at 𝑇𝑎. As ℎ → 0 the flux crossing the boundary becomes uniform from point to point and 𝑘𝑒𝑓𝑓,𝑧 = 𝑙𝑖𝑚 ( ?̇? ∆?̅? ) 𝐿 𝐴 as ?̇?, ∆?̅? → 0 (45) When the boundary conditions on the upper and lower faces have the same ℎ, or are both isothermal or both equal uniform flux, the resulting flow of heat is symmetrical about the mid-plane between the faces, and hence the mid-plane is an isotherm. An 94 example of this is shown in Figure 40. An equivalent half-cell model can be constructed using an isothermal boundary at one face and a copy of the original condition at the other; this cell will possess the same keff,z. Cells with asymmetrical boundary conditions will contain a planar isotherm offset from the mid-plane. It is possible to decompose such a scenario into two sub-cells, each with an isothermal and non-isothermal boundary, but the necessary length of each cell is not known in advance. Reflecting this insight, the FEM study will present results of keff,z for cells with one isothermal boundary and one general boundary, serving as a solution "building block” and allowing cells with symmetrical boundaries to be constructed by symmetry, while providing a starting point for cells with asymmetrical boundaries. As a contrast to the isoflux boundary conditions shown in Figure 40, Figure 41 illustrates the heat flux profile found under the one-dimensional conduction stemming from isothermal boundary surfaces. The flux in the via is proportionately higher than that in the substrate by the ratio 𝑘𝑣/𝑘𝑠. This condition prevails throughout the whole length of the unit cell; a single horizontal path is shown to allow the otherwise overlapping vector labels to emphasize the flux disparity. (Note that the vector length plot parameter in Figure 40 was reduced to scale down such overlap; relative vector lengths are not comparable between Figure 40 and Figure 41.) 95 Figure 40: Heat flux vectors at a vertical cross-section of a unit cell. The top and bottom faces of the cell have isoflux boundary conditions of the same magnitude. The mid-plane contains an isotherm, as evidenced by the parallel flux vectors there. Units are in W/m2 Figure 41: Heat flux vectors resulting from isothermal cell boundary condtions. Results obtained along a path through the via center and parallel to the cell upper and lower surfaces (e.g. a horizontal subselection from the cross-section in Figure 40). Units W/m2 Outcome of FEA – Convection Boundaries A base TXV array geometry was chosen, consisting of 60 µm diameter cylindrical copper vias arranged in a 100 µm pitch, aligned array embedded in a 200 µm thick glass substrate. Motivated by interest in enhanced low-conductivity interposers, these dimensions are within the realm of current manufacturing practice [54] and provide a high copper fill factor of 28%. The thermal conductivities for the glass and copper are 1 96 and 400 W/m-K, respectively. While the phenomenon of micro-spreading occurs to some degree in any via unit cell, the fitting parameters presented in this section are specific to this cell’s materials and lateral dimensions. However, the methodology and correlation form are broadly applicable. Modeling the cell in ANSYS finite element software [41], and applying an isothermal boundary to the bottom face of the cell and a convection boundary with varying ℎ to the top, the thermal response and thus keff,z of the cell was calculated using Eqs. (1-3). Cells subjected to very high ℎ (1010 W/m2-K) were modeled to illustrate that keff,z for these cells agrees with those subjected to two isothermal boundaries. Cells subjected to very low ℎ (1 W/m2-K) were modeled to illustrate that keff,z for these cells agrees with those subjected to one isoflux and one isothermal boundary. Plotted in Figure 42 are the keff,z values for the 200 µm thick substrate as a function of applied ℎ, as well as for fifteen other substrate thicknesses ranging from 25 to 500 µm. What is immediately apparent is that in the isothermal limit, all substrate thicknesses exhibit the same keff,z, at 114.5 W/m-K. This agrees well with the rule of mixtures prediction of Equation (43), setting 𝜙𝑜𝑥 = 0 and 𝜙𝑣 = 28.3%. As the applied ℎ decreases, however, the effective conductivity exhibits an orderly reduction, the final magnitude of which depends on the thickness of the substrate. Substrates with large thicknesses, and hence high aspect ratio vias, display the least reduction in keff,z while low aspect ratio systems are affected the most. 97 Figure 42: TXV array keff,z as computed by FEA The behavior of the unit cell can be explained by recasting the effective conductivity into a thermal resistance. The total (vertical) resistance 𝑅𝑇 of the cell is given by 𝑅𝑇 = 𝐿 𝐴 𝑘𝑒𝑓𝑓,𝑧 = ∆?̅? ?̇? (46) Where Δ?̅? is the difference of the cross-sectional average temperature from the top of the cell to its bottom surface, and 𝐴 its cross-sectional area. Plotted in Figure 43 is 𝑅𝑇 as a function of substrate thickness for five heat transfer coefficients. The curve with the lowest values has the highest ℎ, corresponding to an isothermal boundary on the top face as well as the original isothermal condition on the bottom face. The fact that the resistance for these conditions increases linearly with cell thickness and has a positive resistance intercept at zero thickness confirms the idea that heat flows one-dimensionally under these conditions. For thick enough substrates, convection boundary curves evolve along a line above and parallel to the isothermal boundary curve. 1 1 0 1 0 0 1 0 0 0 1.E+00 1.E+02 1.E+04 1.E+06 1.E+08 1.E+10 E ff ec ti v e C o n d u ct iv it y [ W /m -K ] Applied h [W/m2-K] keff,z: ks = 1, kv = 400 500 350 250 200 150 100 70 50 35 25 114.5 Sub. Thick [µm] 25 µm 500 µm Increasing Aspect Ratio 98 Figure 43: Via cell total thermal resistance, calculated from keff,z data This suggests that the total resistance of the unit cell can be ascribed to the sum of two effects. One is the one-dimensional resistance that linearly increases as the length of the cell increases, 𝑅1𝐷. The other, 𝑅𝜇𝑠𝑝, is a resistance that grows quickly for thin substrates, and then converges to a constant value that depends on the applied ℎ. 𝑅𝜇𝑠𝑝 for each case can be obtained by subtracting the 𝑅1𝐷 from the total resistance. In this way, keff,z can be modeled as 𝑘𝑒𝑓𝑓,𝑧 = 𝐿 𝐴(𝑅1𝐷 + 𝑅𝜇𝑠𝑝) (47) where 𝑅1𝐷 = 𝐿 𝐴[𝜙𝑣𝑘𝑣 + (1 − 𝜙𝑣)𝑘𝑠] (48) and 𝑅𝜇𝑠𝑝 is identified as an ultimately (in the limit of sufficient cell thickness) constant microspreading resistance that depends on the general boundary condition, the material properties and the lateral dimensions of the unit cell. This spreading resistance is due to the lateral flow of heat within the unit cell as flux entering the low conductivity 0 200 400 600 800 1000 1200 1400 1600 1800 0 100 200 300 400 500 T h er m al R es is ta n ce [ K /W ] Substrate Thickness [µm] Total Vertical Thermal Resistance 1E+00 1E+04 1E+05 5E+05 1E+10 "Thick Substrate" behavior Applied h [W/m2-K] 99 substrate seeks the lower resistance path through the central via. This lateral flux component is visible in Figure 40. Figure 44 shows this 𝑅𝜇𝑠𝑝 plotted versus the convection boundary heat transfer coefficient. 𝑅𝜇𝑠𝑝 reaches its maximum value when ℎ is so low as to create a near-isoflux boundary. As ℎ increases to create near-isothermal conditions, 𝑅𝜇𝑠𝑝 drops to zero. A correlation for 𝑅𝜇𝑠𝑝 versus h is plotted as the curve connecting the points: 𝑅𝜇𝑠𝑝 = 𝑅𝜇𝑠𝑝,𝑚𝑎𝑥 1 + ( ℎ𝑃 𝑘𝑠 𝐻0⁄ )𝛽 (49) where 𝑅𝜇𝑠𝑝,𝑚𝑎𝑥 is the maximum spreading resistance seen with an isoflux boundary (here, 1240 K/W), 𝑃 is the array pitch (i.e. unit cell width), and 𝐻0 and 𝛽 are dimensionless fitting parameters. The best fit for the data in Figure 44 is obtained with 𝐻0 = 15.5 and 𝛽= 0.96. Figure 44: Microspreading resistance of thick TXV substrates. Each point is the intercept of the linear asymptote for data sets of the type in Figure 43 (there were three not included for clarity). The line connecting the points is the correlation given by Eq. (6). 0 200 400 600 800 1000 1200 1400 1E+00 1E+02 1E+04 1E+06 1E+08 1E+10 M ic ro sp re ad in g R es is ta n ce [ K /W ] Applied h [W/m2-K] Thick Substrate Microspreading Resistance vs. h 100 Surface Films and Material Interfaces Because no component of a thermal stack exists in isolation from the entire package, it is important to consider how various layers interact to affect the overall performance of the via-ed layer or substrate. In this section, the effect of contacting materials bonded to the surface of a TXV is investigated. These materials may be die attach materials, metallization films, bulk substrates or even back-end-of-line (BEOL) layers. The effect of surface oxide layers and/or bond pads could also be modeled as that of a contacting material. Finite element modeling was performed in a fashion similar to the last section. An isothermal boundary was placed at the bottom face of 60 µm diameter, 100 µm pitch copper-glass via cell of varying thickness. Next, a film layer of varying thickness and conductivity was placed on the top face of the Cu-glass region. A boundary condition was then placed on the exposed top surface of the film layer, and all other surfaces insulated. The interface between the film and via unit cell was treated as a perfect thermal contact. Isothermal and isoflux film boundary conditions were investigated. The keff,z of the Cu-glass is then evaluated using Eqs. (1-3) by placing the upper reference surface at the glass-film interface and the lower at the bottom of the cell. In this way the resulting keff,z measures the heat flow in just the TXV array itself, and not the film. Equivalent thermal resistance results can be obtained by including in the calculation the temperature drop across the film, which would then be subtracted out as an additional, static thermal resistance. Plotted in Figure 45 are four solution sets for keff,z of a 200 µm thick cell in contact with a film. Half of the curves are solutions for films of conductivity 𝑘𝑓 = 10 101 W/m-K, the other half with film conductivity 𝑘𝑓 = 40 W/m-K. The sets with diamond markers are evaluated from a system with an isoflux film boundary; the sets with diamond markers from an isothermal film boundary. For very thin films, the keff,z values approach the values the cell possessed with an isothermal or isoflux boundary applied directly to the top of the substrate (marked with horizontal dashed lines). As the film thickness increases, however, the effective via cell conductivities, keff,z , converge to a value that is independent of the boundary condition on the exposed surface of the film. At this point, the boundary condition on the edge of the film is so far away from the Cu- glass region that its effect on the thermal conductivity is negligible and only the interaction of the via, substrate, and film material (conductivity) play a role in keff,z. Figure 45: Evolution of 𝒌𝒆𝒇𝒇,𝒛 of a TXV array as an adhered film increases in thickness. Film conductivity is 10 and 40 W/m-K, and substrate thickness is 200 µm. Plotted in Figure 46 are these converged keff,z values for sufficiently thick films of various conductivities and several substrate thicknesses. As in Figure 42, conditions that 0 20 40 60 80 100 120 0 5 10 15 20 25 30 35 40 45 50 T X V E ff ec ti v e C o n d u ct iv it y [ W /m -K ] Film Thickness [µm] keff,z vs film thickness 14.15 W/m-K 114.5 W/m-K kf 10 W/m-K 40 W/m-K B.C. Isoflux Isothermal 102 lead to more uniform substrate surface temperatures result in keff,z closer to the rule-of- mixtures value. Instead of a high ℎ convection boundary, here it is due to an interface with a high conductivity material. At the opposite end, the lowest conductivity film material produces a keff,z close to that of an isoflux boundary. Figure 46: keff,z versus contacting material thermal conductivity for different substrate/cell thicknesses Recasting the keff,z into thermal resistance and extracting the 𝑅𝑠𝑝 component, as in the last section, results in the values plotted in Figure 47. The curve in the plot is given by an analogous correlation: 𝑅𝜇𝑠𝑝 = 𝑅𝜇𝑠𝑝,𝑚𝑎𝑥 1 + ( 𝑘𝑓 𝑘𝑠 𝜅0⁄ )𝛽 (50) where 𝜅0 and 𝛽 are fitting parameters. Setting 𝜅0 = 2 and keeping 𝛽= 0.96 produces the curve shown. 𝑅𝑠𝑝,𝑚𝑎𝑥 remains at 1240 K/W since the geometry and materials of the TXV array are unchanged. 1 1 0 1 0 0 0.01 0.1 1 10 100 1000T X V E ff ec ti v e C o n d u ct iv it y [ W /m -K ] Contacting Material Conductivity [W/m-K] keff,z vs kf 1000 500 300 200 140 100 70 50 Sub Thick. [µm] 50 µm 100 µm 103 Figure 47: Micro Spreading resistance versus contacting material conductivity. Each point is obtained from FEM results in Figure 46. The line connecting the points is the correlation given by Eq. (7). From the work described above emerges a method of estimating the keff,z of an entire cylindrical TXV array under general conditions. Since the micro-spreading effect is largely contained in the near-surface volume of the via-ed unit cell, for a thick enough substrate, 𝑅𝜇𝑠𝑝 is insensitive to the length of the via. Consequently, two such substrate cells can be joined at the isothermal boundary condition, resulting in a larger cell with general boundaries on its upper and lower faces. The vertical effective conductivity of such a TXV array is then 𝑘𝑒𝑓𝑓,𝑧 = 𝐿 𝐴[𝑅1𝐷 + (𝑓𝑢 + 𝑓𝑙)𝑅𝜇𝑠𝑝,𝑚𝑎𝑥] (51) where 𝑅1𝐷 = 𝐿 𝐴[𝜙𝑣𝑘𝑣 + (1 − 𝜙𝑣)𝑘𝑠] (52) and 𝑢 and 𝑙 refer to the upper and lower surfaces of the TXV array and 𝑓 is an “adjustment” factor depending on the conditions at that surface. For a convection boundary at the surface 0 200 400 600 800 1000 1200 1400 0.01 0.1 1 10 100 1000S p re ad in g R es is ta n ce [ K /W ] Contacting Material Conductivity [W/m-K] Thick Substrate MicroSpreading Resistance vs. kf 104 𝑓 = [1 + ( ℎ𝑃 𝑘𝑠 𝐻0⁄ ) 𝛽] −1 (53) and for a material interface 𝑓 = [1 + ( 𝑘𝑓 𝑘𝑠 𝜅0⁄ ) 𝛽] −1 (54) There are a few assumptions and restrictions upon which Eqs. (8-11) rely. First, the substrate containing the TXV array is assumed to be thick enough for the spreading resistances associated with each boundary to reach a constant value. For the materials, via diameter, and pitch used in this subchapter that thickness is about 120 µm. This corresponds to a via aspect ratio of 2. Applying Eqs. (8-11) to insufficiently thick substrates will result in an underestimate of keff,z, with the maximum error occurring when both TXV surface boundaries are isoflux and 𝑓𝑢 + 𝑓𝑙 = 2. This is because Eqs. (8-11) assume the micro-spreading resistance skin effect is fully developed; in via cells thinner than the thickness of the skin effect the actual 𝑅𝜇𝑠𝑝 is less. Second, the thickness of any contacting material used in Eq. (15) must be large enough to disregard the conditions on the other side of the material or film. As suggested by Figure 45, for the array studied here, this thickness is about 35 µm. Higher aspect vias and cells will reduce this thickness. Insufficiently thick contacting films will allow conditions on the exposed side of the film to influence the 𝑅𝜇𝑠𝑝 attributable to the film- TXV interface. Third, the contacting materials considered have been of uniform conductivity and thickness. In practical TXV arrays, contacting materials are often heterogeneous and/or anisotropic. 105 Extension to Axisymmetric Via Cells The previous two sections outline the methodology for modeling micro-spreading resistances using a particular via array – one with 60 µm diameter copper vias in an aligned array with spacing of 100 µm in a glass substrate. The particular correlation determined for that array can be extended to other via systems, providing designers the ability to predict the thermal response of candidate arrays prior to modeling them. The first method of extension is to consider arrays possessing cells with uniform scaling of cells that have already been modeled. For example, consider a cell with material conductivities twice that of the copper-glass cell modeled above: the maximum spreading resistance (and 1D resistance) will drop by a factor of two, and Eqs. (14) and (15) have already been constructed so as to account for the effect of the scaling. Uniform scaling of cell lateral dimensions can also be accounted for. As long as the cell height and any relevant film thickness are still sufficient for the response magnitude to have converged to a constant value, the spreading resistance will decrease by the same multiplicative factor by which the dimensions have increased while the 1D resistance will decrease by the square of that factor. This means that on an area basis, the 1D resistance will be unchanged (a logical result since the via fill factor is unchanged) while the areal spreading resistance (in units of mm2-K/W, for example) will have increased in proportion to the increase in lateral dimension. Again, Eqs. (14) and (15) are equipped to handle such scaling. Thus, the via arrays for which the determined correlation does not yet provide predictions are those that have different relative conductivities or relative lateral 106 dimensions. Different material combinations, via fill factors, and via arrangements will in general require different fitting parameters. In an effort to provide a starting point for a more general correlation, a FEA survey of axisymmetric via cells was performed. An axisymmetric domain was chosen for both computational speed and to provide an idealized baseline against which square, rectangular, or hexagonal unit cells can be compared. The survey consists of five via conductivity ratios, (𝑘𝑣/𝑘𝑠), and twelve non- dimensional via diameters, (𝑑/𝑃∗), interacting with ten convection boundary coefficients and ten contacting film conductivities. These varying cell parameters are presented in Table 1. This results in a total of 1,200 unique simulations being represented. The 1D resistance of the cells was also measured by applying isothermal boundary conditions to the finite element models. Table 10: Cell parameters used in axisymmetric micro-spreading survey (𝑘𝑣/𝑘𝑠) 1000, 400, 100, 20, and 3 (each with 𝑘𝑠 = 1) 𝑑, in µm 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 105 (𝑑/𝑃∗) 0.044, 0.087, 0.18, 0.27, 0.35, 0.44, 0.53, 0.62, 0.71, 0.80, 0.89, and 0.93 ℎ, in W/m2-K 1, 1×104, 3×104, 1×105, 5×105, 1×106, 3×106, 1×107, 1×108, and 1×1010 𝑘𝑓, in W/m-K 0.01, 0.5, 5, 10, 20, 40, 100, 200, 500, 1000 The cell outer diameter was fixed at 𝑃∗ = 2/√𝜋 ∙ 100µm (≈112.84 µm) so as to have the same cross sectional area as the cells from the preceding sections. The height was fixed at 400 µm, after a series of simulations using 700 µm agreed to four significant figures, indicating that 400 µm is sufficient to be sure the magnitude of the spreading resistance converged. A similar effort resulted in the choice of 100 µm for the thickness of the films used in such simulations. The substrate conductivity was held at 1 W/m-K, and the via conductivity varied. 107 A mesh convergence study concluded that square high-order plane elements (PLANE77 in ANSYS) with maximum side lengths of 0.2 µm provide the necessary accuracy to resolve the spreading resistance compared to the 1D resistance, even in the cases with the smallest ratio of via to substrate conductivity. The maximum spreading resistance seen in each cell is plotted in Fig. 11. Since increasing the via conductivity with fixed substrate conductivity serves to decrease the 1D resistance (as well as the total resistance) while the spreading resistance is seen to increase, the spreading resistance is clearly most important in systems with high conductivity ratios. Figure 48: Maximum cell spreading resistance as a function of Non-Dimensional via diameter and conductivity With each of these points is associated a sigmoidally shaped curve like those in Figs. 6 and 10, which depends on the nature of the boundary condition applied. When normalizing each curve by its maximum spreading value, they do not lie on top of each other since the fitting parameters for each cell configuration are somewhat different. Adding in a dependence on the relative via diameter (𝑑/𝑃∗) and relative conductivity 0 500 1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500 0.00 0.20 0.40 0.60 0.80 1.00 S p re ad in g R es is ta n ce [ K /W ] Non-Dimensional Via Diameter (d/P*) Maximum Spreading Resistance 1000 400 100 20 3 kv / ks 108 (𝑘𝑣/𝑘𝑠) to relations like Eqs. (14) and (15) can bring them to closer agreement. The modified relations are 𝑓 = 1 1 + 𝜁 (55) where 𝜁 = [( ℎ𝑃∗ 𝑘𝑠 ) 𝐶 ( 𝑑 𝑃∗ ) 𝛾 (1 − 𝑑 𝑃∗ ) 𝛿 ] 0.95 (56) for convection boundaries, and 𝜁 = ( 𝑘𝑓 𝑘𝑠 )𝐶 ( 𝑑 𝑃∗ ) 𝛾 (1 − 𝑑 𝑃∗ ) 𝛿 (57) for contacting films, and 𝐶, 𝛾, and 𝛿 are parameters that depend on the conductivity ratio according to Tables 2 and 3, below. Table 11: Correlation parameters for convection boundaries 𝒌𝒗/𝒌𝒔 1000 400 100 20 3 𝐶 0.261 0.235 0.293 0.211 0.195 𝛾 1.5 1.4 1.4 1.13 0.75 𝛿 1 0.9 0.9 0.81 0.66 Table 12: Correlation parameters for material contact boundaries 𝒌𝒗/𝒌𝒔 1000 400 100 20 3 𝐶 0.739 0.739 0.739 0.739 0.739 𝛾 0.67 0.67 0.64 0.5 0.1 𝛿 0 0 0 0.1 0.1 The form of the correlations in Equations (56) and (57) is based on the observed variations of 𝐻0, 𝜅0, and 𝛽 with (𝑑/𝑃 ∗) and (𝑘𝑣/𝑘𝑠), as obtained by a minimization of the calculated sum of the squared discrepancy. The proposed form attempts to strike a balance between accuracy and parsimony. For example, although 𝛽 does vary, it does so weakly enough that a constant value of 0.95 and 1 for convection and material contact, 109 respectively, can provide suitable accuracy. A particularly troublesome set of cells are ones with very small (𝑑/𝑃∗) ratios. The basic form of the fit, Eqs. (14) and (15) produces larger and larger rms error during attempts to find the best fit as (𝑑/𝑃∗) approaches zero. As a result, the final form proposed in Equations (55(57) and the values given by Tables 2 and 3 are tailored for the cells with better behaved via diameters. This is done by excluding via cells with diameters of 5 µm or 10 µm. This corresponds to non- dimensional via diameter, (𝑑/𝑃∗), of approximately 0.044 and 0.089, respectively. Then, for each set of remaining cells with a particular boundary type and (𝑘𝑣/𝑘𝑠) ratio, 𝐶, 𝛾, and 𝛿 are found using a rms error minimization strategy. Each cell resistance response is normalized by the appropriate maximum resistance from Fig. 11, and the resulting value (ranging from 0 to 1) is plotted using the proposed corrected boundary parameter 𝜁. Each of these data points is compared against the idealized fit from Equation (55). The result of this process for all cells (including those with the smallest vias) for the parameter values in Tables 2 and 3 is shown in Figure 49. Varying any of the correlation parameters has the effect of shifting sets of points left or right in Fig. 12. By using a solver routine to minimize the rms error between the actual relative spreading resistance and that suggested by Equation (55), the best values of the correlation parameters for each set are obtained. 110 Figure 49: Value of the discount factor, f, for all 1200 axisymmetric cells. The points that fall farthest from the curve are those cells with the smallest via diameters. Circles correspond to the convection boundary condition, while diamonds correspond to film contact. One method of visualizing the quality of the correlation is shown in Figure 50. Bounds are provided that delineate a variation in 𝜁 of ±15%, and the plot focused on the region near the inflection point. The set of cells with the two smallest via diameters have been excluded, and the set with the next smallest diameter 20 µm, with (𝑑/𝑃∗) ≈ 0.18, are the points lying just outside the error interval. Based on Equation (55), a relative error in 𝜁 of ±15% corresponds to an absolute error in 𝑓 of at worst ±0.035, occurring where 𝜁 = 1. This error in 𝑓 is driven to zero for very high and very low values of 𝜁. 0 0.2 0.4 0.6 0.8 1 1.2 1.E-07 1.E-05 1.E-03 1.E-01 1.E+01 1.E+03 1.E+05 ζ Boundary Discount Factor, 𝑓 Ideal fit, Eq. (16) 111 Figure 50: Detail view of data in Fig. 12, with ±15% bounds on 𝜻 plotted. Cells with (𝒅 𝑷∗⁄ ) < 0.18 are excluded. Chapter Summary In the process of “homogenizing” a thermal via array for purposes of streamlined computational modeling and simulation, care must be taken in determining the effective vertical thermal conductivity. Rather than behaving as a bulk material, the array’s thermal response includes important near-surface effects that depend both on the array parameters and the environment to which it is responding. These near-surface effects (skin effects) are manifested in the form of a micro-spreading resistance that must be included in the determination of the substrate thermal resistance and yields values that are different than predicted by a rule-of-mixtures calculation. 0 0.2 0.4 0.6 0.8 1 1.E-02 1.E-01 1.E+00 1.E+01 ζ Detail, Boundary Discount Factor, 𝑓 Ideal fit, Eq. (16) ±15% Lateral Bound 112 A framework is given for modeling this phenomenon of micro-spreading resistance. In this framework, an effort is made to decouple the intrinsic capacity of a via cell to exhibit micro-spreading, represented by 𝑅𝜇𝑠𝑝,𝑚𝑎𝑥, and the role of the array’s environment in bringing this resistance into play, captured by 𝑓𝑢 and 𝑓𝑙. This subchapter focuses its effort on the latter. Motivated by glass interposer design, where micro-spreading plays a significant role, a case study, using a copper-glass via array, is presented. While the correlations of Equations (53) and (54) remain faithful for uniform scaling of lateral cell dimensions and/or material conductivities (when 𝑅𝑠𝑝,𝑚𝑎𝑥 has also been appropriately scaled) it is acknowledged that changing the via fill factor or the cell conductivity ratio 𝑘𝑣/𝑘𝑠 requires adjustment of the fitting parameters. The FEM survey on a variety of via cell sizes and conductivities is performed to better understand how the parameters must change, and a correlation to predict their values is presented in Equations (55, (57). Even so, the framework is able to make general recommendations for designers wishing to mitigate micro-spreading resistance or create designs where its impact is lessened. High aspect ratio vias result in a lower relative contribution of micro-spreading resistance to that of the 1D resistance. Additionally, the reduction of lateral scale (i.e. smaller via pitch while holding 𝑑/𝑃 constant) increases the apparent ℎ for convection boundaries (Eq. (53), always helpful) and increases the apparent film thickness (Figure 45, helpful for high conductivity films). Beyond aspect ratio, designers should endeavor to place the highest conductivity materials and highest convective heat transfer coefficients available at the array surface. 113 This framework, when coupled with an analytic or empirical formula for 𝑅𝜇𝑠𝑝,𝑚𝑎𝑥 based on the internal cell parameters, will allow designers to estimate keff,z for a wide range of TXV systems without direct analysis with FEM. This frees the designer to optimize a TXV array for a given system based on desired thermal conductivity properties. The next Chapter provides an analytical series solution that determines 𝑅𝜇𝑠𝑝,𝑚𝑎𝑥 for axisymmetric cells. It also provides a generalized solution for 𝑅𝜇𝑠𝑝 under convection boundaries that obviates the need for the correlation Equations (55,(56). It stops short, however, of providing a general, closed-form expression for 𝑅𝜇𝑠𝑝,𝑚𝑎𝑥 as a function of cell parameters. 114 7.0 ANALYTIC MODEL OF MICROSPREADING IN VIA ARRAY UNIT CELLS This chapter is an analytic treatment of the microspreading resistance that has been investigated during the course of this program. In addition to providing a physics- based underpinning to the FEM-based correlations developed so far, the analytical model can point to useful relations for so far untreated facets of microspreading, such as the maximum (at isoflux) cell resistance or the effect of an interfacial resistance between the via and the substrate (as is seen in through-silicon vias due to their oxide liners). Isoflux Boundary for Coaxial Unit Cells The basis of the analytical model is the solution of the boundary value problem associated with a via cell experiencing an isoflux boundary condition on one exposed surface. As shown in Figure 51, the via cell is treated as an axisymmetric system containing the cylindrical via within a material having an outer diameter equal to the “equivalent pitch” of the array, such that the fill-factor of the cell matches that of the array. This outer surface is adiabatic, while the upper surface of the cell is subjected to a uniform heat flux and the lower surface fixed at a zero reference temperature. Between the isotropic via and the isotropic substrate is a finite interfacial conductance, h, that can be used to model the effects of imperfect interfaces or additional low conductivity layers between the via and the substrate. The governing differential equation of this steady state problem is Laplace’s Equation in two cylindrical dimensions, r and z. Because there are two media, the problem can be separated into two domains that are coupled along the interface at r=a. Thus the equations and boundary conditions to be solved are 115 Domain 1 Equations 1 𝑟 𝜕 𝜕𝑟 (𝑟 𝜕𝑇1 𝜕𝑟 ) + 𝜕2𝑇1 𝜕𝑧2 = 0 (58) 𝜕𝑇1 𝜕𝑧 (𝑟, 0) = − 𝑞′′ 𝑘1 (59) 𝑇1(𝑟, 𝐿) = 0 (60) 𝜕𝑇1 𝜕𝑟 (0, 𝑧) = 0 (61) 𝜕𝑇1 𝜕𝑟 (𝑎, 𝑧) = −ℎ 𝑘1 (𝑇1(𝑎, 𝑧) − 𝑇2(𝑎, 𝑧)) (62) Domain 2 Equations 1 𝑟 𝜕 𝜕𝑟 (𝑟 𝜕𝑇2 𝜕𝑟 ) + 𝜕2𝑇2 𝜕𝑧2 = 0 (63) 𝜕𝑇2 𝜕𝑧 (𝑟, 0) = − 𝑞′′ 𝑘2 (64) 𝑇2(𝑟, 𝐿) = 0 (65) 𝜕𝑇2 𝜕𝑟 (𝑏, 𝑧) = 0 (66) 𝜕𝑇2 𝜕𝑟 (𝑎, 𝑧) = ℎ 𝑘2 (𝑇2(𝑎, 𝑧) − 𝑇1(𝑎, 𝑧)) (67) Figure 51: Schematic of Boundary Value Problem 116 In order to solve Laplace’s equation using separation of variables, all but one of the boundary conditions should be homogeneous; each of these problems has two inhomogeneous conditions. To rectify this, each can be broken into a superposition of two subproblems that each satisfy only one inhomogeneous condition [55]. To further simplify the solution, the problems can be nondimensionalized, using characteristic lengths a and L and characteristic temperature 𝑄 = 𝑞𝐿/𝑘1, by transforming coordinates 𝜌 = 𝑟/𝑎 and 𝜁 = 𝑧/𝐿 and solution Θ = 𝑇/𝑄. This reduces the independent parameters of the cell from seven to four: (𝑏/𝑎), (𝐿/𝑎), 𝐾 = 𝑘1/𝑘2, and 𝐻 = ℎ𝑎/𝑘1. The characteristic temperature 𝑄 has an interpretation: it is the constant temperature at the surface 𝑧 = 0 for the case 𝑘1 = 𝑘2. For all values of 𝑘1, 𝑘2, it can be related to the Δ𝑇 between top and bottom surfaces for the isothermal boundary case that induces the same net heat flow as that created by 𝑞′′𝜋𝑏2, the constant flux condition. This temperature Δ𝑇1𝐷 is given by Δ𝑇1𝐷 = (𝑏 𝑎⁄ ) 2 𝐾 𝑄 (𝑏 𝑎⁄ ) 2 + 𝐾 − 1 (68) The separated, transformed problems to be solved are thus: Domain 1 Equations, Spreading Sub-Problem ( 𝐿 𝑎 ) 2 1 𝜌 𝜕 𝜕𝜌 (𝜌 𝜕Θ1,𝑟 𝜕𝜌 ) + 𝜕2Θ1,𝑟 𝜕𝜁2 = 0 (69) 𝜕Θ1,𝑟 𝜕𝜁 (𝜌, 0) = 0 (70) Θ1,𝑟(𝜌, 1) = 0 (71) 117 𝜕Θ1,𝑟 𝜕𝜌 (0, 𝜁) = 0 (72) 𝜕Θ1,𝑟 𝜕𝜌 (1, 𝜁) + 𝐻 Θ1,𝑟(1, 𝜁) = 𝐻 Θ2(1, 𝜁) (73) Domain 1 Equations, Coupling Sub-Problem ( 𝐿 𝑎 ) 2 1 𝜌 𝜕 𝜕𝜌 (𝜌 𝜕Θ1,𝑧 𝜕𝜌 ) + 𝜕2Θ1,𝑧 𝜕𝜁2 = 0 (74) 𝜕Θ1,𝑧 𝜕𝜁 (𝜌, 0) = −1 (75) Θ1,𝑧(𝜌, 1) = 0 (76) 𝜕Θ1,𝑧 𝜕𝜌 (0, 𝜁) = 0 (77) 𝜕Θ1,𝑧 𝜕𝜌 (1, 𝜁) + 𝐻 Θ1,𝑧(1, 𝜁) = 0 (78) Domain 2 Equations, Spreading Sub-Problem ( 𝐿 𝑎 ) 2 1 𝜌 𝜕 𝜕𝜌 (𝜌 𝜕Θ2,𝑟 𝜕𝜌 ) + 𝜕2Θ2,𝑟 𝜕𝜁2 = 0 (79) 𝜕Θ2,𝑟 𝜕𝜁 (𝜌, 0) = 0 (80) Θ2, 𝑟(𝜌, 1) = 0 (81) 𝜕Θ2,𝑟 𝜕𝜌 ( 𝑏 𝑎 , 𝜁) = 0 (82) 𝜕Θ2,𝑟 𝜕𝜌 (1, 𝜁) − 𝐾𝐻 Θ2,𝑟(1, 𝜁) = −𝐾𝐻 Θ1(1, 𝜁) (83) Domain 2 Equations, Coupling Sub-Problem ( 𝐿 𝑎 ) 2 1 𝜌 𝜕 𝜕𝜌 (𝜌 𝜕Θ2,𝑧 𝜕𝜌 ) + 𝜕2Θ2,𝑧 𝜕𝜁2 = 0 (84) 𝜕Θ2,𝑧 𝜕𝜁 (𝜌, 0) = −𝐾 (85) Θ2,𝑧(𝜌, 1) = 0 (86) 𝜕Θ2,𝑧 𝜕𝜌 ( 𝑏 𝑎 , 𝜁) = 0 (87) 𝜕Θ2,𝑧 𝜕𝜌 (1, 𝜁) − 𝐾𝐻 Θ2,𝑧(1, 𝜁) = 0 (88) 118 The subscripts in each problem refer to the material (1 for via, 2 for substrate) and to the direction normal to the boundary possessing the inhomogeneous condition. For each of the r and z subproblems, there is a physical interpretation as diagrammed in Figure 52. For the z problems, each material is unaware of the other, and heat conducts in through the upper isoflux surface, and down towards the bottom and the location of the interface. The heat leaves each material through the bottom fixed at zero, but also “convects to zero” at the location of the interface based on 𝐻 and 𝐾. In the more complicated r subproblems, the coupling between the two materials is introduced. The upper surface is now insulated, and heat is now introduced at the interface depending on the temperature in the material on the other side at the interface. This temperature, used to introduce heat from the interface, is the total temperature in the other material – that is, the superposition of that material’s subproblems. The eigenfunctions of these problems will involve trigonometric functions of the vertical dimension, 𝜁, and Bessel functions or linear combinations of Bessel functions (so-called cylinder functions) of the radial dimension, 𝜌. Individual Bessel functions 𝐽0 play a role in the cylindrical Material 1 (the via), while more general cylinder functions are needed to describe the temperature in the annular Material 2 (the substrate). 119 Figure 52: Microspreading Subproblem Decomposition 120 The solution for the dimensionless temperature field within the cell – the derivation of which is given in Appendix C – is: 𝑇1(𝜌,𝜁) 𝑄 = 𝛩1(𝜌, 𝜁) = 𝛩1,𝑟(𝜌, 𝜁) + 𝛩1,𝑧(𝜌, 𝜁) (89) = 4𝐻∑ ?̃?𝑛𝐾 2𝐹𝑛 + 𝜓0(𝜆𝑛)𝐺𝑛 ?̃?𝑛?̃?𝑛 − 𝐼0(𝜆𝑛)𝜓0(𝜆𝑛) 𝐜𝐨𝐬 ( 𝐿 𝑎 𝜆𝑛𝜻) 𝐼0(𝜆𝑛𝝆) ∞ 𝑛=1 +2𝐻 ∑ 𝑱𝟎(𝜇𝑚𝝆) [𝐻2 + 𝜇𝑚 2 ] 𝐽0(𝜇𝑚) ∞ 𝑚=1 sinh ( 𝐿 𝑎 𝜇𝑚(1 − 𝜻)) ( 𝐿 𝑎 𝜇𝑚) cosh ( 𝐿 𝑎 𝜇𝑚) 𝑇2(𝜌,𝜁) 𝑄 = 𝛩2(𝜌, 𝜁) = 𝛩2,𝑟(𝜌, 𝜁) + 𝛩2,𝑧(𝜌, 𝜁) (90) = 4𝐻∑ 𝐼0(𝜆𝑛)𝐾 2𝐹𝑛 + ?̃?𝑛𝐺𝑛 ?̃?𝑛?̃?𝑛 − 𝐼0(𝜆𝑛)𝜓0(𝜆𝑛) 𝐜𝐨𝐬 ( 𝐿 𝑎 𝜆𝑛𝜻)𝜓0(𝜆𝑛𝝆) ∞ 𝑛=1 +2𝐾2𝐻∑ 𝜙0(𝜇𝑘)𝝓𝟎(𝜇𝑘𝝆) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘2]𝜙0 2(𝜇𝑘) sinh ( 𝐿 𝑎 𝜇𝑘(1 − 𝜻)) ( 𝐿 𝑎 𝜇𝑘) cosh ( 𝐿 𝑎 𝜇𝑘) ∞ 𝑘=1 With 𝛩1 in domain 𝜌 ∈ [0,1] 𝑎𝑛𝑑 𝜁 ∈ [0,1] (91) With 𝛩2 in domain 𝜌 ∈ [1, 𝑏 𝑎⁄ ] 𝑎𝑛𝑑 𝜁 ∈ [0,1] (92) with vertical eigenvalues 𝜆𝑛 = (𝑛 − 1 2)𝜋 𝐿/𝑎 𝑓𝑜𝑟 𝑛 = 1,2,3… (93) where cylinder functions 𝜓𝜈(𝜆𝑛𝜌) = 𝐾1 (𝜆𝑛 𝑏 𝑎 ) 𝐼𝜈(𝜆𝑛𝜌) + (−1) 𝜈𝐼1 (𝜆𝑛 𝑏 𝑎 )𝐾𝜈(𝜆𝑛𝜌) 𝑓𝑜𝑟 𝜈 = 0,1 (94) 𝜙𝜈(𝜇𝑘𝜌) = 𝑌1 (𝜇𝑘 𝑏 𝑎 ) 𝐽𝜈(𝜇𝑘𝜌) − 𝐽1 (𝜇𝑘 𝑏 𝑎 ) 𝑌𝜈(𝜇𝑘𝜌) 𝑓𝑜𝑟 𝜈 = 0,1 (95) with radial eigenvalues 𝜇𝑚 𝑡ℎ𝑒 𝑚𝑡ℎ 𝑟𝑜𝑜𝑡 𝑠𝑎𝑡𝑖𝑠𝑓𝑦𝑖𝑛𝑔 𝜇 𝐽1(𝜇) − 𝐻 𝐽0(𝜇) = 0 (96) 𝜇𝑘 𝑡ℎ𝑒 𝑘𝑡ℎ 𝑟𝑜𝑜𝑡 𝑠𝑎𝑡𝑖𝑠𝑓𝑦𝑖𝑛𝑔 𝜇 𝜙1(𝜇) + 𝐾𝐻𝜙0(𝜇) = 0 (97) where interface contribution factors 𝐺𝑛 = ∑ 1 [𝐻2 + 𝜇𝑚 2 ] ∞ 𝑚=1 ∙ 1 ( 𝐿 𝑎 𝜇𝑚) 2 + [(𝑛 − 1 2)𝜋] 2 𝑓𝑜𝑟 𝑛 = 1,2,3… (98) 𝐹𝑛 =∑ 𝜙0 2(𝜇𝑘) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2(𝜇𝑘) ∞ 𝑘=1 ∙ 1 ( 𝐿 𝑎 𝜇𝑘) 2 + [(𝑛 − 1 2)𝜋] 2 (99) where convection factors ?̃?𝑛 = 1 𝐻 [𝜆𝑛𝐼1(𝜆𝑛) + 𝐻𝐼0(𝜆𝑛)] (100) ?̃?𝑛 = 1 𝐾𝐻 [−𝜆𝑛𝜓1(𝜆𝑛) + 𝐾𝐻𝜓0(𝜆𝑛)] (101) And BVP parameters 𝐿 𝑎 , 𝑏 𝑎 , 𝐻 = ℎ𝑎 𝑘1 , 𝐾 = 𝑘1 𝑘2 , 𝑄 = 𝑞′′𝐿 𝑘1 (102) 121 In Equations (89) and (90) the spatial arguments 𝜌 and 𝜁, as well as the oscillating subproblem eigenfunctions cos, 𝐽0, and 𝜙0 are bolded to highlight the structure of the solution. Paired with the eigenfunctions are non-oscillating companion functions: 𝐼0 and 𝜓0 for cos; and sinh for 𝐽0 and 𝜙0. All other terms stem from the evaluated Fourier coefficients of the series representation. In order to calculate the cell’s vertical thermal resistance – and from there the microspreading resistance – the average temperature of the upper surface must be known. In non-dimensional form, relevant average surface temperatures are: ?̅?1 𝑄 = 2𝜋 ∫ 𝜌 1 0 𝛩1(𝜌, 0)𝑑𝜌 2𝜋 ∫ 𝜌 1 0 𝑑𝜌 = 2𝜏1 (103) ?̅?2 𝑄 = 2𝜋 ∫ 𝜌 𝑏/𝑎 1 𝛩2(𝜌, 0)𝑑𝜌 𝜋 ((𝑏 𝑎⁄ ) 2 − 1) = 2 (𝑏 𝑎⁄ ) 2 − 1 𝜏2 (104) ?̅? 𝑄 = 2𝜋 [∫ 𝜌 1 0 𝛩1(𝜌, 0)𝑑𝜌 + ∫ 𝜌 𝑏/𝑎 1 𝛩2(𝜌, 0)𝑑𝜌] 𝜋(𝑏 𝑎⁄ ) 2 = 2 (𝑏 𝑎⁄ ) 2 [𝜏1 + 𝜏2] (105) where the surface temperature integrals ∫ 𝜌 1 0 𝛩1(𝜌, 0)𝑑𝜌 and ∫ 𝜌 𝑏/𝑎 1 𝛩2(𝜌, 0)𝑑𝜌 are 𝜏1 = 𝜏1,𝑟 + 𝜏1,𝑧 = 4𝐻∑ ?̃?𝑛𝐾 2𝐹𝑛 + 𝜓0(𝜆𝑛)𝐺𝑛 ?̃?𝑛?̃?𝑛 − 𝐼0(𝜆𝑛)𝜓0(𝜆𝑛) 𝐼1(𝜆𝑛) 𝜆𝑛 + ∞ 𝑛=1 2𝐻2 ∑ tanh( 𝐿 𝑎 𝜇𝑚) [𝐻2 + 𝜇𝑚2] ( 𝐿 𝑎 𝜇𝑚 3) ∞ 𝑚=1 (106) 𝜏2 = 𝜏2,𝑟 + 𝜏2,𝑧 = 4𝐻∑ 𝐼0(𝜆𝑛)𝐾 2𝐹𝑛 + ?̃?𝑛𝐺𝑛 ?̃?𝑛?̃?𝑛 − 𝐼0(𝜆𝑛)𝜓0(𝜆𝑛) −𝜓1(𝜆𝑛) 𝜆𝑛 + ∞ 𝑛=1 2𝐾3𝐻2∑ 𝜙0 2(𝜇𝑘) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘2]𝜙0 2(𝜇𝑘) tanh ( 𝐿 𝑎 𝜇𝑘) ( 𝐿 𝑎 𝜇𝑘 3) ∞ 𝑘=1 (107) 122 From these temperatures, the microspreading resistance is (in nondimensional form): 𝑅𝜇𝑠𝑝𝜋𝑘1𝑏 = ( 𝐿 𝑎 ) ( 𝑏 𝑎 ){ 2 (𝑏 𝑎⁄ ) 4 [𝜏1 + 𝜏2] − 𝐾 (𝐾 − 1) + (𝑏 𝑎⁄ ) 2} (108) These series solutions can be compared to previous results obtained by FEM simulations. In the axisymmetric cells surveyed in the preceding chapter, a perfect thermal interface between the cell materials was assumed. The maximum cell microspreading resistance was computed from cells that were subjected to an isoflux boundary condition in the FEM. By assuming a finite sequence of terms of the infinite series solution, the FEM results contained in Figure 48Figure 53 can be reproduced, as shown in Figure 53 and Figure 54. The values chosen for dimensioned parameters correspond to those used in the FE analysis of Section 6.4. The value of interface conductance ℎ chosen to be 50,000 W/m2-K, large enough compared to cell material conductivities to model a perfect interface. For the results in the figures, each summation is taken to 200 terms. As before with FE models, the emergence of microspreading resistance in the via cell is explained by the lateral (radial) patterns of conduction that occur to bring the cell flux distribution closer to a one-dimensional, rule-of-mixtures pattern. For low via- substrate conductivity mismatch, this deviation is small, leading to a low value of microspreading. Increasing the via conductivity lowers the total cell resistance, but not as much as the rule-of-mixtures would predict. The discrepancy is captured by the high microspreading resistance. 123 Additionally, that the relative via diameter at which spreading resistance is maximum depends on conductivity ratio has a heuristic answer. The “carrying capacity” of the via depends on both conductivity and material. Starting from large diameter vias, reducing diameter size serves to increase the radial distance through the substrate heat must travel to relax to one-dimensional rule of mixtures. As the via becomes very small, however, the quantity of heat that must be redistributed decreases, as the vias rule-of- mixtures carrying capacity is reduced. The breakeven point between these effects is dictated by the conductivity mismatch. In the limit as 𝑘𝑣 → 𝑘𝑠 the relative via diameter with maximum microspreading 𝑎/𝑏 → √1/2, which corresponds to a fill factor of 50%. This can be demonstrated using Equations (181) and (191) from Section 7.4, squeezing the microspreading case between a limit of two one-dimensional scenarios. Just as decreasing the size of the elements in the FE model yields results closer to the “true” value of spreading, so too does the approximation from a finite series improve as more terms are added. To achieve good agreement with the FEM simulation (e.g. within 1%) for the large values of spreading resistance (such as when 𝑘𝑣/𝑘𝑠 = 1000) only around 10 terms are needed, while for systems where spreading is very small compared to the 1D resistance (like when 𝑘𝑣/𝑘𝑠 is close to 1), hundreds of terms are needed. This is because [𝜏1 + 𝜏2] factors into the total cell resistance, and resolving the comparatively small spreading component (by subtracting the second, 1D term in Eq. 3.1) requires many more terms. 124 Figure 53: Total cell thermal resistance (in K/W) for isoflux boundary cells computed using series solution. Uses fixed cell diameter 𝟐𝒃 = 𝟐/√𝝅 ∙100µm, length 400 µm, substrate conductivity 1 W/m-K, and via-substrate interface 𝒉 = 50,000 W/m2-K Figure 54: Isoflux cell spreading resistance component (in K/W) for conditions plotted in Figure 53. 125 What is more interesting than just replicating prior FEM data is exploring the effects of finite interface conductances. Examining the case where 𝐾 = 3 (the red crosses in Figure 53), which is of the order seen in through-silicon copper via systems, low values of 𝐻 should lead to a much higher spreading resistance. This is seen to be the case in Figure 55, where the peak spreading resistance increases by as much as six-fold (for a via ratio, a/b, of ≈0.5) by adding a 1 W/m-K oxide with a thickness of 5% of the via diameter. Since the interface conductance of a TSV can be estimated from the thickness and conductivity of its oxide liner: ℎ = 𝑘𝑜𝑥/𝑡, 𝐻 can be related to the ratio of oxide thickness to via diameter, 𝜀 = 𝑡/2𝑎, by: 𝐻 = ℎ𝑎 𝑘𝑣 = 𝑘𝑜𝑥 (2𝑘𝑣𝜀) (109) Figure 55: Spreading resistance for a TSV-like system with varying interface conductance Relative Via Diameter (a/b) 0.2 0.4 0.6 0.8 2 4 6 8 10 12 Sp re ad in g R es is ta n ce [ K /W ] k v = 450, k s = 150, k ox = 1, L = 400 m, b = 112.6 m 0.2 0.4 0.6 0.8 2 4 6 8 10 12 0.2 0.4 0.6 0.8 2 4 6 8 0 12 0.2 0.4 0.6 0.8 2 4 6 8 10 12 0.2 0.4 0.6 0.8 2 4 6 8 10 12 5% 3% 0.11% 0% Relative Oxide Thickness, 𝜀 H 1/45 1/27 1 ∞ 126 Special Case: Perfect Thermal Interface As stated before, the FEM results assumed perfect thermal contact between the via and substrate. This can be approximated by choosing a large value of 𝐻 (100 is usually sufficient). Alternatively, the analytical solution can be reduced by taking the limit 𝐻 → ∞ and making the approximation exact. In this limit, the solution is: lim ℎ→∞ 𝛩1(𝜌, 𝜁) = lim ℎ→∞ 𝛩1,𝑟(𝜌, 𝜁) + lim ℎ→∞ 𝛩1,𝑧(𝜌, 𝜁) (110) =∑ 4 𝜆𝑛 𝐾𝜓0(𝜆𝑛) 𝑂𝑛 𝐾𝜓0(𝜆𝑛) 𝐼1(𝜆𝑛) − 𝐼0(𝜆𝑛)𝜓1(𝜆𝑛) 𝐜𝐨𝐬 ( 𝐿 𝑎 𝜆𝑛𝜻) 𝐼0(𝜆𝑛𝝆) ∞ 𝑛=1 + 2 ∑ 𝑱𝟎(𝜇𝑚𝝆) 𝜇𝑚𝐽1(𝜇𝑚) ∙ sinh ( 𝐿 𝑎 𝜇𝑚(1 − 𝜻)) ( 𝐿 𝑎 𝜇𝑚) cosh ( 𝐿 𝑎 𝜇𝑚) ∞ 𝑚=1 lim ℎ→∞ 𝛩2(𝜌, 𝜁) = lim ℎ→∞ 𝛩2,𝑟(𝜌, 𝜁) + lim ℎ→∞ 𝛩2,𝑧(𝜌, 𝜁) (111) =∑ 4 𝜆𝑛 𝐾𝐼0(𝜆𝑛) 𝑂𝑛 𝐾𝜓0(𝜆𝑛) 𝐼1(𝜆𝑛) − 𝐼0(𝜆𝑛)𝜓1(𝜆𝑛) 𝐜𝐨𝐬 ( 𝐿 𝑎 𝜆𝑛𝜻)𝜓0(𝜆𝑛𝝆) ∞ 𝑛=1 + 2∑ 𝜇𝑘𝜙1(𝜇𝑘)𝝓𝟎(𝜇𝑘𝝆) 𝜇𝑘2𝜙1 2(𝜇𝑘) − 4 𝜋2 ∙ sinh ( 𝐿 𝑎 𝜇𝑘(1 − 𝜻)) ( 𝐿 𝑎 𝜇𝑘) cosh ( 𝐿 𝑎 𝜇𝑘) ∞ 𝑘=1 With 𝛩1 in domain 𝜌 ∈ [0,1] 𝑎𝑛𝑑 𝜁 ∈ [0,1] (112) With 𝛩2 in domain 𝜌 ∈ [1, 𝑏 𝑎⁄ ] 𝑎𝑛𝑑 𝜁 ∈ [0,1] (113) with vertical eigenvalues 𝜆𝑛 = (𝑛 − 1 2)𝜋 𝐿/𝑎 𝑓𝑜𝑟 𝑛 = 1,2,3… (114) where cylinder functions 𝜓𝜈(𝜆𝑛𝜌) = 𝐾1 (𝜆𝑛 𝑏 𝑎 ) 𝐼𝜈(𝜆𝑛𝜌) + (−1) 𝜈𝐼1 (𝜆𝑛 𝑏 𝑎 )𝐾𝜈(𝜆𝑛𝜌) 𝑓𝑜𝑟 𝜈 = 0,1 (115) 𝜙𝜈(𝜇𝑘𝜌) = 𝑌1 (𝜇𝑘 𝑏 𝑎 ) 𝐽𝜈(𝜇𝑘𝜌) − 𝐽1 (𝜇𝑘 𝑏 𝑎 ) 𝑌𝜈(𝜇𝑘𝜌) 𝑓𝑜𝑟 𝜈 = 0,1 (116) with radial eigenvalues 𝜇𝑚 𝑡ℎ𝑒 𝑚𝑡ℎ 𝑟𝑜𝑜𝑡 𝑠𝑎𝑡𝑖𝑠𝑓𝑦𝑖𝑛𝑔 𝐽0(𝜇) = 0 (117) 𝜇𝑘 𝑡ℎ𝑒 𝑘𝑡ℎ 𝑟𝑜𝑜𝑡 𝑠𝑎𝑡𝑖𝑠𝑓𝑦𝑖𝑛𝑔 𝜙0(𝜇) = 0 (118) where interface contribution factor 𝑂𝑛 =∑ 𝜇𝑘 2𝜙1 2(𝜇𝑘) 4 𝜋2 − 𝜇𝑘2𝜙1 2(𝜇𝑘) ∞ 𝑘=1 ∙ 1 ( 𝐿 𝑎 𝜇𝑘) 2 + [(𝑛 − 1 2) 𝜋] 2 + ∑ 1 ( 𝐿 𝑎 𝜇𝑚) 2 + [(𝑛 − 1 2) 𝜋] 2 ∞ 𝑚=1 (119) And BVP parameters 𝐿 𝑎 , 𝑏 𝑎 , 𝐾 = 𝑘1 𝑘2 , 𝑄 = 𝑞′′𝐿 𝑘1 (120) 127 And for average surface temperatures: lim ℎ→∞ 𝜏1 =∑ 4 𝜆𝑛2 𝐾𝜓0(𝜆𝑛)𝐼1(𝜆𝑛) 𝑂𝑛 𝐾𝜓0(𝜆𝑛) 𝐼1(𝜆𝑛) − 𝐼0(𝜆𝑛)𝜓1(𝜆𝑛) + ∞ 𝑛=1 2 ∑ tanh ( 𝐿 𝑎 𝜇𝑚) ( 𝐿 𝑎 𝜇𝑚 3) ∞ 𝑚=1 (121) lim ℎ→∞ 𝜏2 =∑ 4 𝜆𝑛2 −𝐾𝜓1(𝜆𝑛)𝐼0(𝜆𝑛) 𝑂𝑛 𝐾𝜓0(𝜆𝑛) 𝐼1(𝜆𝑛) − 𝐼0(𝜆𝑛)𝜓1(𝜆𝑛) + ∞ 𝑛=1 2𝐾∑ 𝜇𝑘 2𝜙1 2(𝜇𝑘) 4 𝜋2 − 𝜇𝑘2𝜙1 2(𝜇𝑘) tanh ( 𝐿 𝑎 𝜇𝑘) ( 𝐿 𝑎 𝜇𝑘 3) ∞ 𝑘=1 (122) The details of obtaining this limiting case solution are provided in Appendix C. Generalization: Upper Surface Convection Boundary The solution for the isoflux condition on the cell upper surface provides an anchor point, representing an idealized case. Just as with the FEM modeling performed in section 0, that boundary condition can be generalized from a Neumann condition to a Robin condition, replacing isoflux heat transfer with convection heat transfer. A convection coefficient ℎ𝑓 approaching infinity represents an isothermal boundary, while allowing ℎ𝑓 to approach zero (with appropriate normalization of the convecting fluid temperature) recaptures the isoflux condition. As will be shown, the generalized problem solution follows along the lines of the isoflux case, but has some challenges associated with the convection boundary. Replacing the isoflux condition at 𝑧 = 0 with convection to a fluid temperature of 𝑇𝑓 yields a new boundary value problem with boundary condition at 𝑧 = 0: 𝑘𝑖 𝜕𝑇𝑖(𝑟, 0) 𝜕𝑧 = ℎ𝑓(𝑇𝑖(𝑟, 0) − 𝑇𝑓) (123) Again, using 𝐾 = 𝑘1/𝑘2, dividing by 𝐿, we rearrange each upper condition into: − 𝜕𝑇1(𝜌, 0) 𝜕𝜁 + 𝐻𝑓𝑇1(𝜌, 0) = 𝐻𝑓𝑇𝑓 (124) 128 − 𝜕𝑇2(𝜌, 0) 𝜕𝜁 + 𝐾𝐻𝑓𝑇2(𝜌, 0) = 𝐾𝐻𝑓𝑇𝑓 (125) where 𝐻𝑓 = ℎ𝑓𝐿/𝑘1 and again 𝜌 = 𝑟/𝑎 and 𝜁 = 𝑧/𝐿. Temperatures are now normalized using the fluid temperature 𝑇𝑓. Decomposing into subproblems: Domain 1 Equations, Spreading Sub-Problem ( 𝐿 𝑎 ) 2 1 𝜌 𝜕 𝜕𝜌 (𝜌 𝜕Θ1,𝑟 𝜕𝜌 ) + 𝜕2Θ1,𝑟 𝜕𝜁2 = 0 (126) − 𝜕Θ1,𝑟 𝜕𝜁 (𝜌, 0) + 𝐻𝑓Θ1,𝑟(𝜌, 0) = 0 (127) Θ1,𝑟(𝜌, 1) = 0 (128) 𝜕Θ1,𝑟 𝜕𝜌 (0, 𝜁) = 0 (129) 𝜕Θ1,𝑟 𝜕𝜌 (1, 𝜁) + 𝐻 Θ1,𝑟(1, 𝜁) = 𝐻 Θ2(1, 𝜁) (130) Domain 1 Equations, Coupling Sub-Problem ( 𝐿 𝑎 ) 2 1 𝜌 𝜕 𝜕𝜌 (𝜌 𝜕Θ1,𝑧 𝜕𝜌 ) + 𝜕2Θ1,𝑧 𝜕𝜁2 = 0 (131) − 𝜕Θ1,𝑘 𝜕𝜁 (𝜌, 0) + 𝐻𝑓Θ1,𝑘(𝜌, 0) = 𝐻𝑓 (132) Θ1,𝑧(𝜌, 1) = 0 (133) 𝜕Θ1,𝑧 𝜕𝜌 (0, 𝜁) = 0 (134) 𝜕Θ1,𝑧 𝜕𝜌 (1, 𝜁) + 𝐻 Θ1,𝑧(1, 𝜁) = 0 (135) 129 Domain 2 Equations, Spreading Sub-Problem ( 𝐿 𝑎 ) 2 1 𝜌 𝜕 𝜕𝜌 (𝜌 𝜕Θ2,𝑟 𝜕𝜌 ) + 𝜕2Θ2,𝑟 𝜕𝜁2 = 0 (136) − 𝜕Θ2,𝑟 𝜕𝜁 (𝜌, 0) + 𝐾𝐻𝑓Θ2,𝑟(𝜌, 0) = 0 (137) Θ2, 𝑟(𝜌, 1) = 0 (138) 𝜕Θ2,𝑟 𝜕𝜌 ( 𝑏 𝑎 , 𝜁) = 0 (139) 𝜕Θ2,𝑟 𝜕𝜌 (1, 𝜁) − 𝐾𝐻 Θ2,𝑟(1, 𝜁) = −𝐾𝐻 Θ1(1, 𝜁) (140) Domain 2 Equations, Coupling Sub-Problem ( 𝐿 𝑎 ) 2 1 𝜌 𝜕 𝜕𝜌 (𝜌 𝜕Θ2,𝑧 𝜕𝜌 ) + 𝜕2Θ2,𝑧 𝜕𝜁2 = 0 (141) − 𝜕Θ2,𝑘 𝜕𝜁 (𝜌, 0) + 𝐾𝐻𝑓Θ2,𝑘(𝜌, 0) = 𝐾𝐻𝑓 (142) Θ2,𝑧(𝜌, 1) = 0 (143) 𝜕Θ2,𝑧 𝜕𝜌 ( 𝑏 𝑎 , 𝜁) = 0 (144) 𝜕Θ2,𝑧 𝜕𝜌 (1, 𝜁) − 𝐾𝐻 Θ2,𝑧(1, 𝜁) = 0 (145) In formulating solutions, the radial eigenfunctions are unchanged; they remain 𝐽0 and 𝜙0, and have the same eigenvalues as for the isoflux case. The fundamental change is that cos ( 𝐿 𝑎 𝜆𝑛𝜁) is no longer the appropriate vertical eigenfunction since the slope at 𝜁 = 0 is no longer necessarily zero in the r-subproblem. It instead must be replaced with sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑛], which automatically satisfies the zero-temperature condition on the bottom surface, while allowing a new series of eigenvalues 𝜆𝑛 and 𝜆𝑙 to be chosen that satisfy the upper convection boundary. Observe that choosing 𝜆𝑛 = (𝑛 − 1 2 ) 𝜋 𝐿 𝑎 ⁄ 130 recovers the original isoflux eigenfunction. In general, however, these new eigenvalues must be obtained as roots of the transcendental equations and − 1 𝐻𝑓 ( 𝐿 𝑎 𝜆𝑛) = tan ( 𝐿 𝑎 𝜆𝑛) (146) − 1 𝐾𝐻𝑓 ( 𝐿 𝑎 𝜆𝑙) = tan ( 𝐿 𝑎 𝜆𝑙) (147) This is where the primary challenge of the generalized problem arises. In solving the coupled r-subproblem, the material temperatures along the interface are expanded into a Fourier series (see Appendix A). For the isoflux case, since the eigenvalues are the same 𝜆𝑛, the terms of these series for Material 1 and 2 correspond in a one-to-one manner, where the 𝑛𝑡ℎ term in one series only depends on the 𝑛𝑡ℎ term of the other. Relaxing the upper boundary introduces a factor of 𝐾 into Material 2’s boundary condition, breaking the one-to-one dependency. There is now a broader overlap between terms, where the 𝑛𝑡ℎ term of one series depends most strongly on the 𝑛𝑡ℎ of the other but also to a lesser degree on preceding and subsequent terms. This is captured by an overlap matrix 𝑺 with entries: 𝑆𝑛,𝑙 = sin ( 𝐿 𝑎 (𝜆𝑛 − 𝜆𝑙)) 2 𝐿 𝑎 (𝜆𝑛 − 𝜆𝑙) − sin ( 𝐿 𝑎 (𝜆𝑛 + 𝜆𝑙)) 2 𝐿 𝑎 (𝜆𝑛 + 𝜆𝑙) (148) The original isoflux behavior is recaptured when 𝜆𝑛 = 𝜆𝑙, resulting in the diagonal matrix 𝑆𝑛,𝑙 = 1 2 𝛿𝑛,𝑙. 131 The resulting temperature solution is 𝑇1(𝜌,𝜁) 𝑇𝑓 = 𝛩1(𝜌, 𝜁) = 𝛩1,𝑟(𝜌, 𝜁) + 𝛩1,𝑧(𝜌, 𝜁) (149) =∑𝐴𝑛 𝐬𝐢𝐧 [(1 − 𝜻) 𝐿 𝑎 𝜆𝑛] 𝐼0(𝜆𝑛𝝆) ∞ 𝑛=1 + 2𝐻𝐻𝑓 ∑ ∞ 𝑚=1 𝑱𝟎(𝜇𝑚𝝆) [𝐻2 + 𝜇𝑚2 ]𝐽0(𝜇𝑚) ∙ sinh [(1 − 𝜻) 𝐿 𝑎 𝜇𝑚] 𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑚) + 𝐿 𝑎 𝜇𝑚 cosh ( 𝐿 𝑎 𝜇𝑚) 𝑇2(𝜌,𝜁) 𝑇𝑓 = 𝛩2(𝜌, 𝜁) = 𝛩2,𝑟(𝜌, 𝜁) + 𝛩2,𝑧(𝜌, 𝜁) (150) =∑𝐶𝑙 𝐬𝐢𝐧 [(1 − 𝜻) 𝐿 𝑎 𝜆𝑙] 𝜓0(𝜆𝑙𝝆) ∞ 𝑙=1 + 2𝐾2𝐻𝐻𝑓∑ 𝜙0(𝜇𝑘) 𝝓𝟎(𝜇𝑘𝝆) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2(𝜇𝑘) ∙ sinh [(1 − 𝜻) 𝐿 𝑎 𝜇𝑘] 𝐾𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑘) + 𝐿 𝑎 𝜇𝑘 cosh ( 𝐿 𝑎 𝜇𝑘) ∞ 𝑘=1 With 𝛩1 in domain 𝜌 ∈ [0,1] 𝑎𝑛𝑑 𝜁 ∈ [0,1] (151) With 𝛩2 in domain 𝜌 ∈ [1, 𝑏 𝑎⁄ ] 𝑎𝑛𝑑 𝜁 ∈ [0,1] (152) where cylinder functions 𝜓𝜈(𝜆𝑛𝜌) = 𝐾1 (𝜆𝑛 𝑏 𝑎 ) 𝐼𝜈(𝜆𝑛𝜌) + (−1) 𝜈𝐼1 (𝜆𝑛 𝑏 𝑎 )𝐾𝜈(𝜆𝑛𝜌) 𝑓𝑜𝑟 𝜈 = 0,1 (153) 𝜙𝜈(𝜇𝑘𝜌) = 𝑌1 (𝜇𝑘 𝑏 𝑎 ) 𝐽𝜈(𝜇𝑘𝜌) − 𝐽1 (𝜇𝑘 𝑏 𝑎 )𝑌𝜈(𝜇𝑘𝜌) 𝑓𝑜𝑟 𝜈 = 0,1 (154) with vertical eigenvalues 𝜆𝑛 > 0 𝑡ℎ𝑒 𝑛𝑡ℎ 𝑟𝑜𝑜𝑡 𝑠𝑎𝑡𝑖𝑠𝑓𝑦𝑖𝑛𝑔 tan ( 𝐿 𝑎 𝜆) − 1 𝐻𝑓 ( 𝐿 𝑎 𝜆) = 0 (155) 𝜆𝑙 > 0 𝑡ℎ𝑒 𝑙𝑡ℎ 𝑟𝑜𝑜𝑡 𝑠𝑎𝑡𝑖𝑠𝑓𝑦𝑖𝑛𝑔 tan ( 𝐿 𝑎 𝜆) − 1 𝐾𝐻𝑓 ( 𝐿 𝑎 𝜆) = 0 (156) with radial eigenvalues 𝜇𝑚 𝑡ℎ𝑒 𝑚𝑡ℎ 𝑟𝑜𝑜𝑡 𝑠𝑎𝑡𝑖𝑠𝑓𝑦𝑖𝑛𝑔 𝜇 𝐽1(𝜇) − 𝐻 𝐽0(𝜇) = 0 (157) 𝜇𝑘 𝑡ℎ𝑒 𝑘𝑡ℎ 𝑟𝑜𝑜𝑡 𝑠𝑎𝑡𝑖𝑠𝑓𝑦𝑖𝑛𝑔 𝜇 𝜙1(𝜇) + 𝐾𝐻𝜙0(𝜇) = 0 (158) Where Fourier coeff 𝐴𝑛, 𝐶𝑙 solve the block matrix equation [ ?̃? −𝑺𝝍𝟎 −𝑺𝑇𝑰𝟎 ?̃? ] [ ?⃗⃗⃗? ?⃗⃗? ] = [ ?⃗⃗⃗? ?⃗⃗⃗? ] , 𝑤ℎ𝑒𝑟𝑒 ?⃗⃗⃗? = [ 𝐴1 𝐴2 ⋮ ] , ?⃗⃗? = [ 𝐶1 𝐶2 ⋮ ] (159) where interface contribution vector elements 𝐹𝑛 = 2𝐾 2𝐻𝐻𝑓 sin ( 𝐿 𝑎 𝜆𝑛)∑ 𝜙0 2(𝜇𝑘) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2(𝜇𝑘) ∙ 1 ( 𝐿 𝑎 𝜇𝑘) 2 + ( 𝐿 𝑎 𝜆𝑛) 2 ∞ 𝑘=1 ∙ 𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑘) + 𝐿 𝑎 𝜇𝑘 cosh ( 𝐿 𝑎 𝜇𝑘) 𝐾𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑘) + 𝐿 𝑎 𝜇𝑘 cosh ( 𝐿 𝑎 𝜇𝑘) (160) 132 𝐺𝑙 = 2𝐻𝐻𝑓 sin ( 𝐿 𝑎 𝜆𝑙) ∑ ∞ 𝑚=1 1 [𝐻2 + 𝜇𝑚 2 ] ∙ 1 ( 𝐿 𝑎 𝜇 𝑚 ) 2 + ( 𝐿 𝑎 𝜆𝑙) 2 ∙ 𝐾𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑚) + 𝐿 𝑎 𝜇𝑚 cosh ( 𝐿 𝑎 𝜇𝑚) 𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑚) + 𝐿 𝑎 𝜇𝑚 cosh ( 𝐿 𝑎 𝜇𝑚) (161) with entries of diagonal convection matrices ?̃?𝑛,𝑛 = [ 1 2 − sin(2 𝐿 𝑎⁄ 𝜆𝑛) 4 𝐿 𝑎⁄ 𝜆𝑛 ] ∙ 𝜆𝑛𝐼1(𝜆𝑛) + 𝐻𝐼0(𝜆𝑛) 𝐻 (162) ?̃?𝑙,𝑙 = [ 1 2 − sin(2 𝐿 𝑎⁄ 𝜆𝑙) 4 𝐿 𝑎⁄ 𝜆𝑙 ] ∙ −𝜆𝑙𝜓1(𝜆𝑙) + 𝐾𝐻𝜓0(𝜆𝑙) 𝐾𝐻 (163) and diagonal companion matrices 𝐼0𝑛,𝑛 = 𝐼0(𝜆𝑛) (164) 𝜓0𝑙,𝑙 = 𝜓0(𝜆𝑙) (165) and overlap matrix 𝑆𝑛,𝑙 = sin( 𝐿 𝑎 (𝜆𝑛 − 𝜆𝑙)) 2 𝐿 𝑎 (𝜆𝑛 − 𝜆𝑙) − sin ( 𝐿 𝑎 (𝜆𝑛 + 𝜆𝑙)) 2 𝐿 𝑎 (𝜆𝑛 + 𝜆𝑙) (166) And non-dim. BVP parameters 𝐿 𝑎 , 𝑏 𝑎 , 𝐻 = ℎ𝑎 𝑘1 , 𝐻𝑓 = ℎ𝑓𝐿 𝑘1 , 𝐾 = 𝑘1 𝑘2 (167) Details and further observations regarding the block matrix Equation (159) can be found in Appendix C. The analogous average surface temperature and associated integrals are also computed: ?̅?1 𝑇𝑓 = 2𝜋 ∫ 𝜌 1 0 𝛩1(𝜌, 0)𝑑𝜌 2𝜋 ∫ 𝜌 1 0 𝑑𝜌 = 2𝜏1 (168) ?̅?2 𝑇𝑓 = 2𝜋 ∫ 𝜌 𝑏/𝑎 1 𝛩2(𝜌, 0)𝑑𝜌 𝜋 ((𝑏 𝑎⁄ ) 2 − 1) = 2 (𝑏 𝑎⁄ ) 2 − 1 𝜏2 (169) ?̅? 𝑇𝑓 = 2𝜋 [∫ 𝜌 1 0 𝛩1(𝜌, 0)𝑑𝜌 + ∫ 𝜌 𝑏/𝑎 1 𝛩2(𝜌, 0)𝑑𝜌] 𝜋(𝑏 𝑎⁄ ) 2 = 2 (𝑏 𝑎⁄ ) 2 [𝜏1 + 𝜏2] (170) 133 where the surface temperature integrals 𝜏1 = ∫ 𝜌 1 0 𝛩1(𝜌, 0)𝑑𝜌 and 𝜏2 = ∫ 𝜌 𝑏/𝑎 1 𝛩2(𝜌, 0)𝑑𝜌 are 𝜏1 = 𝜏1,𝑟 + 𝜏1,𝑧 = 2𝐻2𝐻𝑓 ∑ ∞ 𝑚=1 1 𝜇𝑚 2 [𝐻2 + 𝜇𝑚 2 ] ∙ sinh ( 𝐿 𝑎 𝜇𝑚) 𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑚) + 𝐿 𝑎 𝜇𝑚 cosh ( 𝐿 𝑎 𝜇𝑚) +∑𝐴𝑛 sin ( 𝐿 𝑎 𝜆𝑛) 𝐼1(𝜆𝑛) 𝜆𝑛 ∞ 𝑛=1 (171) 𝜏2 = 𝜏2,𝑟 + 𝜏2,𝑧 = 2𝐾3𝐻2𝐻𝑓∑ 𝜙0 2(𝜇𝑘) 𝜇𝑘 2⁄ 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2(𝜇𝑘) ∙ sinh ( 𝐿 𝑎 𝜇𝑘) 𝐾𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑘) + 𝐿 𝑎 𝜇𝑘 cosh ( 𝐿 𝑎 𝜇𝑘) ∞ 𝑘=1 +∑−𝐶𝑙 sin ( 𝐿 𝑎 𝜆𝑙) 𝜓1(𝜆𝑙) 𝜆𝑙 ∞ 𝑙=1 (172) While the heat flow through the cell for the generalized boundary condition can be calculated from the upper surface temperatures using 𝑞 = 2𝜋𝑎2ℎ𝑓𝑇𝑓 [∫ 𝜌𝑑𝜌 𝑏/𝑎 0 − (𝜏1 + 𝜏2)], (173) better results at low-term series approximations are obtained by avoiding inaccuracy related to Gibb’s phenomenon (the overshoot inherent to Fourier series that model stepped functions) and measuring flux at the bottom isothermal surface using 𝑞 = − 2𝜋𝑎2𝑇𝑓 𝐿 (𝑘1𝜏1 ′ + 𝑘2𝜏2 ′ ) (174) where 𝜏1 ′ and 𝜏2 ′ are gradient lower surface integrals given by: 𝜏1 ′ = ∫ 𝜌 𝜕Θ1(𝜌, 1) 𝜕𝜁 𝑑𝜌 1 0 = 2𝐻2𝐻𝑓 ∑ ∞ 𝑚=1 1 𝜇𝑚2 [𝐻2 + 𝜇𝑚2 ] ∙ − 𝐿 𝑎 𝜇𝑚 𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑚) + 𝐿 𝑎 𝜇𝑚 cosh ( 𝐿 𝑎 𝜇𝑚) +∑−𝐴𝑛 𝐿 𝑎 𝐼1(𝜆𝑛) ∞ 𝑛=1 (175) 134 𝜏2 ′ = ∫ 𝜌 𝜕Θ2(𝜌, 1) 𝜕𝜁 𝑑𝜌 𝑏 𝑎 1 = 2𝐾3𝐻2𝐻𝑓∑ 𝜙0 2(𝜇𝑘) 𝜇𝑘 2⁄ 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2(𝜇𝑘) ∙ − 𝐿 𝑎 𝜇𝑘 𝐾𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑘) + 𝐿 𝑎 𝜇𝑘 cosh ( 𝐿 𝑎 𝜇𝑘) ∞ 𝑘=1 +∑𝐶𝑙 𝐿 𝑎 𝜓1(𝜆𝑙) ∞ 𝑙=1 (176) Using these parameters, the total cell resistance can be found as: 𝑅𝑇𝜋𝑏𝑘1 = −(𝐿 𝑎⁄ ) (𝑏 𝑎⁄ ) 𝐾(𝜏1 + 𝜏2) 𝐾𝜏1 ′ + 𝜏2 ′ (177) Discussion of Analytic Solutions The motivation for pursuing an analytic model of microspreading resistance is to obtain – if not a closed form expression for microspreading – at least a foundational understanding of how microspreading arises and of the interplay between via cell parameters. One challenge is that for the series solutions presented in this Chapter, an important effect of the cell parameters is to play a key role in determining the system’s eigenvalues, scaling them up or down according to relative conductivity, via aspect ratio, etc. This makes their impact difficult to visualize from inspection of the mathematical expressions. This section will present simply obtainable, one-dimensional (closed form) limiting cases, and compare them to several examples of full, two-dimensional solutions obtained through the series solutions. These limiting cases will be presented first, as they provide an excellent way of visualizing the space of possible cell thermal resistances. As has been discussed throughout Chapter 0, the minimum cell vertical thermal resistance is that predicted by rule of mixtures, which arises from one-dimensional conduction resulting from 135 isothermal boundaries. In the context of this Chapter’s non-dimensional nomenclature, the effective conductivity given by the rule of mixtures is 𝑘𝑒𝑓𝑓,1𝐷 = 𝑘𝑠(𝐾𝜙 + (1 − 𝜙)) (178) where 𝜙 = (𝑎/𝑏)2 is the fill factor of the via (not related to any cylinder function from the series solution) and 𝐾 = 𝑘𝑣/𝑘𝑠. The total cell resistance of this rule-of-mixtures cell is straightforward to compute from either this effective conductivity 𝑅𝑇 = 𝐿 𝑘𝑒𝑓𝑓,1𝐷𝐴 (179) or from the sum of the parallel resistances of the via and substrate separately: 𝑅𝑇 = [( 𝐿 𝜙𝑘𝑣𝐴 ) −1 + ( 𝐿 (1 − 𝜙)𝑘𝑠𝐴 ) −1 ] −1 (180) where 𝐴 is the entire cell cross-sectional area and 𝐿 the length of the cell. One impediment to visualizing the parameter space occupied by cells with isothermal boundaries is infinite interval the input parameters can take – for example 𝑘𝑣/𝑘𝑠 can take values from 1 to infinity for systems of high-k vias in low-k substrates 8. One way to remedy this is to present the space along reciprocal coordinates – for example 𝜙 instead of (𝑏/𝑎). Using 1/𝐾 = 𝑘𝑠/𝑘𝑣 as a reciprocal coordinate similarly restricts the conductivity parameter range to an interval between 0 and 1. Multiplying either equation (179) or (180) by 𝑘𝑠𝐴/𝐿 brings the equation into a non-dimensional form that can be plotted along these reciprocal coordinates in a bounded volume of dimensions [0,1]3, as the surface defined by the equation 8 The series solution never makes this a requirement, and is equally apt at describing systems where 𝑘𝑣/𝑘𝑠 ∈ (0,1], with high conductivity substrates and low conductivity vias. 136 𝑅𝑇 𝑘𝑠𝐴 𝐿 = 𝑘𝑠 𝑘𝑒𝑓𝑓,1𝐷 = 1 1 − 𝜙 + 𝜙 1/𝐾 (181) A plot of this surface is shown in Figure 56. Because under one-dimensional conduction there is no heat transfer between the via and the surrounding substrate, 𝜙 and 1/𝐾 are all that is required to parameterize the via cell. In fact, this relation (and the other one-dimensional ones that follow) holds for vias and cells with arbitrary cross sectional shapes, so long as those cross sections are constant along the length of the cell. It is heat transfer across the via-substrate interface, giving rise to higher-dimensional patterns of conduction, which requires consideration of the cross section geometry. For the surface in Figure 56, one a point is selected using 𝜙 and 1/𝐾, further specifying 𝑘𝑠, 𝐴, and 𝐿 specifies a physical, dimensional via cell and fixes its thermal resistance. 137 Figure 56: Bounding surface formed by isothermal boundary condition via cells Exploring the surface presented in Figure 56 results in intuitive conclusions. Setting 𝜙 = 0 and/or 1/𝐾 = 𝑘𝑠/𝑘𝑣 = 1 is equivalent to considering a cell composed of only one material with conductivity 𝑘𝑠. It is straightforward to see that 𝑅𝑇 must then equal 𝐿/𝑘𝑠𝐴. If instead 1/𝐾 is set to 0, this implies a via within the cell with conductivity 𝑘𝑣 → ∞. In that case, under the two isothermal boundary conditions the cell conducts an infinite amount of heat, requiring 𝑅𝑇 = 0. A pointwise discontinuity exists at (𝜙, 1/𝐾) = (0,0) where this super-conducting via has disappeared. Finally, allowing 𝜙 = 1 specifies a cell comprised entirely of via material, and Equation (181) simplifies to 𝑅𝑇 𝑘𝑠𝐴 𝐿 = 1 𝐾 = 𝑘𝑠 𝑘𝑣 (182) demonstrating that under such conditions 𝑅𝑇 must equal 𝐿/𝑘𝑣𝐴. 138 As discussed, these isothermal boundaries establish the minimum vertical cell resistance. To examine the maximum9 possible resistance, an isoflux boundary is considered. In the series solution, there is a particular limit that creates one-dimensional conduction (for any uniform boundary): namely, when the interface conductance between via and substrate is zero. This prevents any communication between the two materials. In that case, for an isoflux boundary at the cell surface, a simple analysis can produce a closed-form expression. From the definitions of vertical resistance, 𝑅𝑇 = (𝐴𝑣Δ𝑇𝑣 + 𝐴𝑠Δ𝑇𝑠)/𝐴 𝐴𝑣𝑞′′ + 𝐴𝑠𝑞′′ (183) where Δ𝑇𝑣 is the temperature difference along the length of the via with cross- sectional area 𝐴𝑣 and likewise for Δ𝑇𝑠 and 𝐴𝑠 for the substrate, with 𝐴𝑣 + 𝐴𝑠 = 𝐴. Recognizing that 𝐴𝑣/𝐴 = 𝜙 and 𝐴𝑠/𝐴 = (1 − 𝜙) and factoring out the group 1/𝐴𝑞′′ results in 𝑅𝑇 = 1 𝐴𝑞′′ [𝜙Δ𝑇𝑣 + (1 − 𝜙)Δ𝑇𝑠] (184) Since the individual temperature response of each material is dictated by their individual thermal resistance, the temperature rise can be substituted for using Δ𝑇𝑣 = 𝑞 ′′𝐴𝑣𝑅𝑣 = 𝑞′′𝐿 𝑘𝑣 (185) Δ𝑇𝑠 = 𝑞 ′′𝐴𝑠𝑅𝑠 = 𝑞′′𝐿 𝑘𝑠 (186) Manipulating: 9 Even larger cell resistances can be obtained by applying non-uniform boundary conditions, specifically those that force higher heat flux into the low conductivity material than that entering the high conductivity one. Out of the three types of uniform (constant) boundary conditions, isoflux (Neumann) leads to the highest resistance. 139 𝑅𝑇 = 𝐿 𝐴 [ 𝜙 𝑘𝑣 + (1 − 𝜙) 𝑘𝑠 ] (187) meaning for isoflux boundary cells with zero interface conducatance, 𝑘𝑒𝑓𝑓 = [ 𝜙 𝑘𝑣 + (1 − 𝜙) 𝑘𝑠 ] −1 (188) For more than two materials within the cell, this generalizes to a weighted harmonic mean with weights summing to 1: ∑ 𝜙𝑖 𝑛 𝑖=1 𝑘𝑒𝑓𝑓 = 1 𝑘𝑒𝑓𝑓 =∑ 𝜙𝑖 𝑘𝑖 𝑛 𝑖=1 (189) An equivalent statement is that the areal resistance of the entire cell is a weighted (by cross-sectional area) average of the individual areal resistances, with weights summing to 1: 𝐴𝑅𝑇 = 𝜙1𝐴1𝑅1 + 𝜙2𝐴2𝑅2… (190) One interpretation, shown in Figure 57, can aid in visualizing this summation rule. It recognizes that the conserved “current” through each of the independent flux tubes formed by the different materials is the constant flux each is carrying. Thus these areal resistances form a series, but to be added properly the relative area ratio 𝜙𝑖 must be applied to each term to properly place the flux tube in relation to the entire cell area. Figure 57: Areal resistance summation rule for isoflux cells with independent flux tubes 140 Proceeding from Equation (187), in non-dimensional form the cell resistance under an isoflux boundary is 𝑅𝑇 𝑘𝑠𝐴 𝐿 = 1 − 𝜙 + 𝜙 1 𝐾 (191) Plotted in Figure 58 is the surface defined by Equation (191) using the same reciprocal coordinates from Figure 56. This function collapses to the same limits at 𝜙 = 0 or 1 and 1/𝐾 = 1 as isothermal boundary case, and for the same reasons. However, for infinite conductivity vias (1/𝐾 = 0), rather than zero 𝑅𝑇 for any size via, the cell thermal resistance is directly proportional to (1 − 𝜙). This follows from the implementation of the rule in Figure 57, where the via resistance 𝑅1 and temperature drop Δ𝑇1 are set to zero. The only term in the summation is thus 𝜙2𝐴2𝑅2, and since 𝜙2 = (1 − 𝜙) and 𝐴2𝑅2 = 𝐿/𝑘𝑠, the relation follows. 141 Figure 58: Bounding surface formed by via cells with isoflux upper surface boundaries and zero interfacial conductance These two surfaces form the bounds between which fall all two-material via cell vertical resistances. Accessing the interior of this volume in parametric space occurs in one of two ways, only one of which maintains the one-dimensional conduction pattern and thus closed-form relation. This first method is to relax the isoflux condition at the upper surface to one described by a convection boundary with conductance ℎ to a fluid of temperature 𝑇𝑓. The other system that reaches intermediate cell resistances is that which relaxes the adiabatic interface between the two materials, generating higher dimensional conduction such as that considered by the series solution. 142 For the former, one-dimensional case, from the definition of cell resistance (and dropping the deltas by observing that without loss of generality the bottom surface temperature can be taken as zero): 𝑅𝑇 = (𝐴𝑣𝑇𝑣 + 𝐴𝑠𝑇𝑠)/𝐴 𝐴𝑣ℎ(𝑇𝑓 − 𝑇𝑣) + 𝐴𝑠ℎ(𝑇𝑓 − 𝑇𝑠) (192) The same definition can be used to define a resistance across the convection boundary, from the fluid to the cell: 𝑅𝑐𝑜𝑛𝑣 = [𝐴𝑣(𝑇𝑓 − 𝑇𝑣) + 𝐴𝑠(𝑇𝑓 − 𝑇𝑠)]/𝐴 𝐴𝑣ℎ(𝑇𝑓 − 𝑇𝑣) + 𝐴𝑠ℎ(𝑇𝑓 − 𝑇𝑠) = 1 ℎ𝐴 (193) where from inspection 1 ℎ𝐴 + 𝑅𝑇 = 𝑇𝑓 𝐴𝑣ℎ(𝑇𝑓 − 𝑇𝑣) + 𝐴𝑠ℎ(𝑇𝑓 − 𝑇𝑠) (194) Since each material forms an independent flux tube, this total resistance of convection-plus-cell must equal the parallel sum of each material’s convection-plus-bulk resistance: [ 1 ℎ𝐴 + 𝑅𝑇] −1 = [ 1 ℎ𝐴𝑣 + 𝐿 𝑘𝑣𝐴𝑣 ] −1 + [ 1 ℎ𝐴𝑠 + 𝐿 𝑘𝑠𝐴𝑠 ] −1 (195) Solving for 𝑅𝑇 and isolating 1/𝑘𝑒𝑓𝑓 in brackets: 𝑅𝑇 = 𝐿 𝐴{ 1 ℎ𝐿 ( 𝜙 1 + 𝑘𝑣 ℎ𝐿⁄ + 1 − 𝜙 1 + 𝑘𝑠 ℎ𝐿⁄ ) − 1 ℎ𝐿} (196) Finally, recognizing ℎ𝐿/𝑘𝑠 as a new dimensionless parameter 𝐻 𝑅𝑇 𝑘𝑠𝐴 𝐿 = 1 𝐾 (𝜙 + 𝐻) + (1 − 𝜙) 1 + 𝜙𝐻 + 1 𝐾𝐻(1 − 𝜙) (197) 143 with the underbar to emphasize that this parameter is not the same as the 𝐻 used in the series solution. In the terms of the nomenclature used for the series solution, 𝐻 = 𝐻𝑓/𝐾 (and so is in a sense reciprocal along the same lines as 𝜙 and 1/𝐾). That Equation (197) appropriately links the isothermal and isoflux boundary cases is evident from the fact that it reduces to Eqs. (181) and (191) when taking the limits 𝐻 → ∞ and 𝐻 → 0, respectively. Varying 𝐻 between these limits sweeps out the volume bounded by Eqs. (181) and (191) as shown in Figure 59. It is important to realize, however, that within this interior there is now an implicit dependence on 𝑘𝑠 and 𝐿 through 𝐻. While it makes sense that to compare systems and maintain equivalent patterns of heat transfer requires that the ratio of ℎ to 𝑘𝑠/𝐿 remain constant, the dependence on 𝐿 in particular poses a conceptual wrinkle when considering the second avenue for accessing the parametric space between the two bounding surfaces: microspreading. 144 Figure 59: Representation of cell resistance parameter space using zero-interface conductance cells. Adjusting parameter 𝑯 from 0 to infinity sweeps the middle surface from the upper isoflux bounding surface to the lower isothermal one. In this example, 𝑯 = 𝟒. All of the discussion in this Section has been based on the stipulation that there is no exchange of heat between the two materials in the cell – a feature that occurs trivially due the parallel isotherms in the isothermal boundary case, and is explicitly required by the zero-conductance interface for the convection and isoflux boundaries cases that result in Eqs. (191) and (197). By relaxing this interface to one with finite conductance or perfect thermal contact, microspreading at the upper surface is allowed to occur. But, as discussed in Chapter 0, microspreading can be thought of as a skin effect that reaches a steady value after the cell has reached a sufficient length. Thus, total cell response with microspreading is also sensitive to cell length, but as a result of the conduction patterns 145 within the cell and not just the relative size of a surface convection resistance to that of the bulk. As an illustration, Figure 60 plots the three sets of series solution results from Figure 53 against the parametric bounding surfaces described by Eqs. (181) and (191). Those cells have 𝑘𝑠 = 1 W/m-K, 2𝑏 = 2/√𝜋 ∙100 µm (~112 µm to correspond with Chapter 6.4), 𝐿 = 400 µm, and via-substrate interface ℎ = 50,000 W/m2-K. Also plotted are cone-shaped markers that designate each point’s intercept with the lower bounding surface, with vertical lines connecting the corresponding point. To demonstrate the dependence of cell length, a fourth series is plotted that replicates the cell with a 400 W/m-K via, but at a cell length of only 100 µm. These are plotted with dashed lines linking them to their bounding surface intercepts (the same intercepts as the full length cell). An enlarged version of the figure is available as Figure 70 in Appendix A. Figure 60: Series solution results plotted against isothermal and isoflux parametric bounding surfaces. Three series plotted are those from Figure 53, with an 146 additional series representing a shortened unit cell with 𝑳 = 𝟏𝟎𝟎𝝁𝒎, 𝒌𝒗 = 𝟒𝟎𝟎 W/m-K, and other parameters maintained at values from Figure 53. The comparison of 100 µm and 400 µm cells in Figure 60 illustrates the relative magnitude of the 𝑅𝜇𝑠𝑝 component to the bulk resistance. Extending the cell length drives the total cell resistance to that of its rule-of-mixtures value since that bulk resistance will dominate. Conversely, by reducing the cell length from 400 µm to 100 µm, the depth of the microspreading skin effect is now on the same order as the cell length. This can be seen in an examination of the points indicated by the black arrows in Figure 60. Shown in each of Figure 61 and Figure 62 is the temperature rise within the cell due only to microspreading resistance, 𝑇𝑠𝑝, plotted as a function of relative position within the cell, 𝜌 = 𝑟/𝑏 and 𝜁 = 𝑧/𝐿. These are obtained by subtracting the one- dimensional rule-of-mixtures temperature rise from the total rise (or equivalently, Figure 41 from Figure 40), such that no net heat flow crosses the upper or lower surface. That the skin depth of microspreading is thinner than the length of the 400 µm cell can be seen by the 𝑇𝑠𝑝 field (and its gradient) decaying to zero at the former isothermal lower surface at 𝜁 = 1. In contrast, while in the short cell 𝑇𝑠𝑝 at 𝜁 = 1 is also zero (as demanded by superposition), in the vicinity of that lower surface there is a significant temperature change due to microspreading. 147 Figure 61: Temperature field in isoflux boundary via cell due only to microspreading resistance for a cell 400 µm long. The former isoflux surface is at 𝜻 = 𝟎, and the central cell axis at 𝝆 = 𝟎. 𝒌𝒗 = 𝟒𝟎𝟎 W/m-K, 𝒌𝒔 = 𝟏 W/m-K, 𝒒 ′′ = 50 W/cm2. The via-substrate interface is located at 𝝆 = 𝟐𝒃 𝟐𝒂 = 𝑷∗ 𝒅 = 𝟏𝟏𝟐.𝟖𝝁𝒎 𝟐𝟎𝝁𝒎 = 𝟎. 𝟏𝟕𝟕. Figure 62: Temperature field in isoflux boundary via cell due only to microspreading resistance for a cell 100 µm long. Other parameters maintained as described in Figure 61. 148 Concluding this chapter is a final comment on the interpretation of microspreading suggested by Figure 61 and Figure 62. Microspreading can be thought of as a “circulation” of heat flux from the substrate to the via that is superimposed on the simpler, rule-of-mixtures conduction pattern. Since under microspreading the via is underutilized for much of its length, the microspreading temperature component in the via is negative. The associated heat flux vectors in the via flow back towards the upper surface, partially canceling the rule-of-mixtures flux pattern (Figure 41) to produce the required isoflux (or more general) boundary. 149 8.0 FUTURE WORK AND RECOMMENDATIONS This study demonstrates the basic feasibility of using via-enhanced low-k interposers in place of highly conductive substrates such as silicon or SiC. However, several issues exist with currently manufacturable interposers that limit the range of HI applications where they would provide a compelling benefit. The foremost of these is the low vertical effective conductivity of the array. This limits the effectiveness of heat transfer through the intended path – through the thickness of the interposer. This low conductivity primarily stems from the fact that the available metal fill- factor of the via arrays is limited by design rules on permissible via pitch:diameter ratios, where fabrication below a 2:1 ratio is avoided. This limits metal fill factor to (nominally) 22.6% of the interposer volume. Because fill factor varies with the square of 𝑑𝑣/𝑃, even modest reductions in via spacing would achieve much higher conductivities. Another avenue for improvement is in higher conductivity via fill materials. The thermal expansion-matched Cu frit used in this study has a nominal conductivity of 300 W/m-K. Increasing the fill conductivity will have a proportionate effect on the interposer’s effective conductivity. A promising category of fill materials is silver-diamond pastes. However at the time of this work the minimum size diamond particle in typical studies is on the order of 50 µm – much too large for satisfactory filling of thermal vias. The choice to focus on via-enhanced low-k interposers as an isolation strategy stems from two factors. The first is that the technology needed to fabricate these thermal via arrays is relatively mature. The costs of the developing the further manufacturing advancements described above (to bring enhanced interposers to a requisite level of performance) must be weighed against the costs of exploring and developing alternative 150 thermal isolation technologies. It is entirely likely, however, that these alternative strategies would be usable in conjunction and not simply in lieu of enhanced interposers, providing justification for additional investigation on both fronts. The second reason via-enhanced interposers are attractive is that the interposer itself could be leveraged as an active part of the heterogeneously integrated circuit. The vias within the array could be used to carry signals into and out of the hosted devices with minimal disruption of current fabrication and packaging processes. In this sense enhanced interposers are easily integrated compared to alternative isolation approaches. In order to take this step however, new electrical-thermal co-design techniques would need to be developed to properly leverage this multi-functional interposer. There is also further work to be done developing the concept of microspreading resistance. A critical step is isolating the effect of microspreading experimentally. One method of doing this would be to place a via array sample between layers of material with high or low conductivity within an ASTM D5470 Standard thermal conductivity test [56, 57]. By maintaining the same materials within the thermal stack and only varying their order, different levels of microspreading can be induced without changing the bulk, one-dimensional resistance of the stack. Further work on microspreading would entail a simple to use numerical tool using the analytical solution obtained in Chapter 0. Published online and/or accessible via an application programming interface (API), designers would be able to integrate a microspreading calculator into their workflow. To be useful in systems that do not rely on embedded fluid cooling, the analytic solutions will need to be extended to systems with material layers in contact with the via cell surfaces, as in Chapter 6.3. As a final 151 extension, effective properties beyond thermal conductivity – such as thermal diffusivity – will enable transient thermal behavior to be captured during via array homogenization. As systems with high conductivity contrast ordered arrays become more prevalent, fast yet accurate material models will become key to the thermal/electrical co-design of HI and other emerging packaging technologies. 152 9.0 SUMMARY AND CONTRIBUTIONS In investigating HI systems where steps could be taken to thermally isolate disparate components, 2.5D chiplet based approaches were determined to be the most amenable HI configuration. By implementing a via-enhanced glass interposer in place of traditional silicon interposers, an anisotropic substrate for the placement of HI devices can be obtained. This anisotropy laterally isolates adjacent devices from each other at the cost of increasing the total thermal resistance faced by high heat dissipating components. For systems limited by the operating temperature of low-power, sensitive devices rather than that of the high-power, heterogeneous devices, this trade-off is beneficial. When there exist strict constraints on the temperature rise of sensitive components – such as in applications where inlet coolant temperature is much higher than ambient – thermal isolation can permit much smaller HI device spacing, even as the high dissipation device temperatures are allowed to rise. Thermal isolation also allows the implementation of a differential cooling strategy, where a high-intensity embedded cooler is applied in the regions of high dissipation and a low intensity cooling solution is used in the remaining interposer regions. This can lead to a reduction in the required pressure drop, flowrate, and pumping power of the thermal management system. In actual microgap embedded cooling testing of via-enhanced glass interposers, a crossover point was successfully demonstrated: at 1.37 mm upstream from the chip edge the enhanced glass interposer exhibited lower surface temperatures than silicon for the conditions tested. This distance is still relatively long compared to the most ambitious HI interconnect lengths, but with advances in through-glass via array technology the distance could be reduced. This would also increase the thermal coupling coefficient at the 153 crossover point, which in the experiments was 0.24±.013 K/W of heater power. Increasing this breakeven coupling coefficient would broaden the range of HI component types that would benefit from via-enhanced low-k interposers. Further increases in via fill-factor, higher conductivity fills, and maintaining control of microspreading resistances are the key avenues to achieving this progress. Specific contributions as a result of this study include:  Modeling o Identification of microspreading resistance skin effect phenomenon in thermal via arrays o Analysis and correlation of boundary condition influence on microspreading resistance o Analytical model of conjugate heat transfer within dual-medium coaxial via unit cells o System-level framework for assessing tradeoffs between effective medium substrates in 2.5D HI applications  Experimental o In collaboration with contracted vendors, fabricated frit filled thermal via arrays in semiconductor grade glass wafer o Demonstrated integrability with microfluidic cooling using single-phase microgap o Performed first example of direct liquid cooling of thermal via arrays in glass interposers o Demonstrated a break-even keep-out-zone radius of 1.37 mm in an enhanced glass interposer when compared to silicon for the conditions tested 154 APPENDIX A – SUPPLEMENTAL CASE STUDY MODELS During the creation of the heterogeneous integration thermal case study, an array of FE models were investigated to explore different system configurations. All figures depict systems with the dimensions detailed in Figure 3, with 200 µm interposers. An initial exploration was whether a bond of an entire silicon wafer with both CMOS devices and on-wafer fabricated GaN HEMTs could have isolation issued addressed with a via-enhanced interposer. This system on chip (SoC) demonstrated that the silicon wafer, even when thinned to 100 µm, provided such an effective lateral thermal pathway that the thermal coupling between HEMT and CMOS was unable to be addressed by the low-k via enhanced interposer. Figure 63: SoC with uniform cooling and no vias Figure 64: SoC with uniform cooling and copper via array 155 Figure 65: SoC with differential cooling and copper via array Next followed a simple parametric study on systems with discrete device chiplets hosted on a low-k interposer – a so-called system in package (SiP). 200 µm glass interposers were equipped with a copper via array, enhanced 30,000 W/m2-K cooling in the HEMT footprint, neither, or both. The models indicated that both the copper vias and high underside local convection were required to maintain temperatures within workable ranges. Finally, Table 13 summarizes relevant temperature rise for the SiP systems in Figures Figure 66 through Figure 69 as well as for a final parametric dimension, reduced interposer thickness to 100 µm. Unusual behavior in the maximum observed amplifier temperature is in retrospect attributed to effects of microspreading resistance in the conical vias of the array. The low 3,000 W/m2-K ℎ used for the uniform cooling boundary coupled with a small, 30 µm conical via lower diameter had a particularly curious impact, leading to a higher amplifier temperature when thinning the interposer. 156 Figure 66: SiP with no vias and uniform cooling Figure 67: SiP with copper vias and uniform cooling Figure 68: SiP with no vias and differenti al cooling Figure 69: SiP with copper vias and differenti al cooling 157 Table 13: Chiplet Temperature Rise for 200 µm and 100 µm Interposers Without Vias With Vias Interposer Thickness Max ∆Tamp [K] Avg ∆Tcmos [K] Max ∆Tamp [K] Avg ∆Tcmos [K] Uniform Cooling 200µm 771 16.5 522 14.9 Differential cooling 200µm 411 8.5 113 5.1 Uniform Cooling 100µm 678 6.5 564 6.2 Differential cooling 100µm 250 3.5 110 3.0 158 APPENDIX B – MICROCOOLER DESIGN DRAWING 159 APPENDIX C – DERIVATION OF ANALYTICAL SERIES SOLUTION The Solutions 𝜣𝟏,𝒓(𝝆, 𝜻) and 𝜣𝟐,𝒓(𝝆, 𝜻) Each of these problems can be easily solved with separation of variables. For problems 𝛩𝑖,𝑟, recognize that the solutions oscillate in 𝜁, leading to eigenfunctions cos ( 𝐿 𝑎 𝜆𝑛𝜁). Then for the solution 𝛩1,𝑟, (since the temperature is finite at the origin): 𝛩1,𝑟(𝜌, 𝜁) =∑ 𝐴𝑛 ∞ 𝑛=1 cos( 𝐿 𝑎 𝜆𝑛𝜁) 𝐼0(𝜆𝑛𝜌) 𝑤𝑖𝑡ℎ 𝜆𝑛 = [𝑛 − 1 2]𝜋 𝐿 𝑎⁄ , 𝑛 = 1,2,3… (198) 𝑢𝑠𝑖𝑛𝑔 𝑐𝑜𝑛𝑑𝑖𝑡𝑖𝑜𝑛𝑠 𝑎𝑡 𝑡ℎ𝑒 𝑖𝑛𝑡𝑒𝑟𝑓𝑎𝑐𝑒: 𝐴𝑛 = 2𝐻 ∫ cos 1 0 ( 𝐿 𝑎 𝜆𝑛𝜁)𝛩2 (1, 𝜁)𝑑𝜁 𝜆𝑛𝐼1(𝜆𝑛) + 𝐻𝐼0(𝜆𝑛) (199) where 𝐼0 and 𝐼1 are modified Bessel’s functions of the first kind of index 0 and 1, respectively. The eigenfunctions (in 𝜁) for 𝛩2,𝑟 are identical, but the dependence on 𝜌 is now a linear combination of modified Bessel’s functions of the first and second kind: 𝑏𝑛𝐼0(𝜆𝑛𝜌)+ 𝑑𝑛𝐾0(𝜆𝑛𝜌). A choice that satisfies the adiabatic boundary condition at 𝜌 = 𝑏 𝑎⁄ is any constant multiple of the modified cylinder function: 𝜓0(𝜆𝑛𝜌) = 𝐾1 (𝜆𝑛 𝑏 𝑎 ) 𝐼0(𝜆𝑛𝜌)+ 𝐼1 (𝜆𝑛 𝑏 𝑎 )𝐾0(𝜆𝑛𝜌) (200) where the indices with the under-bar are fixed (and are not related to the index of 𝜓). Aside: A cylinder function is any non-trivial linear combination of the Bessel’s functions 𝐽𝜈(𝑧), 𝑌𝜈(𝑧), 𝐻𝜈 (1)(𝑧), and 𝐻𝜈 (2)(𝑧). Analogously, a modified cylinder function is any non-trivial linear combination of 𝐼𝜈(𝑧) and 𝑒 𝜈𝜋𝑖𝐾𝜈(𝑧). Such functions obey many of 160 the key recurrence relations belonging to the underlying Bessel’s functions. See DLMF10 §§ 10.2(ii), 10.25(ii), 10.6, and 10.29. Here we make a small abuse, in that the coefficients in the linear combination should not depend on 𝜈 or 𝑧, but the understanding is that for each 𝑛, within each 𝜓0(𝜆𝑛𝜌) the parameter 𝜆𝑛 is a fixed constant. Thus the solution, 𝛩2,𝑟, is given by: 𝛩2,𝑟(𝜌, 𝜁) =∑ 𝐶𝑛 ∞ 𝑛=1 cos( 𝐿 𝑎 𝜆𝑛𝜁)𝜓0(𝜆𝑛𝜌) 𝑤𝑖𝑡ℎ 𝜆𝑛 = [𝑛− 1 2]𝜋 𝐿 𝑎⁄ , 𝑛 = 1,2,3… (201) Using conditions at the interface: 𝐶𝑛 = −2𝐾𝐻∫ cos 1 0 ( 𝐿 𝑎𝜆𝑛𝜁)𝛩1(1, 𝜁)𝑑𝜁 𝜆𝑛𝜓1(𝜆𝑛)−𝐾𝐻𝜓0(𝜆𝑛) (202) where 𝜓1(𝜆𝑛𝜌) = 𝐾1 ( 𝜆𝑛 𝑏 𝑎 ) 𝐼1(𝜆𝑛𝜌)− 𝐼1 ( 𝜆𝑛 𝑏 𝑎 )𝐾1(𝜆𝑛𝜌) (203) In both of these solutions, the coefficients 𝐴𝑛 and 𝐶𝑛 contain information relating to the coupling of the two subdomains at the interface. Further evaluation of these coefficients will require the solutions to 𝛩1,𝑧 and 𝛩2,𝑧. The Solution 𝜣𝟏,𝒛(𝝆, 𝜻) With two homogeneous boundaries in the radial direction, the solutions 𝛩1,𝑧 and 𝛩2,𝑧 will oscillate in 𝜌. Due to the convection boundary, the radial component of each solution will be a Dini series, introducing new eigenvalues, 𝜇𝑚 and 𝜇𝑘, stemming from 𝛩1,𝑧 and 𝛩2,𝑧 respectively 11,12. Because the temperature is bounded at 𝜌 = 0, the radial eigenfunction for 𝛩1,𝑧 is 𝐽0(𝜇𝑚𝜌). Each eigenvalue 𝜇𝑚 is the 𝑚th root of 𝑧 𝐽1(𝑧) − 𝐻 𝐽0(𝑧) = 0. Such 10 http://dlmf.nist.gov/10 11 Carslaw, H.S., Jaeger, J.C. Conduction of Heat in Solids. Oxford University Press, §7.5, 1959. 12 Bowman, F.Introduction to Bessel Functions. New York: Dover, p.109, 1958. 161 eigenvalues are the only values that satisfy the convection condition at 𝜌 = 1. Continuing, the dependence on 𝜁 is then sinh ( 𝐿 𝑎 𝜇𝑚(1 − 𝜁)). The solution for 𝛩1,𝑧 is: 𝛩1,𝑧(𝜌, 𝜁) = ∑ 𝐵𝑚 ∞ 𝑚=1 𝐽0(𝜇𝑚𝜌) sinh( 𝐿 𝑎 𝜇𝑚(1 − 𝜁)) (204) 𝑤𝑖𝑡ℎ 𝜇𝑚 𝑡ℎ𝑒 𝑟𝑜𝑜𝑡𝑠 𝑜𝑓 𝑧 𝐽1(𝑧) − 𝐻 𝐽0(𝑧) = 0 (205) The coefficients 𝐵𝑚 are used to satisfy the non-homogeneous boundary at the upper surface. Fortunately, this boundary is that of a uniform flux, which after the normalization requires: 1 𝑄 𝜕𝑇1,𝑧 𝜕𝜁 (𝜌, 0) = 𝜕𝛩1,𝑧 𝜕𝜁 (𝜌, 0) = ∑ 𝐵𝑚 ∞ 𝑚=1 𝐽0(𝜇𝑚𝜌) (− 𝐿 𝑎 𝜇 𝑚 ) cosh( 𝐿 𝑎 𝜇𝑚) = −1 (206) Aside: The Dini expansion of any function satisfying 𝑓′(1)+𝐻 𝑓(1) = 0 in radial coordinates is 𝑓(𝜌)~ ∑ 𝑏𝑚 𝐽0(𝜇𝑚𝜌) ∞ 𝑚=1 , with coeff 𝑏𝑚 = 2𝜇𝑚 2 [𝐻2+𝜇𝑚 2 ] 𝐽0(𝜇𝑚)2 ∫ 𝜌 𝐽0(𝜇𝑚𝜌)𝑓(𝜌)𝑑𝜌 1 0 (207) 𝑎𝑠 𝑎 𝑟𝑒𝑠𝑢𝑙𝑡 𝑜𝑓 ∫ 𝜌 𝐽0(𝜇𝑚𝜌)𝐽0(𝜇𝑛𝜌)𝑑𝜌 1 0 = { [𝐻2+𝜇𝑚 2 ] 𝐽0(𝜇𝑚) 2 2𝜇𝑚 2 𝑓𝑜𝑟 𝑛 = 𝑚 0 𝑓𝑜𝑟 𝑛 ≠ 𝑚 𝜇𝑖 𝑓𝑟𝑜𝑚 (205) (208) So due to the uniform condition at the upper surface (and since ∫ 𝜌 𝐽0(𝜇𝜌)𝑑𝜌 1 0 = 𝐽1(𝜇)/𝜇 ∀𝜇 ), 𝐵𝑚 = 2𝜇𝑚 2 [𝐻2 + 𝜇𝑚 2 ] 𝐽0(𝜇𝑚) 2 𝐽1(𝜇𝑚) 𝜇𝑚 1 ( 𝐿 𝑎𝜇𝑚 ) cosh( 𝐿 𝑎𝜇𝑚) = 2𝐻 [𝐻2 + 𝜇𝑚 2 ] 𝐽0(𝜇𝑚) 1 ( 𝐿 𝑎𝜇𝑚 ) cosh( 𝐿 𝑎𝜇𝑚) (209) because from equation (205), 𝐽1(𝜇𝑚) 𝐽0(𝜇𝑚) = 𝐻 𝜇𝑚 . 162 Thus, the full solution for 𝛩1,𝑧(𝜌, 𝜁), with coefficients made explicit, is 𝛩1,𝑧(𝜌, 𝜁) = 2𝐻∑ 𝐽0(𝜇𝑚𝜌) [𝐻2 + 𝜇𝑚 2 ] 𝐽0(𝜇𝑚) ∞ 𝑚=1 sinh ( 𝐿 𝑎𝜇𝑚(1 − 𝜁)) ( 𝐿 𝑎𝜇𝑚 ) cosh ( 𝐿 𝑎𝜇𝑚) (210) The solution 𝜣𝟐,𝒛(𝝆, 𝜻) The approach to solving for 𝛩2,𝑧(𝜌, 𝜁) borrows from concepts used in both the 2, 𝑟 and 1, 𝑧 subproblems. A cylinder function will be defined that is a linear combination of 𝐽0 and 𝑌0 to serve as the radial eigenfunction. Then the solution will be based on a Dini expansion in terms of this cylinder function instead of solely 𝐽0. The domain of material two has an annular cross section ranging from 1 ≤ 𝜌 ≤ 𝑏/𝑎. The adiabatic condition at the outer radius 𝑏/𝑎 suggests the eigenfunction of the form: 𝜙0(𝜇𝜌) = 𝑌1 (𝜇 𝑏 𝑎 ) 𝐽0(𝜇𝜌)− 𝐽1 (𝜇 𝑏 𝑎 )𝑌0(𝜇𝜌) (211) satisfyin g 𝜕𝜙0(𝜇𝜌) 𝜕𝜌 | 𝑝=𝑏/𝑎 = −𝜇𝜙1 (𝜇 𝑏 𝑎 ) = 𝜇 [−𝑌1 (𝜇 𝑏 𝑎 ) 𝐽1 (𝜇 𝑏 𝑎 )+ 𝐽1 (𝜇 𝑏 𝑎 )𝑌1 (𝜇 𝑏 𝑎 )] = 0 (212) This function can be used as the basis for a Dini expansion by restricting values of 𝜇 when 𝜌 = 1 to the roots of 𝑧𝜙0 ′ (𝑧) − 𝐾𝐻𝜙0(𝑧) = 0 (213) or explicitly −𝑌1 (𝑧 𝑏 𝑎⁄ ) [𝑧 𝐽1(𝑧)+𝐾𝐻 𝐽0(𝑧)]+ 𝐽1 (𝑧 𝑏 𝑎⁄ ) [𝑧 𝑌1(𝑧)+𝐾𝐻 𝑌0(𝑧)] = 0 (214) since the coefficients 𝑌1 and 𝐽1 are varying. Upon obtaining the 𝑘 = 1,2,3… roots, we can fix the coefficients and define the cylinder function: 𝜙0(𝜇𝑘𝜌) = 𝑌1 (𝜇𝑘 𝑏 𝑎 ) 𝐽0(𝜇𝑘𝜌)− 𝐽1 (𝜇𝑘 𝑏 𝑎 )𝑌0(𝜇𝑘𝜌) (215) 𝑤𝑖𝑡ℎ 𝜇𝑘 𝑒𝑎𝑐ℎ 𝑠𝑎𝑡𝑖𝑠𝑓𝑦𝑖𝑛𝑔 𝜇𝑘𝜙1(𝜇𝑘) + 𝐾𝐻𝜙0(𝜇𝑘) = 0 (216) Useful characteristics of this function are: 163 [ 𝑑𝜙0(𝜇𝑘𝜌) 𝑑𝜌 ] 𝜌=1 = −𝜇𝑘𝜙1(𝜇𝑘) = 𝐾𝐻𝜙0(𝜇𝑘) (217) [ 𝑑𝜙0(𝜇𝑘𝜌) 𝑑𝜌 ] 𝜌=𝑏/𝑎 = −𝜇𝑘𝜙1 (𝜇𝑘 𝑏 𝑎 ) = 0 (218) 𝜙0 (𝜇𝑘 𝑏 𝑎 ) = −𝒲{𝐽0(𝑧), 𝑌0(𝑧)}|𝑧=𝜇𝑏𝑎 = − [𝐽1 (𝜇𝑘 𝑏 𝑎 )𝑌0 (𝜇𝑘 𝑏 𝑎 )−𝑌1 (𝜇𝑘 𝑏 𝑎 ) 𝐽0 (𝜇𝑘 𝑏 𝑎 )] = − 2 𝜋𝜇𝑘 𝑏 𝑎 (219) with Equation (217) and (218) by construction at the boundaries, and (219) a result of DLMF §10.5. The solution 𝛩2,𝑧 follows, with unknown coefficients: 𝛩2,𝑧(𝜌, 𝜁) = ∑ 𝐷𝑘 ∞ 𝑘=1 𝜙0(𝜇𝑘𝜌) sinh( 𝐿 𝑎 𝜇𝑘(1 − 𝜁)) (220) Evaluating the coefficients 𝐷𝑘 will proceed as in the solution of problem 1, 𝑧. Required will be the evaluation of the integrals ∫ 𝜌 𝜙0(𝜇𝑘𝜌)𝑑𝜌 𝑏/𝑎 1 and ∫ 𝜌 𝜙0(𝜇𝑘𝜌)𝜙0(𝜇𝑙𝜌)𝑑𝜌 𝑏/𝑎 1 . For the former, ∫ 𝜌 𝜙0(𝜇𝑘𝜌)𝑑𝜌 𝑏/𝑎 1 = 1 𝜇𝑘 2 ∫ (𝜇𝑘𝜌)𝜙0(𝜇𝑘𝜌)𝑑(𝜇𝑘𝜌) 𝜇𝑘𝑏/𝑎 𝜇𝑘 = 1 𝜇𝑘 2 ∫ 𝑧 𝜙0(𝑧)𝑑𝑧 𝜇𝑘𝑏/𝑎 𝜇𝑘 (221) 𝐹𝑜𝑟 𝑎𝑛𝑦 𝑐𝑦𝑙𝑖𝑛𝑑𝑒𝑟 𝑓𝑢𝑛𝑐𝑡𝑖𝑜𝑛 ℭν(𝑧), 𝑧ℭν ′ (𝑧) + 𝜈ℭν(𝑧) = 𝑧ℭν−1(𝑧) (222) thus [𝑧 𝜙1(𝑧)] ′ = 𝑧 𝜙1 ′ (𝑧)+𝜙 1 (𝑧) = 𝑧 𝜙0(𝑧) (223) and [𝑧 𝜙1(𝑧)]|𝜇𝑘 𝜇𝑘𝑏/𝑎 = ∫ 𝑧 𝜙0(𝑧)𝑑𝑧 𝜇𝑘𝑏/𝑎 𝜇𝑘 (224) so ∫ 𝜌 𝜙0(𝜇𝑘𝜌)𝑑𝜌 𝑏/𝑎 1 = 1 𝜇𝑘 2 [𝑧 𝜙1(𝑧)]|𝜇𝑘 𝜇𝑘𝑏/𝑎 = 𝑏/𝑎 𝜇𝑘 𝜙1 (𝜇𝑘 𝑏 𝑎 )− 1 𝜇𝑘 𝜙1(𝜇𝑘) (225) but 𝜙1 (𝜇𝑘 𝑏 𝑎 ) = 0 𝑓𝑟𝑜𝑚 (218) 𝑎𝑛𝑑 −𝜇𝑘𝜙1(𝜇𝑘) = 𝜇𝑘𝜙0 ′ (𝜇𝑘) = 𝐾𝐻 𝜙0(𝜇𝑘) 𝑓𝑟𝑜𝑚 (216) (226) Thus ∫ 𝜌 𝜙0(𝜇𝑘𝜌)𝑑𝜌 𝑏/𝑎 1 = 𝐾𝐻 𝜇𝑘 2𝜙0(𝜇𝑘) (227) 164 For ∫ 𝜌 𝜙0(𝜇𝑘𝜌)𝜙0(𝜇𝑙𝜌)𝑑𝜌 𝑏/𝑎 1 , because Bessel’s equation is a regular Sturm- Liouville eigenvalue problem, Green’s formula provide straightforward results. For two eigenfunctions 𝑢 and 𝑣 with eigenvalues 𝜇𝑘 and 𝜇𝑙: (𝜇𝑘 2 − 𝜇𝑙 2)∫ 𝜌𝑢𝑣 𝑏/𝑎 1 = ∫ [𝑣 𝑑 𝑑𝜌 (𝜌 𝑑𝑢 𝑑𝜌 )− 𝑢 𝑑 𝑑𝜌 (𝑟 𝑑𝑣 𝑑𝜌 )]𝑑𝜌 𝑏/𝑎 1 = 𝜌 [𝑣 𝑑𝑢 𝑑𝜌 − 𝑢 𝑑𝑣 𝑑𝜌 ] 1 𝑏/𝑎 The right hand side vanishes for eigenfunctions that satisfy the homogeneous boundary conditions if they have different eigenvalues, as 𝜙0(𝜇𝑘𝜌) and 𝜙0(𝜇𝑙𝜌) do. They are thus orthogonal with weight 𝜌. Following the approach in Carslaw and Jaeger §7.5 𝑠𝑖𝑛𝑐𝑒 𝜙0 𝑠𝑜𝑙𝑣𝑒𝑠 𝐵𝑒𝑠𝑠𝑒𝑙 ′𝑠 𝑒𝑞𝑢𝑎𝑡𝑖𝑜𝑛: 1 𝜌 𝑑 𝑑𝜌 (𝜌 𝑑𝜙0 𝑑𝜌 ) + 𝜇𝑘 2𝜙0 = 0 2𝜌 𝑑𝜙0 𝑑𝜌 𝑑 𝑑𝜌 (𝜌 𝑑𝜙0 𝑑𝜌 ) + 2𝜇𝑘 2𝜌2𝜙0 𝑑𝜙0 𝑑𝜌 = 0 𝑑 𝑑𝜌 (𝜌 𝑑𝜙0 𝑑𝜌 ) 2 + 𝜇𝑘 2𝜌2 𝑑𝜙0 2 𝑑𝜌 = 0 𝐼𝑛𝑡𝑒𝑔𝑟𝑎𝑡𝑖𝑛𝑔… [(𝜌 𝑑𝜙0 𝑑𝜌 ) 2 ] 1 𝑏 𝑎⁄ + 𝜇𝑘 2∫ 𝜌2 𝑑𝜙0 2 𝑑𝜌 𝑑𝜌 𝑏 𝑎⁄ 1 = 0 𝑠𝑒𝑐𝑜𝑛𝑑 𝑡𝑒𝑟𝑚 𝑏𝑦 𝑝𝑎𝑟𝑡𝑠: 𝜇𝑘 2∫ 𝜌2 𝑑𝜙0 2 𝑑𝜌 𝑑𝜌 𝑏 𝑎⁄ 1 = −2𝜇𝑘 2∫ 𝜌𝜙0 2𝑑𝜌 𝑏/𝑎 1 + [𝜇𝑘 2𝜌2𝜙0 2] 1 𝑏/𝑎 𝑠𝑜 𝑡𝑜𝑔𝑒𝑡ℎ𝑒𝑟, 2𝜇𝑘 2∫ 𝜌𝜙0 2𝑑𝜌 𝑏/𝑎 1 = [𝜌2 ( 𝑑𝜙0 𝑑𝜌 ) 2 + 𝜇𝑘 2𝜌2𝜙0 2] 1 𝑏 𝑎⁄ 𝑢𝑠𝑖𝑛𝑔 (216), [𝜌2 ( 𝑑𝜙0 𝑑𝜌 ) 2 + 𝜇𝑘 2𝜌2𝜙0 2] 1 𝑏 𝑎⁄ = 𝜇𝑘 2 ( 𝑏 𝑎 ) 2 𝜙0 (𝜇𝑘 𝑏 𝑎 ) 2 − (𝐾𝐻)2𝜙0(𝜇𝑘) 2 − 𝜇𝑘 2𝜙0(𝜇𝑘) 2 𝑎𝑛𝑑 (219) 𝑟𝑒𝑑𝑢𝑐𝑒𝑠 𝑡ℎ𝑒 𝑓𝑖𝑟𝑠𝑡 𝑡𝑒𝑟𝑚: 𝜇𝑘 2 ( 𝑏 𝑎 ) 2 𝜙0 (𝜇𝑘 𝑏 𝑎 ) 2 = 4 𝜋2 so finally, 165 ∫ 𝜌𝜙0(𝜇𝑘𝜌) 2 𝑑𝜌 𝑏/𝑎 1 = 4 𝜋2 − [𝜇𝑘 2 + (𝐾𝐻)2]𝜙0(𝜇𝑘) 2 2𝜇𝑘 2 (228) Now the Fourier coefficients 𝐷𝑘 can be evaluated: 𝜕 𝜕𝜁 (𝛩2,𝑧(𝜌, 𝜁)) = ∑ 𝐷𝑘 ∞ 𝑘=1 𝜙0(𝜇𝑘𝜌) (− 𝐿 𝑎 𝜇𝑘) cosh( 𝐿 𝑎 𝜇𝑘) = −𝐾 𝐷𝑘 (− 𝐿 𝑎 𝜇𝑘) cosh( 𝐿 𝑎 𝜇𝑘)∫ 𝜌𝜙0(𝜇𝑘𝜌) 2 𝑑𝜌 𝑏/𝑎 1 = −𝐾∫ 𝜌𝜙0(𝜇𝑘)𝑑𝜌 𝑏/𝑎 1 𝐷𝑘 = 2𝐾2𝐻 𝜙0(𝜇𝑘) 4 𝜋2 − [𝜇𝑘 2 + (𝐾𝐻)2]𝜙0(𝜇𝑘) 2 1 ( 𝐿 𝑎𝜇𝑘) cosh ( 𝐿 𝑎𝜇𝑘) (229) Thus, the solution 𝛩2,𝑧(𝜌, 𝜁) is given by: 𝛩2,𝑧(𝜌, 𝜁) = 2𝐾2𝐻∑ 𝜙0(𝜇𝑘)𝜙0(𝜇𝑘𝜌) 4 𝜋2 − [𝜇𝑘 2 + (𝐾𝐻)2]𝜙0 2 (𝜇𝑘) sinh ( 𝐿 𝑎𝜇𝑘(1 − 𝜁)) ( 𝐿 𝑎𝜇𝑘) cosh ( 𝐿 𝑎𝜇𝑘) ∞ 𝑘=1 (230) 𝑤𝑖𝑡ℎ 𝜇𝑘 𝑒𝑎𝑐ℎ 𝑠𝑎𝑡𝑖𝑠𝑓𝑦𝑖𝑛𝑔 𝜇𝑘𝜙1(𝜇𝑘) + 𝐾𝐻𝜙0(𝜇𝑘) = 0 (216) 166 The coupling coefficients 𝑨𝒏 and 𝑪𝒏 The total temperature rise in each medium, 𝛩1 and 𝛩2, each contain two components. In the last two sections, the independent components of each solution were obtained. These solutions (which may have application beyond this BVP), when combined with the coupling components, allow for the simultaneous determination of the coefficients 𝐴𝑛 and 𝐶𝑛. This process is carried out at the interface of the two media, at 𝜌 = 1. Recall that each 𝐴𝑛 is a constant multiple of ∫ cos 1 0 ( 𝐿 𝑎 𝜆𝑛𝜁)𝛩2(1, 𝜁)𝑑𝜁, and so also 𝐶𝑛 of ∫ cos 1 0 ( 𝐿 𝑎 𝜆𝑛𝜁)𝛩1(1, 𝜁)𝑑𝜁. Thus we look for a Fourier-cosine expansion of those components in each solution that depend on 𝜁. Conveniently, the 𝛩𝑖,𝑟 (the coupled sub- solutions) already form a Fourier-cosine series. Thus the next step is to determine the 𝛩𝑖,𝑧 overlap: ∫ cos [(𝑛 − 1 2 )𝜋𝜁] sinh ( 𝐿 𝑎𝜇𝑖(1 − 𝜁)) ( 𝐿 𝑎𝜇𝑖) cosh ( 𝐿 𝑎𝜇𝑖) 𝑑𝜁 1 0 = 1 ( 𝐿 𝑎𝜇𝑖) 2 + [(𝑛 − 1 2)𝜋] 2 obtained by integrating by parts twice. So evaluating at 𝜌 = 1: ∫ cos 1 0 ( 𝐿 𝑎 𝜆𝑛𝜁)𝛩1(1, 𝜁)𝑑𝜁 = ∫ cos 1 0 ( 𝐿 𝑎 𝜆𝑛𝜁) [∑𝐴𝑛 ∞ 𝑙=1 cos ( 𝐿 𝑎 𝜆𝑙𝜁) 𝐼0(𝜆𝑙𝜌) + 2𝐻 ∑ 𝐽0(𝜇𝑚) [𝐻2 + 𝜇𝑚 2 ] 𝐽0(𝜇𝑚) ∞ 𝑚=1 sinh ( 𝐿 𝑎 𝜇𝑚(1 − 𝜁)) ( 𝐿 𝑎 𝜇𝑚) cosh ( 𝐿 𝑎 𝜇𝑚) ] 𝑑𝜁 so ∫ cos 1 0 ( 𝐿 𝑎 𝜆𝑛𝜁)𝛩1(1, 𝜁)𝑑𝜁 = 1 2 𝐴𝑛𝐼0(𝜆𝑛)+ 2𝐻∑ 1 [𝐻2 + 𝜇𝑚 2 ] ∞ 𝑚=1 1 ( 𝐿 𝑎𝜇𝑚) 2 + [(𝑛 − 1 2)𝜋] 2 by passing the integral under the summations and evaluating term-by-term. 167 Both ∑ 1 [𝐻2 + 𝜇𝑚 2 ] ∞ 𝑚=1 1 ( 𝐿 𝑎𝜇𝑚) 2 + [(𝑛 − 1 2)𝜋] 2 = 𝐺𝑛 (231) and the analogous expression within ∫ cos 1 0 ( 𝐿 𝑎 𝜆𝑛𝜁)𝛩2,𝑧(1, 𝜁)𝑑𝜁 ∑ 𝜙0 2 (𝜇𝑘) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2 (𝜇𝑘) ∞ 𝑘=1 1 ( 𝐿 𝑎𝜇𝑘) 2 + [(𝑛 − 1 2)𝜋] 2 = 𝐹𝑛 (232) we call contribution factors. They represent the contribution of the uncoupled temperature field at the interface in one medium to each 𝑛th coupling coefficient of the other medium (𝐶𝑛 or 𝐴𝑛, respectively), and are related to the Fourier expansion coefficients of the subproblem interface temperature: 𝛩1,𝑧(1, 𝜁) = ∑𝑔𝑛𝑢𝑛 = ∞ 𝑛=1 ∑2𝐻𝐺𝑛 cos ( 𝐿 𝑎 𝜆𝑛𝜁) ∞ 𝑛=1 𝛩2,𝑧(1, 𝜁) = ∑𝑓𝑛𝑢𝑛 = ∞ 𝑛=1 ∑2𝐾2𝐻𝐹𝑛 cos ( 𝐿 𝑎 𝜆𝑛𝜁) ∞ 𝑛=1 Thus each 𝐴𝑛 = 2𝐻 ∫ cos 1 0 ( 𝐿 𝑎𝜆𝑛𝜁)𝛩2(1, 𝜁)𝑑𝜁 𝜆𝑛𝐼1(𝜆𝑛)+𝐻𝐼0(𝜆𝑛) can be put in terms of the corresponding 𝐶𝑛 and 𝐹𝑛: 𝐴𝑛 = 2𝐻 𝜆𝑛𝐼1(𝜆𝑛)+𝐻𝐼0(𝜆𝑛) [ 1 2 𝐶𝑛𝜓0(𝜆𝑛)+ 2𝐾 2𝐻𝐹𝑛] (233) Likewise, each 𝐶𝑛 in terms of 𝐴𝑛 and 𝐺𝑛: 𝐶𝑛 = 2𝐾𝐻 −𝜆𝑛𝜓1(𝜆𝑛)+𝐾𝐻𝜓0(𝜆𝑛) [ 1 2 𝐴𝑛𝐼0(𝜆𝑛)+ 2𝐻𝐺𝑛] (234) Defining the factors ?̃?𝑛 = [𝜆𝑛𝐼1(𝜆𝑛)+𝐻𝐼0(𝜆𝑛)]/𝐻 and ?̃?𝑛 = [−𝜆𝑛𝜓1(𝜆𝑛)+𝐾𝐻𝜓0(𝜆𝑛)]/(𝐾𝐻) and distributing the factor of 2, 168 𝐴𝑛 = 1 ?̃?𝑛 [𝐶𝑛𝜓0(𝜆𝑛)+ 4𝐾 2𝐻𝐹𝑛] 𝑎𝑛𝑑 𝐶𝑛 = 1 ?̃?𝑛 [𝐴𝑛𝐼0(𝜆𝑛)+ 4𝐻𝐺𝑛] (235) Lastly, solving this system, [ ?̃?𝑛𝐴𝑛 − 𝐶𝑛𝜓0(𝜆𝑛) ?̃?𝑛𝐶𝑛−𝐴𝑛𝐼0(𝜆𝑛) ] = 4𝐻 [𝐾 2𝐹𝑛 𝐺𝑛 ] [ ?̃?𝑛 −𝜓0(𝜆𝑛) −𝐼0(𝜆𝑛) ?̃?𝑛 ] [ 𝐴𝑛 𝐶𝑛 ] = 4𝐻 [𝐾 2𝐹𝑛 𝐺𝑛 ] [ 𝐴𝑛 𝐶𝑛 ] = 4𝐻 ?̃?𝑛?̃?𝑛 − 𝐼0(𝜆𝑛)𝜓0(𝜆𝑛) [ ?̃?𝑛 𝜓0(𝜆𝑛) 𝐼0(𝜆𝑛) ?̃?𝑛 ] [𝐾 2𝐹𝑛 𝐺𝑛 ] (236) results in the final determination of the coupling coefficients. Limiting Case: 𝒉 → ∞ A particularly common case of interest is one in which the two media in the cell are in perfect thermal contact. That is to say, the interfacial resistance between them is zero and hence the interfacial conductance must be taken to infinity. Firstly, in this limit the radial eigenvalues are now the roots of the eigenfunctions of order zero: As ℎ → ∞, 𝜇𝑚 𝑖𝑠 𝑡ℎ𝑒 𝑚𝑡ℎ 𝑟𝑜𝑜𝑡 𝑜𝑓 𝐽0(𝜇) (237) 𝜇𝑘 𝑖𝑠 𝑡ℎ𝑒 𝑘𝑡ℎ 𝑟𝑜𝑜𝑡 𝑜𝑓 𝜙0(𝜇) (238) With some algebra, the solutions for the temperature field can be brought to a form amenable to taking the limit ℎ → ∞. First, the solutions with the vertical eigenfunctions: 𝛩1,𝑟(𝜌, 𝜁) = 4∑ −𝜆𝑛𝜓1(𝜆𝑛) 𝐾𝐻 (𝐾𝐻)2𝐹𝑛 + 𝜓0(𝜆𝑛)[(𝐾𝐻) 2𝐹𝑛 + 𝐻 2𝐺𝑛] −𝜆𝑛 2𝜓 1 (𝜆𝑛)𝐼1(𝜆𝑛) 𝐾𝐻 + 𝜓 0 (𝜆𝑛)𝜆𝑛 𝐼1 (𝜆𝑛) − 𝐼0(𝜆𝑛) 𝜆𝑛 𝐾 𝜓 1 (𝜆𝑛) cos ( 𝐿 𝑎 𝜆𝑛𝜁) 𝐼0(𝜆𝑛𝜌) ∞ 𝑛=1 169 𝛩2,𝑟(𝜌, 𝜁) = 4∑ −𝜆𝑛𝐼1(𝜆𝑛) 𝐻 𝐻2𝐺𝑛 + 𝐼0(𝜆𝑛)[(𝐾𝐻) 2𝐹𝑛 + 𝐻 2𝐺𝑛] −𝜆𝑛 2𝜓 1 (𝜆𝑛)𝐼1(𝜆𝑛) 𝐾𝐻 + 𝜓 0 (𝜆𝑛)𝜆𝑛 𝐼1 (𝜆𝑛) − 𝐼0(𝜆𝑛) 𝜆𝑛 𝐾 𝜓 1 (𝜆𝑛) cos ( 𝐿 𝑎 𝜆𝑛𝜁)𝜓0(𝜆𝑛𝜌) ∞ 𝑛=1 accomplished by substituting the definitions of ?̃?𝑛 and ?̃?𝑛, distributing the leading 𝐻 and multiplying by an additional 𝐻/𝐻. The terms 𝐻2𝐺𝑛 and (𝐾𝐻) 2𝐹𝑛 approach constants as ℎ → ∞. 𝐻2𝐺𝑛, done in a straightforward manner (passing the limit under both the 𝑛 and 𝑚 summations): lim ℎ→∞ 𝐻2𝐺𝑛 = ∑ lim ℎ→∞ [ 𝐻2 𝐻2 + 𝜇𝑚 2 ] 1 ( 𝐿 𝑎𝜇𝑚) 2 + [(𝑛 − 1 2)𝜋] 2 ∞ 𝑚=1 = ∑ 1 ( 𝐿 𝑎𝜇𝑚) 2 + [(𝑛− 1 2)𝜋] 2 ∞ 𝑚=1 (239) The limit of (𝐾𝐻)2𝐹𝑛 is slightly more involved, since the constant 𝜙0 2 (𝜇𝑘) goes to zero as ℎ → ∞. Again, passing the limit under the 𝑛 and 𝑘 summations: lim ℎ→∞ (𝐾𝐻)2𝐹 𝑛 = ∑ lim ℎ→∞ [ (𝐾𝐻)2𝜙0 2 (𝜇𝑘) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2 (𝜇𝑘) ] ∞ 𝑘=1 ∙ 1 ( 𝐿 𝑎𝜇𝑘) 2 + [(𝑛− 1 2)𝜋] 2 (240) Fortunately, 𝐾𝐻𝜙0(𝜇𝑘) = −𝜇𝑘 𝜙1(𝜇𝑘) for all 𝐻, so this substitution can be made prior to evaluating the limit. lim ℎ→∞ [ (𝐾𝐻)2𝜙0 2 (𝜇𝑘) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2 (𝜇𝑘) ] = lim ℎ→∞ [ 𝜇𝑘 2𝜙1 2 (𝜇𝑘) 4 𝜋2 − 𝜇𝑘 2𝜙1 2 (𝜇𝑘)+ 𝜇𝑘 2𝜙0 2 (𝜇𝑘) ] Upon evaluating, the third term in the denominator goes to zero, and lim ℎ→∞ (𝐾𝐻)2𝐹 𝑛 =∑ 𝜇𝑘 2𝜙1 2 (𝜇𝑘) 4 𝜋2 − 𝜇𝑘 2𝜙1 2 (𝜇𝑘) ∞ 𝑘=1 ∙ 1 ( 𝐿 𝑎𝜇𝑘) 2 + [(𝑛 − 1 2)𝜋] 2 (241) 170 Thus, in the recast solutions of 𝛩1,𝑟 and 𝛩2,𝑟, the first term in both the numerator and denominator go to zero as ℎ → ∞, while all other terms either are or tend to constants with respect to 𝐻. Defining the in-the-limit contribution factor 𝑂𝑛 = lim ℎ→∞ [(𝐾𝐻)2𝐹𝑛 + 𝐻2𝐺𝑛]: lim ℎ→∞ 𝛩1,𝑟(𝜌, 𝜁) =∑ 4 𝜆𝑛 𝐾𝜓 0 (𝜆𝑛) 𝑂𝑛 𝐾𝜓 0 (𝜆𝑛) 𝐼1 (𝜆𝑛) − 𝐼0(𝜆𝑛)𝜓1(𝜆𝑛) cos ( 𝐿 𝑎 𝜆𝑛𝜁) 𝐼0(𝜆𝑛𝜌) ∞ 𝑛=1 (242) lim ℎ→∞ 𝛩2,𝑟(𝜌, 𝜁) =∑ 4 𝜆𝑛 𝐾𝐼0(𝜆𝑛) 𝑂𝑛 𝐾𝜓 0 (𝜆𝑛) 𝐼1 (𝜆𝑛) − 𝐼0(𝜆𝑛)𝜓1(𝜆𝑛) cos ( 𝐿 𝑎 𝜆𝑛𝜁)𝜓0(𝜆𝑛𝜌) ∞ 𝑛=1 (243) where 𝑂𝑛 =∑ 𝜇𝑘 2𝜙1 2 (𝜇𝑘) 4 𝜋2 − 𝜇𝑘 2𝜙1 2 (𝜇𝑘) ∞ 𝑘=1 ∙ 1 ( 𝐿 𝑎𝜇𝑘) 2 + [(𝑛− 1 2)𝜋] 2 + ∑ 1 ( 𝐿 𝑎𝜇𝑚) 2 + [(𝑛− 1 2)𝜋] 2 ∞ 𝑚=1 ( (244) The limits of solution components with radial eigenfunctions are easier to evaluate, although the same process applies. Distributing the 𝐻 and multiplying by 𝐻/𝐻, we obtain: 𝛩1,𝑧(𝜌, 𝜁) = 2∑ 𝐻2𝐽0(𝜇𝑚𝜌) [𝐻2 + 𝜇𝑚 2 ] 𝐻𝐽0(𝜇𝑚) ∞ 𝑚=1 sinh ( 𝐿 𝑎 𝜇 𝑚 (1 − 𝜁)) ( 𝐿 𝑎 𝜇 𝑚 ) cosh ( 𝐿 𝑎 𝜇 𝑚 ) Similarly, distributing 𝐾2𝐻 and then multiplying by an additional 𝐾2𝐻/𝐾2𝐻: 𝛩2,𝑧(𝜌, 𝜁) = 2∑ (𝐾𝐻)2[𝐾𝐻𝜙 0 (𝜇𝑘)]𝜙0(𝜇𝑘𝜌) 4(𝐾𝐻)2 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2][(𝐾𝐻)2𝜙 0 2 (𝜇𝑘)] sinh ( 𝐿 𝑎 𝜇 𝑘 (1 − 𝜁)) ( 𝐿 𝑎 𝜇 𝑘 ) cosh ( 𝐿 𝑎 𝜇 𝑘 ) ∞ 𝑘=1 Recognizing that 𝐻𝐽0(𝜇𝑚) = 𝜇𝑚𝐽1(𝜇𝑚) and 𝐾𝐻𝜙0(𝜇𝑘) = −𝜇𝑘𝜙1(𝜇𝑘) for all 𝐻, and passing the limit under the 𝑚 and 𝑘 summations, respectively, we obtain: 171 lim ℎ→∞ 𝛩1,𝑧(𝜌, 𝜁) = 2∑ lim ℎ→∞ [ 𝐻2 𝐻2 + 𝜇 𝑚 2 ] ∞ 𝑚=1 𝐽0(𝜇𝑚𝜌) 𝜇𝑚𝐽1(𝜇𝑚) sinh ( 𝐿 𝑎 𝜇 𝑚 (1 − 𝜁)) ( 𝐿 𝑎 𝜇 𝑚 ) cosh ( 𝐿 𝑎 𝜇 𝑚 ) (245) lim ℎ→∞ 𝛩2,𝑧(𝜌, 𝜁) = 2∑ lim ℎ→∞ { −(𝐾𝐻)2𝜇 𝑘 𝜙 1 (𝜇𝑘) (𝐾𝐻)2 [ 4 𝜋2 − 𝜇 𝑘 2𝜙 1 2(𝜇𝑘)] + 𝜇𝑘 4𝜙 1 2(𝜇𝑘) }𝜙 0 (𝜇𝑘𝜌) sinh ( 𝐿 𝑎 𝜇 𝑘 (1 − 𝜁)) ( 𝐿 𝑎 𝜇 𝑘 ) cosh ( 𝐿 𝑎 𝜇 𝑘 ) ∞ 𝑘=1 (246) Temperature Solution for 𝑯𝒇 The solutions to each BVP (with eigenfunctions first) are: Θ1,𝑟 =∑ 𝐴𝑛 sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑛] 𝐼0(𝜆𝑛𝜌) ∞ 𝑛=1 𝑤ℎ𝑒𝑟𝑒 𝜆𝑛 > 0 𝑎𝑟𝑒 𝑟𝑜𝑜𝑡𝑠 𝑜𝑓 − 1 𝐻𝑓 ( 𝐿 𝑎 𝜆𝑛) = tan ( 𝐿 𝑎 𝜆𝑛) Θ2,𝑟 =∑𝐶𝑙 sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑙]𝜓0(𝜆𝑙𝜌) ∞ 𝑙=1 𝑤ℎ𝑒𝑟𝑒 𝜆𝑙 > 0 𝑎𝑟𝑒 𝑟𝑜𝑜𝑡𝑠 𝑜𝑓 − 1 𝐾𝐻𝑓 ( 𝐿 𝑎 𝜆𝑙) = tan ( 𝐿 𝑎 𝜆𝑙) Θ1,𝑧 = ∑ 𝐵𝑚𝐽0(𝜇𝑚𝜌) sinh [(1 − 𝜁) 𝐿 𝑎 𝜇𝑚] ∞ 𝑚=1 𝑤𝑖𝑡ℎ 𝜇𝑚 𝑡ℎ𝑒 𝑟𝑜𝑜𝑡𝑠 𝑜𝑓 − 𝜇𝑚𝐽1(𝜇𝑚) + 𝐻 𝐽0(𝜇𝑚) = 0 Θ2,𝑧 =∑ 𝐷𝑘𝜙0(𝜇𝑘𝜌) sinh [(1 − 𝜁) 𝐿 𝑎 𝜇𝑘] ∞ 𝑘=1 𝑤𝑖𝑡ℎ 𝜇𝑘 𝑡ℎ𝑒 𝑟𝑜𝑜𝑡𝑠 𝑜𝑓𝜇𝑘𝜙1(𝜇𝑘) + 𝐻 𝜙0(𝜇𝑘) = 0 The main source of added complexity is that the vertical eigenfunctions/eigenvalues are no longer the same in each material, meaning that the eigenfunction expansions of temperature along the interface can no longer be compared 172 term-by-term, complicating the evaluation of coefficients 𝐴𝑛 and 𝐶𝑙. However, since the procedure for obtaining the coefficients of the other subproblem is largely unchanged, they will be evaluated first. Substituting at the inhomogeneous condition at 𝜁 = 0 and using the orthogonality of 𝐽0, 𝜙0, the process of solving for 𝐵𝑚 and 𝐷𝑘 is complicated only by the fact that ∂ 𝜕𝜁 sinh [(1 − 𝜁) 𝐿 𝑎 𝜇𝑘] is no longer zero at 𝜁 = 0. This leads to expressions containing linear combinations of sinh and cosh: 𝐵𝑚 = 2𝐻𝐻𝑓 [𝐻2 + 𝜇𝑚 2 ]𝐽0(𝜇𝑚) ∙ 1 𝐻𝑓 sinh ( 𝐿 𝑎𝜇𝑚)+ 𝐿 𝑎𝜇𝑚 cosh ( 𝐿 𝑎𝜇𝑚) 𝐷𝑘 = 2𝐾2𝐻𝐻𝑓 𝜙0(𝜇𝑘) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2(𝜇𝑘) ∙ 1 𝐾𝐻𝑓 sinh ( 𝐿 𝑎𝜇𝑘)+ 𝐿 𝑎𝜇𝑘 cosh ( 𝐿 𝑎𝜇𝑘) Substituting, the subproblem solutions are Θ1,𝑧 = 2𝐻𝐻𝑓 ∑ ∞ 𝑚=1 𝐽0(𝜇𝑚𝜌) [𝐻2 + 𝜇𝑚 2 ]𝐽0(𝜇𝑚) ∙ sinh [(1 − 𝜁) 𝐿 𝑎𝜇𝑚] 𝐻𝑓 sinh ( 𝐿 𝑎𝜇𝑚)+ 𝐿 𝑎𝜇𝑚 cosh ( 𝐿 𝑎𝜇𝑚) Θ2,𝑧 = 2𝐾 2𝐻𝐻𝑓∑ 𝜙0(𝜇𝑘𝜌) 𝜙0(𝜇𝑘) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2(𝜇𝑘) ∙ sinh [(1 − 𝜁) 𝐿 𝑎𝜇𝑘] 𝐾𝐻𝑓 sinh ( 𝐿 𝑎𝜇𝑘)+ 𝐿 𝑎𝜇𝑘 cosh ( 𝐿 𝑎𝜇𝑘) ∞ 𝑘=1 As for the original isoflux problem, these solutions will be incorporated into a full eigenfunction expansion at the interface, requiring the evaluation of the expansion coefficients 𝐹𝑛 = ∫ sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑛] ∙ Θ2,𝑧𝑑𝜁 1 0 and 𝐺𝑙 = ∫ sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑙] ∙ Θ1,𝑧𝑑𝜁 1 0 . Carrying the integral under the summation, and using the definition of 𝜆𝑛, 𝜆𝑙 to substitute e.g. − 𝐿 𝑎 𝜆𝑙 cos ( 𝐿 𝑎 𝜆𝑙) = 𝐻𝑓 sin ( 𝐿 𝑎 𝜆𝑙) yields 173 𝐺𝑙 = 2𝐻𝐻𝑓 sin ( 𝐿 𝑎 𝜆𝑙) ∑ ∞ 𝑚=1 1 [𝐻2+𝜇𝑚 2 ] ∙ 1 ( 𝐿 𝑎 𝜇 𝑚 ) 2 + ( 𝐿 𝑎 𝜆𝑙) 2 ∙ 𝐾𝐻𝑓 sinh ( 𝐿 𝑎𝜇𝑚)+ 𝐿 𝑎𝜇𝑚 cosh ( 𝐿 𝑎𝜇𝑚) 𝐻𝑓 sinh ( 𝐿 𝑎𝜇𝑚)+ 𝐿 𝑎𝜇𝑚 cosh ( 𝐿 𝑎𝜇𝑚) 𝐹𝑛 = 2𝐾 2𝐻𝐻𝑓 sin ( 𝐿 𝑎 𝜆𝑛)∑ 𝜙0 2(𝜇𝑘) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2(𝜇𝑘) ∙ 1 ( 𝐿 𝑎 𝜇𝑘) 2 + ( 𝐿 𝑎 𝜆𝑛) 2 ∙ 𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑘) + 𝐿 𝑎 𝜇𝑘 cosh ( 𝐿 𝑎 𝜇𝑘) 𝐾𝐻𝑓 sinh ( 𝐿 𝑎 𝜇𝑘) + 𝐿 𝑎 𝜇𝑘 cosh ( 𝐿 𝑎 𝜇𝑘) ∞ 𝑘=1 Thus, the relation pair 𝜕Θ1,𝑟 𝜕𝜌 (1, 𝜁) + 𝐻 Θ1,𝑟(1, 𝜁) = 𝐻 [Θ2,𝑟 + Θ2,𝑧](1, 𝜁) 𝜕Θ1,𝑟 𝜕𝜌 (1, 𝜁) − 𝐾𝐻 Θ1,𝑟(1, 𝜁) = −𝐾𝐻 [Θ1,𝑟 + Θ1,𝑧](1, 𝜁) expands to ∑𝐴𝑛[𝜆𝑛𝐼1(𝜆𝑛) + 𝐻𝐼0(𝜆𝑛)] sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑛] ∞ 𝑛=1 = 𝐻 { ∑𝐶𝑙𝜓0(𝜆𝑙) sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑙] ∞ 𝑙=1 +∑ 𝐹𝑛 sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑛] [ 1 2 − sin(2 𝐿 𝑎⁄ 𝜆𝑛) 4 𝐿 𝑎⁄ 𝜆𝑛 ] ∞ 𝑛=1 } ∑𝐶𝑙[−𝜆𝑙𝜓1(𝜆𝑙) + 𝐾𝐻𝜓0(𝜆𝑙)] sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑙] ∞ 𝑙=1 = 𝐾𝐻 { ∑𝐴𝑛𝐼0(𝜆𝑛) sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑛] ∞ 𝑛=1 +∑ 𝐺𝑙 sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑙] [ 1 2 − sin(2 𝐿 𝑎⁄ 𝜆𝑙) 4 𝐿 𝑎⁄ 𝜆𝑙 ] ∞ 𝑙=1 } where [ 1 2 − sin(2 𝐿 𝑎 ⁄ 𝜆𝑙) 4 𝐿 𝑎 ⁄ 𝜆𝑙 ] is the normalizing factor resulting from ∫ sin2 [(1 − 𝜁) 𝐿 𝑎 𝜆𝑙] 𝑑𝜁 1 0 for the general 𝜆𝑛, 𝜆𝑙. This factor was simply 1/2 for the original isoflux problem. The other issue, again, is that the 𝐴𝑛 and 𝐶𝑙 are not expressed by the same set of eigenfunctions. Sifting for a particular 𝐴𝑛 (or 𝐶𝑙) coefficient returns a single 𝐹𝑛 (𝐺𝑙), but also a linear combination of the opposing 𝐶𝑙 (𝐴𝑛). An explicit example: 174 ∫ sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑛]∑𝐶𝑙𝜓0(𝜆𝑙) sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑙] ∞ 𝑙=1 1 0 𝑑𝜁 =∑𝐶𝑙𝜓0(𝜆𝑙)∫ sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑛] 1 0 sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑙] 𝑑𝜁 ∞ 𝑙=1 =∑𝐶𝑙𝜓0(𝜆𝑙) [ sin ( 𝐿 𝑎 (𝜆𝑛 − 𝜆𝑙)) 2 𝐿 𝑎 (𝜆𝑛 − 𝜆𝑙) − sin ( 𝐿 𝑎 (𝜆𝑛 + 𝜆𝑙)) 2 𝐿 𝑎 (𝜆𝑛 + 𝜆𝑙) ] ∞ 𝑙=1 It is convenient to define this eigenfunction overlap as a matrix 𝑺 with entries 𝑆𝑛,𝑙 = sin( 𝐿 𝑎 (𝜆𝑛 − 𝜆𝑙)) 2 𝐿 𝑎 (𝜆𝑛 − 𝜆𝑙) − sin( 𝐿 𝑎 (𝜆𝑛 + 𝜆𝑙)) 2 𝐿 𝑎 (𝜆𝑛 + 𝜆𝑙) Note that this overlap in the original isoflux case condensed to 𝑆𝑛,𝑙 = 1 2 𝛿𝑛,𝑙 since 𝜆𝑛, 𝜆𝑙 are from the same series of eigenvalues. In this problem, as 𝑛, 𝑙 → ∞, this behavior is recovered, so 𝑺 is “nearly diagonal.” This allows a matrix equation relating the vectors of solution coefficients 𝐴𝑛 and 𝐶𝑙: ?̃?𝐴 = 𝑺𝝍𝟎𝐶 + 𝐹 [𝑁 × 𝑁]𝑁 = [𝑁 × 𝐿][𝐿 × 𝐿]𝐿 + 𝑁 ?̃?𝐶 = 𝑺𝑇𝑰𝟎𝐴 + 𝐺 [𝐿 × 𝐿]𝐿 = [𝐿 × 𝑁][𝑁 × 𝑁]𝑁 + 𝐿 temporarily considering the finite series approximation of the first 𝑁 𝜆𝑛 and the first 𝐿 𝜆𝑙 eigenvalues for the purpose of illustrating dimension, and where ?̃?, ?̃?, 𝑰𝟎, and 𝝍𝟎 are diagonal matrices with elements ?̃?𝑛,𝑛 = [ 1 2 − sin(2 𝐿 𝑎⁄ 𝜆𝑛) 4 𝐿 𝑎⁄ 𝜆𝑛 ] ∙ 𝜆𝑛𝐼1(𝜆𝑛) + 𝐻𝐼0(𝜆𝑛) 𝐻 ?̃?𝑙,𝑙 = [ 1 2 − sin(2 𝐿 𝑎⁄ 𝜆𝑙) 4 𝐿 𝑎⁄ 𝜆𝑙 ] ∙ −𝜆𝑙𝜓1(𝜆𝑙) + 𝐾𝐻𝜓0(𝜆𝑙) 𝐾𝐻 175 𝐼0𝑛,𝑛 = 𝐼0(𝜆𝑛) 𝜓0𝑙,𝑙 = 𝜓0(𝜆𝑙) This allows the assembly of the (𝑁 + 𝐿) × (𝑁 + 𝐿) block matrix and associated equation [ ?̃? −𝑺𝝍𝟎 −𝑺 𝑇 𝑰𝟎 ?̃? ] [ ?⃗⃗⃗? ?⃗⃗⃗? ] = [ ?⃗⃗⃗? ?⃗⃗⃗? ] Computationally, if a finite series approximation of 𝑁 and 𝐿 terms has been chosen, this equation can be solved by inversion (although with enough terms it may be poorly conditioned/close to singular). Further study could point the way on handling the infinite solution. A good place to start may be interleaving rows and columns (mapping indices covering ℕ+ ℕ → ℕ). Swapping rows first: [ ?̃?1,1 0 ⋯ −𝑆1,1𝜓01 −𝑆1,2 ⋯ −𝑆1,1𝐼01 −𝑆2,1 ⋯ ?̃?1,1 0 ⋯ 0 ?̃?2,2 ⋯ −𝑆2,1 −𝑆2,2𝜓02 ⋯ −𝑆1,2 −𝑆2,2𝐼02 ⋯ 0 ?̃?2,2 ⋯ ⋮ ⋮ ⋱ ⋮ ⋮ ⋱ ⋮ ⋮ ⋱ ⋮ ⋮ ⋱ ] [ 𝐴1 𝐴2 ⋮ 𝐶1 𝐶2 ⋮ ] = [ 𝐹1 𝐺1 𝐹2 𝐺2 ⋮ ⋮ ] then columns: [ ?̃?1,1 −𝑆1,1𝜓01 0 −𝑆1,2 ⋯ ⋯ −𝑆1,1𝐼01 ?̃?1,1 −𝑆2,1 0 ⋯ ⋯ 0 −𝑆2,1 ?̃?2,2 −𝑆2,2𝜓02 ⋯ ⋯ −𝑆1,2 0 −𝑆2,2𝐼02 ?̃?2,2 ⋯ ⋯ ⋮ ⋮ ⋮ ⋮ ⋱ ⋱ ⋮ ⋮ ⋮ ⋮ ⋱ ⋱ ] [ 𝐴1 𝐶1 𝐴2 𝐶2 ⋮ ⋮ ] = [ 𝐹1 𝐺1 𝐹2 𝐺2 ⋮ ⋮ ] Since the original isoflux problem saw 𝑆𝑛,𝑙 = 1 2 𝛿𝑛,𝑙, this would reduce to a block diagonal matrix with 2x2 blocks on the diagonal, recovering the original term-by-term relationship for 𝐴𝑛, 𝐶𝑛. Again, at very large indices of this infinite matrix equation, this block behavior prevails for this more general case. 176 Recapping full solution: Θ1 = 2𝐻𝐻𝑓 ∑ ∞ 𝑚=1 𝐽0(𝜇𝑚𝜌) [𝐻2 + 𝜇𝑚 2 ]𝐽0(𝜇𝑚) ∙ sinh [(1 − 𝜁) 𝐿 𝑎𝜇𝑚] 𝐻𝑓 sinh ( 𝐿 𝑎𝜇𝑚)+ 𝐿 𝑎𝜇𝑚 cosh ( 𝐿 𝑎𝜇𝑚) +∑ 𝐴𝑛 sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑛] 𝐼0(𝜆𝑛𝜌) ∞ 𝑛=1 Θ2 = 2𝐾 2𝐻𝐻𝑓∑ 𝜙0(𝜇𝑘𝜌) 𝜙0(𝜇𝑘) 4 𝜋2 − [(𝐾𝐻)2 + 𝜇𝑘 2]𝜙0 2(𝜇𝑘) ∙ sinh [(1 − 𝜁) 𝐿 𝑎𝜇𝑘] 𝐾𝐻𝑓 sinh ( 𝐿 𝑎𝜇𝑘)+ 𝐿 𝑎𝜇𝑘 cosh ( 𝐿 𝑎𝜇𝑘) ∞ 𝑘=1 +∑𝐶𝑙 sin [(1 − 𝜁) 𝐿 𝑎 𝜆𝑙]𝜓0(𝜆𝑙𝜌) ∞ 𝑙=1 where 𝑤ℎ𝑒𝑟𝑒 𝜆𝑛 > 0 𝑎𝑟𝑒 𝑟𝑜𝑜𝑡𝑠 𝑜𝑓 − 1 𝐻𝑓 ( 𝐿 𝑎 𝜆𝑛) = tan ( 𝐿 𝑎 𝜆𝑛) 𝑤ℎ𝑒𝑟𝑒 𝜆𝑙 > 0 𝑎𝑟𝑒 𝑟𝑜𝑜𝑡𝑠 𝑜𝑓 − 1 𝐾𝐻𝑓 ( 𝐿 𝑎 𝜆𝑙) = tan ( 𝐿 𝑎 𝜆𝑙) 𝑤𝑖𝑡ℎ 𝜇𝑚 𝑡ℎ𝑒 𝑟𝑜𝑜𝑡𝑠 𝑜𝑓 − 𝜇𝑚𝐽1(𝜇𝑚) + 𝐻 𝐽0(𝜇𝑚) = 0 𝑤𝑖𝑡ℎ 𝜇𝑘 𝑡ℎ𝑒 𝑟𝑜𝑜𝑡𝑠 𝑜𝑓𝜇𝑘𝜙1(𝜇𝑘) + 𝐻 𝜙0(𝜇𝑘) = 0 177 Figure 70: Enlarged view of Figure 60 178 REFERENCES [1] Green, D. S., Dohrman, C. L., and Chang, T., 2014, "The DARPA Diverse Accessible Heterogeneous Integration (DAHI) Program: Status and Future Directions," CS MANTECH Conference, Denver, Colorado, pp. 343. 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