ABSTRACT Title of Document: CHARACTERIZATION AND MODELING OF HIGH POWER MICROWAVE EFFECTS IN CMOS MICROELECTRONICS. Michael A. Holloway, Doctor of Philosophy, 2010 Directed By: Professor & Chair, Patrick G. O'Shea, Department of Electrical and Computer Engineering The intentional use of high power microwave (HPM) signals to disrupt microelectronic systems is a substantial threat to vital infrastructure. Conventional methods to assess HPM threats involve empirical testing of electronic equipment, which provides no insight into fundamental mechanisms of HPM induced upset. The work presented in this dissertation is part of a broad effort to develop more effective means for HPM threat assessment. Comprehensive experimental evaluation of CMOS digital electronics was performed to provide critical information of the elementary mechanisms that govern the dynamics of HPM effects. Results show that electrostatic discharge (ESD) protection devices play a significant role in the behavior of circuits irradiated by HPM pulses. The PN junctions of the ESD protection devices distort HPM waveforms producing DC voltages at the input of the core logic elements, which produces output bit errors and abnormal circuit power dissipation. The dynamic capacitance of these devices combines with linear parasitic elements to create resonant structures that produce nonlinear circuit dynamics such as spurious oscillations. The insight into the fundamental mechanisms this research has revealed will contribute substantially to the broader effort aimed at identifying and mitigating susceptibilities in critical systems. Also presented in this work is a modeling technique based on scalable analytical circuit models that accounts for the non-quasi- static behavior of the ESD protection PN junctions. The results of circuit simulations employing these device models are in excellent agreement with experimental measurements, and are capable of predicting the threshold of effect for HPM driven non-linear circuit dynamics. For the first time, a deterministic method of evaluating HPM effects based on physical, scalable device parameters has been demonstrated. The modeling presented in this dissertation can be easily integrated into design cycles and will greatly aid the development of electronic systems with improved HPM immunity. CHARACTERIZATION AND MODELING OF HIGH POWER MICROWAVE EFFECTS IN CMOS MICROELECTRONICS By Michael A. Holloway Dissertation submitted to the Faculty of the Graduate School of the University of Maryland, College Park, in partial fulfillment of the requirements for the degree of Doctor of Philosophy 2010 Advisory Committee: Professor Patrick G. O'Shea, Chair Doctor John Rodgers Professor Neil Goldsman Professor Victor Granatstein Professor Aris Christou ? Copyright by Michael A. Holloway 2010 ii Dedication To my parents Theodore B. Holloway Jr. and Shirley L. Holloway for all of their love, support, and sacrifices. iii Acknowledgements It is difficult to find the words of gratitude to adequately express my profound appreciation to so many people who have mentored, encouraged, and inspired me during my time as a student in IREAP. My journey began when I met Professor Patrick O'Shea in spring of 2002. I was a student in his basic circuit theory class when he offered me a job to work in his lab as an undergraduate. From that point on he has been a constant mentor, advisor, and example. He has encouraged and supported me at every step in my journey. I am forever grateful for all Professor O'Shea has done for me. Working with Dr. John Rodgers over the past two years has truly been a privilege. Dr. Rodger's is a brilliant experimentalist who is dedicated to his students. I will cherish the opportunity I had to work with him and always appreciate the fact that I had a research advisor who also liked to talk football. I would like to thank Dr. Zeynep Dilli who has gone out of her way to assist me many times. I would also like to offer a special thanks to Dr. Neil Goldsman who generously offered advice both academic and personal, and who gave me the opportunity to work with him on some very exciting projects outside of my doctoral research. I am also very grateful to have worked Dr. Ralph Fiorito and Dr. Anatoly Shkvarunets who mentored me for my Masters research. Many more names and many more stories could fill endless pages of this acknowledgement. So I would like to thank all of the many people of IREAP who I have ever had the great privilege to work with, to call colleagues, and most importantly, to call friends. I would also like to thank the Air Force Office of Scientific Research for their support of this work. iv Table of Contents Dedication .................................................................................................................... ii? Acknowledgements .................................................................................................... iii? Table of Contents ....................................................................................................... iv? List of Tables .............................................................................................................. vi? List of Figures ............................................................................................................ vii? Chapter 1 : Introduction ............................................................................................ 1? 1.1?Motivation ........................................................................................................... 1? 1.2 Fundamental Description of HPM Effects .......................................................... 3? 1.2.1 HPM Sources ............................................................................................... 4? 1.2.2 EM Coupling and Cavity Effects ................................................................. 4? 1.2.3 Circuit and Device Effects ........................................................................... 6? 1.3 Historical Overview ............................................................................................ 8? 1.3.2 HPM Effects Research ............................................................................... 11? 1.3.3 Focus of Recent Research Efforts .............................................................. 13? 1.4 Project Overview .............................................................................................. 18? Chapter 2 : Circuit Design ....................................................................................... 21? 2.1 Test Circuit Overview ....................................................................................... 21? 2.2 Basic Logic Gate Design .................................................................................. 22? 2.2.1 Design and Layout ..................................................................................... 22? 2.1.2 Performance Evaluation ............................................................................. 27? 2.3 JK Flip Flop and 4 Bit Counter Design ............................................................ 29? 2.3 ESD Protection Circuit ..................................................................................... 32? 2.4 Input and Output Buffer Circuits ...................................................................... 36? 2.4.1 Input Buffer ................................................................................................ 36? 2.4.2 Output Buffer ............................................................................................. 38? 2.5 Full Test Circuit Evaluation .............................................................................. 42? Chapter 3 : Experimental Approach....................................................................... 47? 3.1 Introduction ....................................................................................................... 47? 3.2 Direct Injection Experiments ............................................................................ 48? 3.3 Printed Circuit Board Design ............................................................................ 52? 3.4 Experimental Methods ...................................................................................... 55? 3.4.1 Instrument Control and Data Acquisition .................................................. 55? 3.4.2 Measurement Procedure ............................................................................. 56? Chapter 4 : Input Analysis and ESD-HPM Interaction ........................................ 58? 4.1 Introduction ....................................................................................................... 58? 4.2 Theoretical Background ? PN Junction Transient Analysis ............................. 58? 4.2.1 Linear Approximations and Initial Steady State ........................................ 60? 4.2.2 Reverse Recovery Transient ...................................................................... 63? 4.2.3 Approximation of Non-Quasi-static Effects .............................................. 65? 4.3 Experimental Results ........................................................................................ 71? 4.3.2 Accounting for linear parasitic elements ................................................... 73? v 4.3.3 Determining the Voltage Amplitude at the Input ...................................... 77? 4.4 Chapter Conclusions ......................................................................................... 83? Chapter 5 : HPM Effects in CMOS Test Circuits .................................................. 85? 5.1 Introduction ....................................................................................................... 85? 5.2 Experimental Results for the Single Inverter Test Circuit ................................ 86? 5.2.1 Output Voltage Measurements .................................................................. 87? 5.2.2 Current Measurement Results .................................................................... 91? 5.3 Analysis of Experimental Measurements on the Single Inverter Test Circuit .. 94? 5.3.1 Analysis of Output Voltage Measurements ............................................... 95? 5.3.2 Analysis of Current Measurements ............................................................ 98? 5.3.3 Summary of Analysis ............................................................................... 106? 5.4 Experimental Measurements of CMOS Digital Test Circuits ........................ 106? 5.4.1 In-Band HPM Effects .............................................................................. 107? 5.4.2 Out-of-Band HPM Effects ....................................................................... 113? 5.4.3 Analysis of Out-of-Band Oscillation Effects ........................................... 124? 5.5 Summary and discussion................................................................................ 129? Chapter 6 : Modeling HPM Effects in CMOS...................................................... 134? 6.1 Modeling Approach ........................................................................................ 134? 6.2 Modeling the Input ESD Response to HPM Excitation.................................. 137? 6.2.1 Background on BSIM Drain/Source to Body PN Junction Model .......... 137? 6.2.2 Compensating for Non Quasi-Static Behavior ........................................ 139? 6.2.3 Input Response Simulations Results ........................................................ 141? 6.3 Modeling the Single Inverter Test Circuit ...................................................... 147? 6.3.1 In-Band Simulation .................................................................................. 148? 6.3.2 Out-of-Band Simulation........................................................................... 151? 6.4 Modeling HPM Effects in the CMOS Test Circuits ....................................... 154? 6.4.1 In Band Effects Modeling on Full test IC's .............................................. 154? 6.4.2 Out-of-Band Effects Modeling on Full test IC's ...................................... 157? Chapter 7 : Discussion and Conclusions ............................................................... 169? 7.1 Summary of Experimental Results ................................................................. 169? 7.2 HPM Effects Modeling ................................................................................... 175? 7.3 Future Work .................................................................................................... 176? 7.4 Closing Remarks ............................................................................................. 179? Appendix: BSIM Parameters ................................................................................. 181? Bibliography ............................................................................................................ 183? vi List of Tables Table 2.1: Physical parameters of basic logic cells extracted from the layout ........... 26? Table 2.2: Intrinsic device characteristics derived from SPETCRE simulations ....... 29? Table 2.3: Dimensional parameters for the ggNMOS and ggPMOS per finger ......... 34? Table 2.4: Dimensional parameters for a single finger of the 6 finger inverter of the input buffer circuit. ..................................................................................................... 37? Table 2.5: Dimensional parameters for the output buffer circuit ................................ 41? Table 2.6: Results of performance measurements for the test circuits under digital excitation ..................................................................................................................... 45? Table 4.1: Minority carrier diffusion constants in silicon ........................................... 67? Table 5.1: Approximate values for each element of the total load capacitance of single inverter test circuit ...................................................................................................... 96? Table 6.1: Substrate resistance value for the ESD protection devices ...................... 142? vii List of Figures Figure 1.1: Primary elements of typical HPM effects scenarios .................................. 4? Figure 1.2: Example of experimental verification of the RCM on a computer case. Port 1 antenna broadcasts the attacking waveform while the statistics of the induced voltage were measured at Port 2[34]. ......................................................................... 14? Figure 1.3: Measured PDF of induced voltages at PORT 2 versus the PDF predicted by the RCM for frequency range of 8 to 9 GHz. The plot on the left is for a flat power spectral density (PSD) and the figure on the right is for a Gaussian PSD[34]. .......... 15? Figure 1.4: Input voltage response (left) and output waveform (right) for a commercial CMOS IC excited by HPM[38] .............................................................. 16? Figure 1.5: Example of a test structure used to measure the behavior of ESD devices when influenced by HPM signals[42]......................................................................... 18? Figure 2.1: General test circuit topology .................................................................... 22? Figure 2.2: NOT gate schematic (left) and layout (right) ........................................... 24? Figure 2.3: Two input NAND gate schematic (left) and layout (right) ...................... 24? Figure 2.4: Two input NOR gate schematic (left) and layout (right) ......................... 25? Figure 2.5: Three input NAND gate schematic (left) and layout (right) .................... 25? Figure 2.6: Four input NOR gate schematic (left) and layout (right) ......................... 26? Figure 2.7: Plot of the voltage transfer characteristics of the NOT; Illustration of noise margin measurement ................................................................................................... 27? Figure 2.8: Current drive curve for the NOT gate ..................................................... 28? Figure 2.9: Schematic (top) and layout (bottom) of the JK flip flop test circuit ........ 30? Figure 2.10: Schematic (top) and layout of the 4 bit counter test circuit .................... 31? Figure 2.11: Cross section of ggNMOS ESD protection device showing the parasitic BJT .............................................................................................................................. 33? Figure 2.12: Individual gate grounded NMOS layout ................................................ 34? Figure 2.13: ESD protection ring and bonding pad arrangement for the digital test circuits ......................................................................................................................... 35? Figure 2.14: Schematic and layout of the inverter used in the input buffer circuit .... 36? Figure 2.15: Voltage transfer curve for the input buffer circuit. ................................ 37? Figure 2.16: Transient simulation of the input buffer circuit...................................... 38? Figure 2.17: Output buffer schematic ......................................................................... 40? Figure 2.18: Output buffer layout ............................................................................... 40? Figure 2.19: Voltage transfer curve for the output buffer circuit ............................... 41? Figure 2.20: Input and output voltage waveform from transient simulation of the output buffer circuit. ................................................................................................... 42? Figure 2.21: Measurement setup for test circuit performance evaluation .................. 44? Figure 2.22: Average current measurement results for the HPM effects test circuits 45? Figure 3.1: Schematic of the experimental setup for direct injection experiments .... 48? Figure 3.2: Schematic of bias network for probing input signals ............................... 49? Figure 3.3: Photograph of the RF probe, bias network, and high pass filter .............. 50? Figure 3.4: Photographs of the breadboard probing station ........................................ 51? Figure 3.5: Photograph of the complete experimental setup ...................................... 52? viii Figure 3.6: Photograph of a test PCB design for a chip containing the JK flip flop and the 4 bit counter .......................................................................................................... 54? Figure 3.7: Battery attachment for the DUT ............................................................... 54? Figure 3.8: Example program written in Agilent VEE Pro. ....................................... 56? Figure 4.1: Drain body PN junction for a ggNMOS ................................................... 59? Figure 4.2: One sided step junction in steady state forward bias................................ 62? Figure 4.3: Reverse current vs time. t1 is the length of time for the storage phase and t2 is the time of the recovery phase defined by the point at which the reverse current reaches 10% of its initial value. .................................................................................. 64? Figure 4.4: The effect of the reverse recovery approximation .................................... 68? Figure 4.5: Calculated ESD protection device DC response over a frequency range of 100 MHz to 10 GHz .................................................................................................... 69? Figure 4.6: Simplified schematic of input ESD protection device arrangement ........ 70? Figure 4.7: Test circuit input stage measurement schematic ...................................... 71? Figure 4.8: Example time trace illustrating how detected voltage is measured. ......... 72? Figure 4.9: Measured Input detected voltage for frequencies 100 MHz to 900 MHz, which illustrates how ESD diode response changes with frequency. ......................... 72? Figure 4.10: Measured Input detected voltage for frequencies 1 GHz to 4 GHz, which illustrates how ESD diode response changes with frequency. .................................... 73? Figure 4.11: Detected voltage vs. frequency for a constant input power of 15dBm demonstrating the effects of linear parasitic elements on the input response. ............ 74? Figure 4.12: Input test board used to measure linear parasitic elements .................... 75? Figure 4.13: Test setup for measuring the S-parameters of the linear parasitic elements ...................................................................................................................... 76? Figure 4.14: Forward reflection and transmission coefficients for the input linear parasitic elements. ....................................................................................................... 76? Figure 4.15: Reverse reflection and transmission coefficients for the input linear parasitic elements. ....................................................................................................... 77? Figure 4.16: Measured small signal capacitance of the ESD protection circuits vs frequency for various input DC bias [42]. .................................................................. 80? Figure 4.17: Measured voltage gain for frequencies of 100 MHz to 1 GHz .............. 81? Figure 4.18: Measured voltage gain for frequencies of 1 GHz to 4 GHz ................... 81? Figure 4.19: Detected voltage plotted vs. the input voltage amplitude that was calculated from the gain measurement. ...................................................................... 82? Figure 5.1: Schematics for the single inverter test circuit .......................................... 87? Figure 5.2: Mean output voltage vs. input RF power and frequency of the single inverter test circuit for frequencies from 100 MHz to 800 MHz. ............................... 87? Figure 5.3: Mean output voltage vs. input RF power and frequency of the single inverter test circuit for frequencies from 1 GHz to 4 GHz. ........................................ 88? Figure 5.4: Output voltage waveforms for input HPM amplitude of 4V and for frequencies of 100 MHz (top), 600 MHz (middle) and 1 GHz (bottom). The plots demonstrate the change in the output voltage response from 100 MHz to 1 GHz ..... 89? Figure 5.5: Output voltage waveform for input HPM amplitude of 4V and for frequency 2.5 GHz. The plot shows the output response resembles a single state change in the inverter that occurs for the duration of the HPM pulse. ....................... 90? ix Figure 5.6: Average current vs. input RF power and frequency of the single inverter test circuit for frequencies from 100 MHz to 800 MHz. ............................................ 91? Figure 5.7: Average current vs. input RF power and frequency of the single inverter test circuit for frequencies from 1 GHz to 4 GHz. ...................................................... 92? Figure 5.8: Average current draw vs. input voltage amplitude for frequencies from 100 MHz to 600 MHz for the single inverter test circuit. ........................................... 93? Figure 5.9: Average current draw vs. input voltage amplitude for frequencies from 1 GHz to 4 GHz for the single inverter test circuit. ....................................................... 93? Figure 5.10: Simple digital MOSFET model used to approximate the maximum the switching speed of the single inverter test circuit. ...................................................... 95? Figure 5.11: Schematic diagram of dynamic current in a CMOS inverter ................. 99? Figure 5.12: Short circuit current in a CMOS inverter during full state changes. .... 100? Figure 5.13: Measured average current for input drive frequency of 200 MHz compared to theoretical calculation of the average current for full transistor switching. ................................................................................................................................... 102? Figure 5.14: Measured maximum average current values compared to theoretical calculation for the single inverter test circuit. ........................................................... 103? Figure 5.15: Comparison of the measured average current to the input detected voltage and the mean output voltage of the single inverter test circuit, with input drive frequency of 1 GHz. .................................................................................................. 104? Figure 5.16 : Comparison of the measured average current to the input detected voltage and the mean output voltage of the single inverter test circuit, with input drive frequency of 2.5 GHz. ............................................................................................... 104? Figure 5.17: DC transfer curve for the single inverter test circuit. ........................... 105? Figure 5.18: Mean output voltage of the digital test circuits versus the input amplitude. The inverter test circuit was driven at 200 MHz. The JK flip-flop and 4-bit counter were driven at 100 MHz. ............................................................................. 107? Figure 5.19: In-band output voltage response for the inverter chain circuit (top), the JK flip-flop (middle), and the 4-bit counter. ............................................................. 109? Figure 5.20: Output voltage spectrum for in-band HPM excitation for the inverter chain circuit (top), the JK flip-flop (middle), and the 4-bit counter. ........................ 110? Figure 5.21: Measured HPM induced current compared to normal operation current for the inverter chain test circuit. .............................................................................. 111? Figure 5.22: Measured HPM induced current compared to normal operation current for the JK flip-flop test circuit. ................................................................................. 112? Figure 5.23: Measured HPM induced current compared to the current measured under normal digital excitation for the 4 bit counter test circuit. ........................................ 112? Figure 5.24: Mean output voltage of each of the digital test circuits for HPM excitation frequency of 2.5 GHz. The plot demonstrates the onset of HPM induced single bit errors. ........................................................................................................ 114? Figure 5.25: Example of single bit error in the inverter chain test circuit ................ 115? Figure 5.26: Current measurement for the inverter chain circuit with input drive of 2.5 GHz (left); Output voltage during current spike at 2 V input amplitude (right) ....... 115? Figure 5.27: Output voltage spectrum for the inverter chain test circuit with RF input frequency of 1 GHz ................................................................................................... 118? x Figure 5.28: Example of stable (top) and aperiodic (bottom) output oscillations for the inverter chain test circuit driven at RF frequency of 1 GHz ..................................... 119? Figure 5.31: Output voltage spectrum for the flip-flop test circuit with RF input frequency of 1 GHz. .................................................................................................. 120? Figure 5.32: Output voltage spectrum for the least significant bit of the counter test circuit with RF input frequency of 1 GHz. ............................................................... 120? Figure 5.33: Output voltage spectrum for the second least significant bit of the counter test circuit with RF input frequency of 1 GHz. ............................................ 121? Figure 5.34: Output voltage spectrum for the second most significant bit of the counter test circuit with RF input frequency of 1 GHz. ............................................ 121? Figure 5.35: Output voltage spectrum for the second most significant bit of the counter test circuit with RF input frequency of 1 GHz. ............................................ 122? Figure 5.36: Current measurement for the inverter chain test circuit with an input RF frequency of 1 GHz ................................................................................................... 123? Figure 5.37: Current measurement for the JK flip-flop test circuit with an input RF frequency of 1 GHz ................................................................................................... 123? Figure 5.38: Current measurement for the 4 bit counter test circuit with an input RF frequency of 1 GHz .................................................................................................. 124? Figure 5.29: Lower band frequency spectrum for the output (left) and the input (right) for an input RF amplitude of 6.5 V at 1 GHz ........................................................... 126? Figure 5.30: Plot of the input and output voltage phase difference compared to the output signal. The output signal trace is blue and the phase difference is red. ......... 127? Figure 5.39: Color legend for the summary of results presented in figures 5.40, 5.41, and 5.42 ..................................................................................................................... 130? Figure 5.40: Summary of effects observed for the inverter chain circuit ................. 130? Figure 5.41: Summary of effects observed for the JK flip flop circuit ..................... 131? Figure 5.42: Summary of effects observed for the 4-bit counter .............................. 131? Figure 6.1: BSIM 4 substrate resistor network ......................................................... 140? Figure 6.2: ADS schematic for input response simulation ....................................... 141? Figure 6.3: Comparison of simulation and experiment for the detected voltage of the ESD protection circuit at a fixed input power .......................................................... 143? Figure 6.4: Detected voltage predicted by simulation with the body resistor ESD model vs. experiment for input frequency of 200 MHz ............................................ 144? Figure 6.5: Detected voltage predicted by simulation without the body resistor ESD model vs. experiment for input frequency of 200 MHz ............................................ 144? Figure 6.6: Detected voltage predicted by simulation with the body resistor ESD model vs. experiment for input frequency of 1 GHz ................................................ 145? Figure 6.7: Detected voltage predicted by simulation without the body resistor ESD model vs. experiment for input frequency of 2.5 GHz ............................................. 145? Figure 6.8: Detected voltage predicted by simulation with the body resistor ESD model vs. experiment for input frequency of 2.5 GHz ............................................. 146? Figure 6.9: Detected voltage predicted by simulation without the body resistor ESD model vs. experiment for input frequency of 2.5 GHz ............................................. 146? Figure 6.10: ADS Schematic used for single inverter test circuit simulations ......... 148? Figure 6.11: Simulation output waveforms for input amplitude of 4 V at 200 MHz for single inverter test circuit. ......................................................................................... 149? xi Figure 6.12: Comparison with experiment of the mean output voltage and average current predicted by simulation for the single inverter test circuit with an input frequency of 200 MHz. ............................................................................................. 149? Figure 6.13: Example of output voltage waveform distorted due to overdriven input amplitude................................................................................................................... 150? Figure 6.14: Simulation output waveforms for input amplitude of 4 V at 1 GHz for the single inverter test circuit. ................................................................................... 152? Figure 6.15: Comparison with experiment of the mean output voltage and average current predicted by simulation for the single inverter test circuit for frequencies 1 GHz (top) and 2.5 GHz (bottom). ............................................................................. 153? Figure 6.16: Simulation time domain waveforms of the output voltage of the inverter chain circuit (top), JK flip flop (middle), and the most significant bit of the 4 bit counter (bottom)........................................................................................................ 155? Figure 6.17: Comparison with experiment of the mean output voltage and average current predicted by simulation for the inverter chain circuit at 200 MHz input frequency (top), and the JK flip flop (middle) and 4 bit counter (bottom) with an input frequency of 100 MHz. ............................................................................................. 156? Figure 6.18: Comparison with experiment of the mean output voltage and average current predicted by simulation for the inverter chain circuit (top), the JK flip flop (middle) and 4 bit counter (bottom) with 2.5 GHz input frequency. ....................... 158? Figure 6.20: Simulation vs. experiment for the output voltage of the inverter chain circuit when driven by a 1 GHz HPM signal ............................................................ 160? Figure 6.20: Simulation vs. experiment for the average current of inverter chain circuit when driven by a 1 GHz HPM signal ............................................................ 160? Figure 6.21: Simulation vs. experiment for the output voltage of the JK flip flop circuit when driven by a 1 GHz HPM signal ............................................................ 161? Figure 6.22: Time domain plot of the output voltage of the JK flip flop for an input amplitude of 3.5 V and frequency of 1 GHz ............................................................ 162? Figure 6.23: Simulation vs. experiment for the output voltage of the most significant bit of the 4 bit counter circuit when driven by a 1 GHz HPM signal ....................... 164? Figure 6.24: Time domain plot of the output voltage of the most significant bit of the 4 bit counter for input amplitude of 3.5 V and frequency of 1 GHz ......................... 164? Figure 6.25: Simulation vs. experiment for the average current of the JK flip flop circuit when driven by a 1 GHz HPM signal ............................................................ 165? Figure 6.26: Simulation vs. experiment for the average current of the 4 bit counter circuit when driven by a 1 GHz HPM signal ............................................................ 166? Figure 6.27: Schematic used for simulation verification of oscillation dynamics. ... 167? Figure 6.28: Output voltage results of the simulation of the JK flip flop circuit in Figure 6.27. ............................................................................................................... 167? Figure 7.1: Estimation of the radiation power density needed to stimulate HPM effects ........................................................................................................................ 174? Figure 7.2: Example device build for RF illumination experiment .......................... 177? Figure 7.3: Anechoic chamber designed for HPM effects testing ............................ 178? 1 Chapter 1 : Introduction 1.1 Motivation Over the past few decades, technology has advanced at an astonishing pace. Equally astonishing is how quickly human civilization has adopted and assimilated new technologies into every facet of life. Many clever inventions begin as a convenience or luxury but quickly become a dependency as their practicality often relieves the drudgery of cumbersome and time consuming tasks. Among the greatest inventions of the 20th Century and perhaps even in all of human history is the integrated circuit. Microelectronic technology has become ubiquitous; so much so that daily life depends on microelectronic systems. The emergence of interconnected systems enabled by the growth of the internet has furthered our reliance on microelectronic systems. Much of our financial system exists as digital data stored in vast networks of computer systems accessible completely through the internet. Commercial transactions are often completed without the use of paper currency via the internet or wireless devices. Microelectronic systems have also greatly enhanced medical technology and improved overall health care considerably compared to only a few decades ago. Vital civil infrastructure such as traffic control systems, public transportation, automobiles, aircraft, and ships all rely on a myriad of microelectronic control and communication systems. With the unending proliferation of technology comes an increased need to protect vital systems from potentially catastrophic disruptions. Generically, this is referred to as cyber security. Most of the global conversation regarding cyber 2 security deals with software driven attacks and network breaches. However, an emerging concern, critical to cyber security, is the protection of the physical layer. An attack on the physical layer refers to a directed attack on the microelectronic devices themselves. An example of such a physical layer threat that is gaining considerable attention in both military and civilian sectors is the ability of microwave radiation to disrupt the proper function of microelectronic systems. Microwave energy is transmitted by many sources such as radar, cell phone towers, Wi-Fi transmitters, satellite communications, or even portable electronic devices. The phenomenon of errant microwave signals interfering with the operation of electronics systems is not an entirely new concern. Anyone traveling by commercial jet has experienced the request to refrain from using portable electronic devices during the critical moments of takeoff and landing. Disruption from electromagnetic interference (EMI) generated by electronic equipment and wireless systems has been studied for some time. In the United States, electronic systems must meet electromagnetic compatibility standards (EMC) to ensure that equipment is able to function reliably in its electromagnetic environment without itself introducing intolerable electromagnetic disturbances [1]. Also, aircraft must have adequate shielding to protect instrumentation from high power sources such as radar [2]. The greater and more substantial threat to infrastructure and equipment is the intentional emission of microwave energy to disrupt or damage microelectronic systems. A focused attack from a high powered microwave (HPM) source can disrupt or destroy critical systems with potentially lethal consequences. The concern about such a scenario occurring has increased considerably over the past two decades 3 [3-14]. The threat of terrorism has prompted the evaluation of the susceptibility of electronic systems to the HPM threat in the US and many European countries. Many systems remain unprotected, and EMC standards set by governing authorities regulate electric fields produced by low-level of microwave emissions. The vulnerability of electronic systems to HPM is a glaring Achilles heel to vital civil infrastructure that must be addressed. 1.2 Fundamental Description of HPM Effects The term "HPM effects" as used throughout the body of this work refers to the specific behavior or physical effects in microelectronic systems that occur as a result of intentional focusing of high power microwave energy onto the system. HPM interaction with microelectronics systems is a very complex phenomenon when one considers all the elements involved in a typical HPM effects scenario. It is comprised of several fundamental stages, as depicted in Figure 1. A source of directed energy emits HPM radiation, which penetrates enclosures and excites EM modes within the enclosure. Circuit board traces and wires act as antennas that couple EM energy into microelectronic devices. The devices respond to the HPM excitation, producing effects that will potentially trigger system upset or cause physical damage. 4 Figure 1.1: Primary elements of typical HPM effects scenarios 1.2.1 HPM Sources A survey of the literature will reveal a somewhat ambiguous classification of what qualifies as an HPM source [6, 11, 15, 16]. In general an HPM source is classified as one that is capable of producing at least 100 MW of peak RF power in the frequency range of 1 MHz to 100 GHz, with pulse durations that range from tens of nanoseconds to a few microseconds [15, 17, 18]. Examples of HPM sources include klystrons, magnetrons, and gyrotrons. 1.2.2 EM Coupling and Cavity Effects HPM will couple to microelectronic systems in many ways. Any system that communicates with the outside world will have ingress paths that potentially harmful electromagnetic energy can penetrate. Electromagnetic coupling to a system is 5 typically considered in two categories. "Front door" is defined as the HPM coupling to systems through ports intended to transmit signals for communication with other systems[4]. Wireless systems with antennas such as Wi-Fi, cells phones, and blue tooth are good examples of systems with front door vulnerability. Protecting systems from front door coupling presents a particularly difficult challenge. Any attempt to attenuate or filter unwanted signals will also adversely affect the reception and processing of normal signals. Also, receiver systems typically have low noise amplifiers, which could unintentionally amplify harmful signals [13]. "Back door" coupling is defined as electromagnetic coupling to wires, power lines, circuit traces, or any part of the system not specifically designed to transmit or receive RF signals [4]. Back door coupling creates voltages on traces and wires that superimpose with normal signals and enter device terminals. While circuit traces and wires are not designed specifically to transmit and receive signals, they introduce parasitic resonances in systems that reduce the level of RF power required to stimulate HPM effects [4]. Cavity fields are another important aspect of HPM effects. HPM will penetrate enclosures such as computer cases and excite field distributions according to the resonant modes of the structure. Predicting these field distributions deterministically is difficult due to the complexity of the EM boundary conditions that are typical of even the most basic electronic enclosures. Often times the dimensions of the enclosures and the corresponding EM boundaries are many times greater than the wavelength of the HPM radiation. Thus, structures support numerous modes that are typically closely spaced in frequency [19]. Further complicating the 6 analysis of EM fields is the fact that the EM boundaries are rarely static. Small changes due to motion, vibration, or temperature may substantially alter the field distribution. 1.2.3 Circuit and Device Effects As technology advances towards smaller faster devices, the potential of microwave energy to disrupt electronic systems may increase [12, 20]. Smaller electronic devices require less charge to switch states and have reduced noise margins [20]. Also, oxide layers become more vulnerable to dielectric breakdown as their thickness decreases. In addition to technological advances in microelectronic fabrication, continued advances in the power output capabilities of microwave sources will also increase circuit vulnerability. The study of circuit and device effects involves determining the port or input voltage transfer characteristics when these ports and pins are excited by HPM signals. On the system level, the objective is to establish how effects cascade throughout the large-scale systems and cause upset. In the literature electronic circuit and system upset levels are generally classified according to their severity. A commonly used and accepted classification is found in [17]: ? "deny"- Denial is upset caused by HPM signals that disrupt the function of a system for the duration of the event without causing any lasting damage to the system. The affected system will typically return to normal operation after the event. This type of disruption is also often referred to as "jamming". ? "degrade"- Degrade is a very interesting classification. At this level of upset, the HPM signal still does little to no damage to the affected system's 7 components. However, the induced upset persists after the HPM event is over and the affected system must be reset to return to normal operation. An example would be an HPM event that causes a computer system to freeze, requiring that the system be rebooted. On occasion, this general condition is incorrectly referred to as "latch-up", which is a very specific upset condition exclusive to CMOS devices. ? "damage"- Damage is one of two levels of upset that departs from the disruption of function from invading signals to the physical breakdown of materials that make up the system components. This level of upset will include device level oxide breakdown in MOS gates, bonding wire degradation due to thermal effects, etc. In terms of the total system, "damage" refers to a particular component of the affected system being damaged and needing to be replaced for the system to return to normal function. For example, if only an Ethernet card of a computer is damaged during and HPM event, the computer system itself will return to normal operation once the card has been removed or replaced. ? "destroy"- Destruction is the most severe upset HPM can cause to a microelectronic system. Destruction occurs when high levels of EM energy couple to a system and causes numerous components to suffer irreparable damage. The severity of the inflicted damage necessitates replacement of the entire system. 8 The upset classifications "deny" and "degrade" primarily deal with the circuit response to HPM signals. The study of these levels of upset will deal primarily with semiconductor device physics and circuit theory. In contrast, "damage" and "destroy" levels of upset involve the material properties of the system components such as the dielectric breakdown levels of oxide gates and thermal tolerances of bond wires. 1.3 Historical Overview The work presented in this dissertation focuses on the study of the effects of HPM signals on the operation of CMOS circuits. This section contains a summary of the literature relevant to the study of electrometric interference effects in solid sate electronics. 1.3.1 Electromagnetic Interference Research Some of the earliest work concerning electromagnetic interference effects in digital integrated circuits was conducted in the late 1970's. The prevailing device technology at the time was the bi-polar junction (BJT) transistor based TTL logic. Work conducted by Richardson [2, 21, 22] investigated the ability of microwave signals to shift the quiescent operation point of a bipolar junction transistor. Richardson demonstrated that low level RF signals are rectified by the nonlinear response of the emitter-base junction. An interesting result of this work was that, although the rectification response decreases with frequency, frequencies several orders of magnitude above the transition frequency of the device were also rectified. Larson and Roe [23] developed a modified Ebers-Moll transistor model capable of worst case scenario prediction of low level rectification effects in BJT's. Whalen et al used the modified Ebers-Moll model to perform susceptibility analysis on 7400 TTL 9 NAND gates using SPICE [24]. He demonstrated that RF injected at the input was capable of shifting the DC output level above or below the noise margins resulting invalid logic states. In the 1980's the emphasis shifted to field effect transistors, as CMOS emerged as the preferred technology for digital integrated circuits. The first susceptibility analysis of a MOS device was published in 1981 by Roach [25]. In this study he characterized the susceptibility of NMOS memories. A very important work published by Kenneally [26] investigated the influence of electrostatic discharge (ESD) protection circuits on device susceptibility to EMI. Kenneally performed both experiments and computer simulation on a protected and unprotected D-type flip-flop and 8086 microprocessor. He demonstrated that EMI susceptibility decreases by approximately 40 dB as the RF frequency is increased from 5 MHz to 300 MHz. The maximum switching frequency of the device was approximately 5 MHz, which suggests that CMOS electronic devices are more susceptible to RF interference within their normal operating band. He also showed that ESD protection circuits can potentially increase device susceptibility, and that the more advanced 8086 processor was more susceptible at higher interference frequencies, which suggests susceptibility frequency ranges increases with more advanced process technologies. Another work by Kenneally et al [27] presented experimental results on CMOS D-type flip flops that demonstrated greater susceptibility of the clock terminal by as much as 20 dB higher than that of the V dd power terminals. Tront [28] performed a very interesting analysis on the typical input and output stages of CMOS digital IC's using SPICE2 simulations. The circuit 10 configuration for these experiments involved an output driver stage connected to an input buffer circuit, which would be typical of a data line between two independent IC's. RF signals of frequencies ranging from 80 MHz to 260 MHz were injected on the line between the output and input stages and the RF amplitude was varied from 0 to 26 V. Tront showed that 3 effects occurred based on the level of RF injection. High levels of injection produced a state latching effect, which prevented the circuit from changing state in the presence of a normal logic signal. For medium levels of injection, multiple state changes were observed during times when none were expected. Low levels of injection increased the delay time of the circuit. Throughout 1990's a significant amount of work on EMI was conducted by a group at the University of Toronto. Laurin [29] conducted studies on EMI effects in clocked digital circuits. He termed effects as either static, which are EMI induced logic transitions, or dynamic, which involves changes in propagation delay. He showed that changes in propagation delay can lead to timing violations in clocked circuits, which can also lead to system failures. Laurin et al [30] also developed a method for the prediction of EMI induced delays using linear steady sate frequency domain analysis that could be applied to large systems without requiring extensive computer resources. Wallace [31] performed experiments on various CMOS and TTL D-type flip-flops using short transient impulses at the device input terminals. By synchronizing the impulse with clock signal, Wallace showed that devices are more susceptible when interference occurs near the clock transitions. Macleod performed very interesting work in her PhD dissertation [32]. She designed an apparatus to conduct EMI susceptibility stress testing of electronic circuit 11 boards. The testing technique and theory developed in this work is capable of locating weak components that fail due to EMI stress. She also expanded the theory of EMI- induced delay to include high frequency and transmission line effects. 1.3.2 HPM Effects Research The previous section presented a summary of work on the susceptibility of electronics to stray microwave energy produced by the environment. This section highlights work specifically focused on the intentional use of focused HPM to disrupt microelectronic systems. A great deal of work in this area is not available in the public domain due to the inherent defense applications of HPM technology [3]. The following overview presents HPM research centered on civilian applications and susceptibility of electronic systems vital to civil infrastructure. The conventional method of assessing HPM susceptibility presenting in the following literature is the use of empirical testing. In the early 1990's, Pesta et al [33] proposed a standardized method for microelectronic system susceptibility assessment. He describes a methodology comprised of extensive low power microwave tests to measure EM coupling data to systems leads such as wires and board traces, and to assess the upset thresholds of individual system components. The collected data is used to create a database of susceptibility levels for the system under test. The second component of the method involves limited high power microwave testing to validate the database. A group at the University of Hanover in Germany published several studies based on empirical testing of electronic equipment when exposed to ultra-wide band HPM pulses. In one study, Camp et al [9] performed susceptibility studies on 12 microcontroller circuits, where failure rates were measured as a function of the signal line length and HPM pulse rise time. They were able to demonstrate correlation between line length, HPM pulse rise time, and susceptibility, and presented a statistical failure distribution function for the prediction of susceptibility based on the external field strength. A similar study was conducted on personal computers with several generations of Intel processors ranging from the 8088 to the Pentium III [7]. The computers were subjected to UWB HPM pulses with rise times that ranged from 100 ps to 10 ns, pulse widths of 2.5 ns to 1.6 ?s, and amplitudes that ranged from 25 kV to 1 MV. As reported by the authors, the major result of this study was that susceptibility increases substantially with newer computer generations. B?ckstr?m et al with the Swedish Defense Research Agency published a comprehensive work which presents a summary of a decade's worth of HPM testing conducted at the Swedish Microwave Test Facility [5]. HPM effects tests were conducted on various military and civilian systems such as tactical radios, automobiles, computers, etc. The journal article reports many useful general susceptibility trends including the following: Effects are more prominent in the L and S band range (1 GHz to 4 GHz), upset thresholds for systems usually occurs at few hundred volts per meter, and permanent damage begins to occur at field levels of 15 to 25 kV/m and that damage can occur when the system is turned off. Other tests were conducted to determine the effective upset range of different HPM sources. An interesting study was performed by collaborative effort between Kim et al at the University of Maryland and Bayram et al at Ohio State University [6]. The work involved HPM testing of a digital timer circuit used for spark plug sequencing 13 in an automobile. The results of this study showed that even though automotive structures provide significant metal shielding, HPM induce upset can still be achieved using with reasonably achievable power levels. The study also successfully incorporated numerical EM analysis with conventional high frequency circuit simulation techniques to model and evaluate the system under test. 1.3.3 Focus of Recent Research Efforts Recent efforts at the University of Maryland, as part of the Multidisciplinary University Research Initiative (MURI) from 2001 to 2006, began to investigate HPM effects with a new approach. The intention of the MURI project was to conduct research on a basic level in order to determine the physical mechanisms whereby HPM pulses can upset or damage modern integrated circuits, and to develop models and methodology to enable the design of HPM resistant microelectronic systems. Using innovative techniques, this research began the development of methods for evaluating HPM effects that are more effective and produce deeper insight then purely empirical methods. One project during the MURI was focused on the difficult problem of evaluating induced voltages for objects inside complex enclosures such as computer cases and aircraft cockpits. As was noted previously, wavelengths at microwave frequencies tend to be very small compared to the dimensions of enclosures that contain microelectronic systems. Electronic enclosures also tend to have complex geometries where field distributions are highly sensitive to frequency and small perturbations. This makes deterministic evaluations of the field distributions with any degree of precision virtually impossible [34]. 14 A statistical approach was developed to overcome the difficulties in describing fields in complex microelectronic enclosures. The result of this effort was computational model known as the Random Coupling Model (RCM) [34-37]. RCM is capable of predicting the probability density function (PDF) of voltages induced at a targeted electronic component within an enclosure. This calculation is possible with knowledge of the following basic parameters: the radiation impedance of the ports of the enclosure, the radiation impedance of the targeted electronic component, the volume and approximate loss characteristics of the enclosure, and the frequency of the incident waveform [34-37]. RCM has been extensively tested on both idealized enclosures and computer cases. Figures 1.2 and 1.3 show an example of the success of the RCM [34-37]. Figure 1.2: Example of experimental verification of the RCM on a computer case. Port 1 antenna broadcasts the attacking waveform while the statistics of the induced voltage were measured at Port 2[34]. 15 Figure 1.3: Measured PDF of induced voltages at PORT 2 versus the PDF predicted by the RCM for frequency range of 8 to 9 GHz. The plot on the left is for a flat power spectral density (PSD) and the figure on the right is for a Gaussian PSD[34]. In the experiment, the paddles created perturbations in the boundary conditions and mix the modes within the computer cases. The results in figure 1.3 and other experimental verifications show that the RCM accurately predicts the voltage PDF for a given port. Overall this research has produced very promising success and shown great potential for the statistical modeling of HPM fields inside complex enclosures. Another part of the MURI program studied how HPM signals affected the operation of integrated circuits. Early studies performed on commercial IC's revealed that HPM can produce complex dynamics in circuits that result in bit errors, spurious oscillations, and undefined logic states. Figure 1.4 highlights two of the important overall results from measurements performed on a commercial CMOS inverter [38]. 16 Figure 1.4: Input voltage response (left) and output waveform (right) for a commercial CMOS IC excited by HPM[38] The figure on the left demonstrates that the input parasitic impedances greatly influence the actual voltage amplitude at the gate of the device. The red shaded region is where the input voltage levels are higher than the RF amplitude voltage due to resonant voltage gain. On the plot on the right, the blue trace represents the HPM pulse envelope as it corresponds to the output voltage, which is represented by the red trace[38]. The output voltage demonstrates the complex dynamics observed when HPM was injected into the commercial inverter. Results such as these were common with many different commercial ICs. The observations from experiments on commercial devices prompted two parallel efforts to further study the complex circuits dynamics provoked by HPM interference on a more fundamental level. Both of these projects made use of custom fabricated devices designed specifically to measure the effects of HPM signals on normal device operation. One effort studied the influence of HPM on basic IC units such as individual MOSFETs and CMOS inverters. The key results of these experiments are the demonstration of HPM influence on device output current, 17 transistor transconductance, output conductance, and breakdown voltage. Another very important observation was that HPM effects diminished greatly at frequencies above 4 GHz [39-41]. The second research effort focused on the influence of electrostatic discharge (ESD) protection devices on circuit behavior when excited by HPM [42]. Previous studies have speculated that ESD protection devices play a central role in HPM effects. ESD devices typically take the form large PN junction diodes and are present in most commercial IC's. The devices are meant to prevent damage to the core circuit during incidents of electrostatic discharge. Aside from some passive loading, ESD devices are designed to have marginal influence to normal circuit operation. However, when excited by sufficiently large voltage amplitudes the devices can produce a significant DC component at the input of the core circuit thereby enhancing device susceptibility [42]. The experiments in this study were performed on specially designed structures that allow the ESD devices to be measured directly on the silicon chip using specialized precision RF probes. An example of one of these structures is shown in figure 1.5. 18 Figure 1.5: Example of a test structure used to measure the behavior of ESD devices when influenced by HPM signals[42] Extensive measurements on ESD protection devices were performed and revealed that the nonlinear response of the drain to body PN junction greatly enhances HPM effects in simple CMOS inverters for frequencies from 100 MHz to 4 GHz. The characterization of these devices revealed that, at higher HPM frequencies, transient PN junction voltages are not accurately described by simple rectification based on quasi-static approximations [42]. This work also presented preliminary efforts to deterministically model HPM effects in basic devices using scalable physical parameters. 1.4 Project Overview The research presented in this work is part of a larger effort to develop a foundational method for accurately predicting probability of effect in microelectronic systems when illuminated by HPM. The objective is build on the successes of the work presented in section 1.3.3 and contribute to the effort to combine statistical prediction of terminal voltages of devices in complex enclosures with deterministic circuit models that accurately predict HPM effects thresholds. This dissertation ESD Protection Device RF Probe Pads 19 details the results of experimental research performed to study the fundamental mechanisms responsible for HPM effects CMOS circuits, and the development of accurate deterministic modeling techniques to improve effects prediction capability. Chapter 2 of the dissertation presents the design methodology and performance verification of the custom CMOS ICs created for this study. Chapter 3 details the experimental method for injecting HPM signal in to CMOS test circuits and the instrumentation arrangement used to accurately measure circuit response characteristics. Chapter 4 focuses on the input stage of the test circuits exploring in detail the response of the ESD protection devices and relating experimental observation to the relevant device physics. Chapter 5 contains the experimental measurements of the voltage and current characteristics for each of the test circuits, and the analysis of the experimental results used to determine the fundamental dynamics of the observed HPM effects. Chapter 6 presents the modeling techniques used to predict HPM effects thresholds and circuit behavior, and compares simulation results with the experimental measurements. Chapter 7 contains the summary discussion of the research effort and the near term future worked. Highlights of accomplishments in this work include: 1. Development of effective experimental methods for evaluating HPM effects in integrated circuits. 2. Evaluation of circuit input response characteristics based on semi-conductor device physics. 3. Identification of fundamental dynamics involved in observed HPM induced output voltage characteristic in digital CMOS circuits. 20 4. Identification and characterization of abnormal current behavior in CMOS circuits due to HPM effects. 5. Successful HPM effects prediction of CMOS test circuits using compact circuit models based on scalable physical parameters. 6. Demonstration of a technique for HPM effects prediction of non-quasi-static device behavior in ESD protection circuits that can be adapted to BSIM CMOS compact models. 21 Chapter 2 : Circuit Design 2.1 Test Circuit Overview Previous efforts to characterize and model HPM effects in circuits and devices involved experimental evaluation of commercial devices and the use of either basic spice models or models provided by the manufacturer [28, 38]. These spice models are very simple, and in some cases are merely look up tables. Most of the compact model parameters and circuit topology is not made available due to proprietary restrictions. In order to avoid these restrictions, custom designed circuits were fabricated for this work. Custom circuits allow for exact knowledge of all significant parameters that are critical for accurate simulation efforts. All of the analytical model parameters extracted from the process test wafers are also available for each of the test circuits. The general philosophy for the test circuit design is to create basic CMOS circuits using established design principles, which are very similar in structure to their commercial counterpart. Fabricating custom test chips also facilitated measurement of the various stages of a circuit as isolated blocks and as an interconnected system. Thus susceptibility to HPM could be studied in terms of how effects cascade through circuits. The following chapter details the design process for creating the test circuits used in this study. Test circuits were designed using Cadence Virtuoso layout tools and fabricated on the AMI (On Semiconductor) 0.6 ?m process, available through the MOSIS service[43]. The test circuits are all comprised of four basic elements: ESD protection circuits, input buffer, core logic, and output buffer as depicted in figure 2.1. 22 Figure 2.1: General test circuit topology 2.2 Basic Logic Gate Design 2.2.1 Design and Layout This section covers the design of the core logic circuits. In order to create a series of digital test circuits, a basic digital standard cell library was designed consisting of the following logic gates: ? NOT (inverter) ? NAND two input ? (AND two input) ? NAND three input ? (AND three input) ? NOR two input ? (OR two input) ? NOR four input ? (OR four input) The complement of the NAND and NOR gates are created by combining each with a NOT gate. Each cell is made with a standard spacing 13.95 ?m between parallel ground lines and V dd lines to make combining logic gates structurally simple and orderly. Each transistor is designed with the minimum gate width of 0.6 ?m. The widths of each MOS device are kept as small as possible. The ideal switching point 23 for CMOS is V dd /2, which balances the noise margins and ensures the best performance. To accomplish this, the switching characteristics and hence the current characteristic of the NMOS and PMOS should be balanced. The difference in NMOS and PMOS switching characteristics lies in the effective switching resistance defined by equation 2.1 [44]. , 2 , 2 () dd np np dd th LV R kWV V ? = ?? (2.1) V th is the threshold voltage, and W and L are the gate width and length respectively, and the term k is defined by equation 2.2. ,np ox kC?= (2.2) ? n,p is the surface mobility of electrons and holes respectively. C ox is the gate capacitance per unit area. The effective switching resistance of the NMOS and PMOS differs due to the term k and its dependence on mobility. In silicon, the mobility of electrons is approximately two to three times larger than the mobility holes. For this reason, the width of the PMOS is typically three times larger than the NMOS width in the initial design. However, this is based on approximation, and ignores most short channel effects. Thus, the width ratio should be adjusted to ensure the switching point occurs at V dd /2. During the design process, it was determined that a width ratio of 2:1 provided the optimal balance between NMOS and PMOS for the basic inverter. The widths of the other standard cells are also influenced by the number of MOSFETs in parallel or series compared to each transistors compliment. Transistors in parallel reduce the overall effective resistance while parallel connections increases it, and thus widths are 24 adjusted to compensate. The following figures are the schematics and layouts of each cell followed by Table 2.1, which summarizes the important physical parameters. Figure 2.2: NOT gate schematic (left) and layout (right) Figure 2.3: Two input NAND gate schematic (left) and layout (right) 25 Figure 2.4: Two input NOR gate schematic (left) and layout (right) Figure 2.5: Three input NAND gate schematic (left) and layout (right) 26 Figure 2.6: Four input NOR gate schematic (left) and layout (right) Table 2.1: Physical parameters of basic logic cells extracted from the layout ? Gate?Width? (?m)? Drain/Source Diffusion area (m 2 ) Drain/Source Diffusion Perimeter (?m) NOT?NMOS? 1.5? 2.25E?12? 6? NOT?PMOS ? 3? 4.5E?12? 9? NAND?2?NMOS? 1.5? 2.25E?12? 6? NAND?2?PMOS? ? 1.5? 2.25E?12? 6? NOR?2?NMOS? 1.5? 2.25E?12? 6? NOR?2?PMOS? ? 3? 4.50E?12? 9? NAND?3?NMOS? 3? 4.50E?12? 9? NAND?3?PMOS ? 1.5? 2.25E?12? 6? NOR?4?NMOS? 1.5? 2.25E?12? 6? NOR?4?PMOS? 6? 9.00E?12? 15? 27 2.1.2 Performance Evaluation The following basic performance evaluation was conducted using Cadence Spectre circuit simulator. The purpose of the evaluations is to verify the basic design functionality and to assure the device operations conform to established circuit design standards [44, 45]. Extraction was performed on the layout of each circuit in order to include the parasitic capacitances in the simulations. An important performance measure for CMOS electronics in general are the noise margins [44, 45]. One of the greatest advantages to CMOS digital circuits over its junction transistor counterpart is its large noise margins. Consider the voltage transfer curve for the NOT gate in figure 2.6. Any voltage below red line marked V IL is considered a valid logic low on the input of the inverter. Figure 2.7: Plot of the voltage transfer characteristics of the NOT; Illustration of noise margin measurement 28 Any voltage above the line marked V IH is considered a valid logic high on the input of the gate. V IH and V IL are defined by the point where the slope of voltage transfer curve is equal to -1[44]. In other terms, when the input of the circuit is logic low, the circuit can handle any voltage noise level at the input up to V IL without changing state. The region in between V IL and V IH is considered an invalid logic state. In addition to the noise margins, the peak transition current was evaluated for each gate. This is the current drawn by the CMOS circuit as it transitions from one state to another. The plot in figure 2.7 shows the drive curve for the NOT gate. Figure 2.8: Current drive curve for the NOT gate Table 2.2 contains the noise margin and peak current data for each of the gates in the standard cell library for Vdd equal to 3 V. 29 Table 2.2: Intrinsic device characteristics derived from SPETCRE simulations ? VIH?(V)? VIL?(V)? High?Noise?Margin? (V)? Low?Noise?Margin?(V)? Peak?Current? (?A)? NOT? 1.77? 1.33? 1.23? 1.33? 34.2? NAND?2? 1.65? 1.25? 1.35? 1.25? 20.4? NOR?2? 1.66? 1.23? 1.34? 1.23? 28.2? NAND?3? 1.59? 1.25? 1.41? 1.25? 33.6? NOR?4? 1.78? 1.31? 1.22? 1.31? 44.2? 2.3 JK Flip Flop and 4 Bit Counter Design A JK flip-flop and 4 bit synchronous counter were designed as a representative digital test circuit in this study. The flip-flop was chosen because they are ubiquitous devices found in many computational and storage circuits such as synchronizers, registers, and counters [46]. The flip flop also provided the basic building block for the 4 bit counter and can be used as a building block for other computational test circuits in the future. The flip flop design utilizes 2 three input NAND gates, 6 two input NAND gates, and one NOT gate with total transistor count of 48 [46]. The device switches state on the negative transition edge of the input clock signal only when logic 1 is present at the J and K terminals. For the JK flip flop test circuits used in this study, the J and K terminal are permanently tied to the V dd . This creates a T flip flop configuration where the state of the device is only controlled though the input clock signal. One important question to answer in regards to HPM effects is how effects observed on simple CMOS circuits cascade through more complex circuits. A 4 bit synchronous counter was designed for this purpose. The counter represents a very common and basic computational digital logic component. The design consists of 4 30 JK flip flops, 1 two input AND gate, and 1 three input AND gate for a total of 202 transistors. The counter is controlled by an input clock signal and all four bits are available to output pins through the output buffer circuit to allow for independent probing. Figure 2.9 and 2.10 are the schematics and layouts of flip flop and counter circuits. Figure 2.9: Schematic (top) and layout (bottom) of the JK flip flop test circuit 31 Figure 2.10: Schematic (top) and layout of the 4 bit counter test circuit 32 2.3 ESD Protection Circuit ESD protection devices are essential elements in commercial IC's. One of the greatest reliability problems that face the IC industry is the loss of product yield due to ESD generated failure [47, 48]. ESD events occur when two oppositely charged objects are brought into close proximity of one another and charges transfer from object to the other very rapidly. Electrostatic discharges are an extremely fast phenomenon with durations of approximately 100 ns [47]. The resulting current can be as high as tens of Amps and the voltage on the order of kilovolts. When this transient event occurs on I/O pins of IC's, the result is often degradation or destruction of the device. ESD protection devices are large dimension devices whose purpose is to provide a low impedance path in order to shunt high peak ESD currents to ground or through the supply rail, and to clamp the input voltage to a safe level to avoid input gate damage due to dielectric breakdown. The devices are fabricated directly onto the silicon chip just after the bonding pads to the I/O port of the IC [48]. ESD devices can present input and output loading problems to ICs, especially for more advanced very deep sub-micron process technologies. For this reason, many advanced ESD topologies inaccessible due to proprietary restrictions. The ESD protection devices used in the test circuits designed for this study are the gate grounded NMOS (ggNMOS) and gate grounded PMOS (ggPMOS). These ESD devices are well known and commonly used in many commercial IC's [49]. The ggNMOS consists of a large dimension NMOS where the drain is connected to the 33 I/O pin and the gate is connected to ground along with the source. The ggPMOS is configured in the same manner with the exception that the gate is connected to V dd . The ggNMOS and ggPMOS take advantage of a parasitic bipolar junction transistor that is formed between the drain, source and body of the device as shown in figure 2.11[49]. Figure 2.11: Cross section of ggNMOS ESD protection device showing the parasitic BJT When a positive ESD pulse appears at the drain of the ggNMOS, the drain body junction is reversed bias until the avalanche breakdown voltage is reached. A hole current to ground through the body of the device is generated due to the impact ionization created by the breakdown phenomenon. This current creates a voltage drop across the body resistance. As the voltage increases, the source body junction will eventually forward bias. At this point the parasitic NPN BJT turns on, creating a low impedance path to ground away from the input gate of the protected circuit [49]. This process of triggering the parasitic BJT is referred to as snap-back. The ggNMOS and ggPMOS used in the test circuits consist of a 12 finger MOSFET. The dimensions for the ggNMOS and ggPMOS are typically the same since the two transistors do not form a CMOS pair and hence there is no need to 34 balance switching characteristics. Figure 2.12 shows the layout of the ESD protection devices followed by table 2.3, which lists the dimensional parameters. Figure 2.12: Individual gate grounded NMOS layout Table 2.3: Dimensional parameters for the ggNMOS and ggPMOS per finger Gate Width (?m) Gate Length (?m) Drain Diffusion area (m 2 ) Drain Diffusion Perimeter (?m) Source Diffusion area (m 2 ) Source Diffusion Perimeter (?m) 30 0.9 1.845E-10 72.6 8.1e-10 65.4 Polysilicon gate of individual fingers 35 The ESD protection devices are placed together with a metal bonding pad, and each individual ESD and bonding pad section fits together to form a pad ring as shown in figure 2.13. Figure 2.13: ESD protection ring and bonding pad arrangement for the digital test circuits. Individual ESD pad section Digital test circuits 36 2.4 Input and Output Buffer Circuits 2.4.1 Input Buffer Input buffer circuits serve the purpose of accepting input signal to the chip and creating a clean signal to the logic circuits. Typically an input buffer will have very sharp voltage transfer characteristics (high dynamic gain) in order to sharpen any imperfections that may be on the input signal. The input buffer design chosen for this work is a simple two inverter stage buffer with each inverter having equal dimensions. The schematic and layout of the inverter used in the buffer circuit is shown in figure 2.14, followed by dimensional parameters in table 2.4. Figure 2.14: Schematic and layout of the inverter used in the input buffer circuit. 37 Table 2.4: Dimensional parameters for a single finger of the 6 finger inverter of the input buffer circuit. Gate Width (?m) Gate Length (?m) Drain/Source Diffusion area (m 2 ) Drain/Source Diffusion Perimeter (?m) NMOS PMOS 7.95 15.6 0.6 0.6 7.16E-10 1.40E-10 113.4 205.2 The dimensions of the inverter circuit were optimized to create a sharp transfer characteristic centered at approximately 1.5 V. Figure 2.15 shows the voltage transfer curve of the buffer circuit obtained through Sprectre simulation. The blue trace is the voltage transfer curve of the first inverter stage and the red trace is the voltage transfer curve for the full circuit. As can be seen from the plot, the input buffer has very large noise margins with V IL equal to 1.44 V and V IH equal to 1.56 V. Figure 2.15: Voltage transfer curve for the input buffer circuit. 38 The typical load for the input buffer will be at the most on the order of 150 fF, which is the approximate maximum input capacitance of the digital test circuits. Figure 2.16 shows the results of the simulation of the input buffer with a 150 fF load. The input signal was given a slow rise time of 10 ns to demonstrate how the buffer circuit sharpens the rising and falling edges of the signal. The basic inverter based buffer is a common input circuit technique for simple systems. More complex input circuits are often employed in many larger systems to assure timing errors don't result from the input signal rise and fall times being sharpened [44]. However, for this study, the simpler buffer is adequate. Figure 2.16: Transient simulation of the input buffer circuit. 2.4.2 Output Buffer The output of the digital IC must be able to drive the total output load capacitance of the circuit. This capacitance includes the parastic capacitance from the ESD, the board trace, and the input capacitance of the circuits recieving data. For the 39 test setup used in this work the load capacitance will be as a high as a few picofarads. The digital elements described in section 2.2 are not capable of driving such high capacitances. This is typical of any circuit and the difficulty is overcome by proper design output buffer stage. The design goal of an output buffer is to be able to drive a large capacitive load while not substaintially contributing to the propagation delay [44]. The ouput driver used in the test circuit was design using a very common technique. The method involves designing an inverter string with each inverter's width larger than the previous inverter's by a factor "A", which is defined by equation (2.3). 1 1 N load in C A C ?? = ?? ?? (2.3) C load is the load capacitance of the final stage and C in1 is the input capacitance of the first stage. The factor N is the total number of stages defined by equations (2.4). ln load in C N C = (2.4) The concept is that the effective switching resistance of each stage is reduced by the factor A. The total switching resistance is therefor reduced by a factor of A N [44]. As a result, each stage is capable of driving a larger capacitance and no one stage is driving a capacitance that causes a dramatic increase in the total propagation delay. The width and number of stages can be further optimized from the calculated values to minimize the delay. The output driver consists of 3 stages and the schematic and layout are shown in figure 2.17 and figure 2.18, followed by the dimensional parameters in table 2.5. 40 Figure 2.17: Output buffer schematic Figure 2.18: Output buffer layout Individual inverters 41 Table 2.5: Dimensional parameters for the output buffer circuit ? Gate? Width? (?m)? Drain/Source Diffusion area (m 2 ) Drain/Source Diffusion Perimeter (?m) Number of fingers Inverter?1?NMOS? 1.5? 2.25E?12? 6.0? 1? Inverter?1?PMOS ? 3? 4.50E?12? 9.0? 1? Inverter?2?NMOS? 2.85? 4.28E?12? 8.7? 5? Inverter?2?PMOS? ? 4.65? 6.98E?12? 12.3? 4? Inverter?3?NMOS? 11.1? 1.67E?11? 25.3? 8? Inverter?3?PMOS?? 44.4? 6.67E?11? 91.8? 4? The dimensions of each inverter stage was optimized to be able to drive a 5 pF load, which is larger than the typical circuit load used in the experiments. Figure 2.19 shows the drive curve of the buffer circuit at each of its stages acquired from Spectre simulation. Figure 2.19: Voltage transfer curve for the output buffer circuit 42 Figure 2.20 shows the result of transient simulation of the output buffer with an input pulse signal with a 1 ns rise time and a load capacitance of 5 pF. The results predict a propagation delay of 1.6 ns, which is acceptable for the test circuits used in this study. Figure 2.20: Input and output voltage waveform from transient simulation of the output buffer circuit. The rise time of the output is approximately 1 ns, which demonstrates that the circuit will perform very well under the experimental load requirements. 2.5 Full Test Circuit Evaluation This section presents the evaluation of the test circuits used in this study under normal operating conditions. The purpose of this evaluation is determine the maximum digital operating frequency of each circuit and the average current drawn within the normal operating band of each circuit. This distinction is important because HPM signals may be inside the normal operating range or far beyond it. As 43 will be shown in later chapters, circuit effects can be better understood when the operating limits of the circuit are known. . The following test circuits are assembled as shown in the general circuit in figure 2.1: ? single NOT gate (inverter) ? JK flip flop ? 4 bit counter In addition to these circuits, an individual inverter circuit without any buffer stages was independently fabricated. This single inverter test circuit is the same inverter used to construct input buffer shown in figure 2.14. The single NOT gate circuit will be referred to as the "inverter chain circuit" since it consists of 6 total inverters including the buffer stages. This is to avoid confusion with the single inverter test circuit. Each chip is packaged in a LCC 44 surface mount carrier and the chips were mounted to a test printed circuit board. A digital input signal was generated by a Tektronix AWG5014 arbitrary waveform generator. The signal generator is capable of producing a digital waveform with frequencies up to 100 MHz. Probe points were soldered as close as possible to the input and output pins, and Tektronix TAP1500 oscilloscope probes were connected in order to measure the input and output signals. The input and output probes were fed to a Tektronix MSO 4104 mixed signal oscilloscope. The power supply voltage was set 3 V to provide the rail voltage. A Keithley model 6487 picoammeter was connected to the current return path to measure the average current. The complete experimental setup is show in figure 2.21 44 Figure 2.21: Measurement setup for test circuit performance evaluation The first measurement performed was to verify the basic functionality of each of the test circuits. The propagation delay was measured and used to determine the upper operational frequency limit of each test circuit. The frequency limit is assumed to have a period equal to the delay. The delay measurements were performed by measuring the time difference of the input rise and the output rise at the point where they are both at 50% of V dd [44]. The same measurement is performed for the input and output fall times and the two delay times are averaged to obtain the propagation delay. For current measurements, the input frequency was swept from 1 MHz to 100MHz and the pulse width was maintained at one half the periods for each frequency to ensure maximum switching and congruence between each frequency. The results of the current measurements are presented in the plot in figure 2.22. 45 Figure 2.22: Average current measurement results for the HPM effects test circuits The current of the test circuits increases linearly with frequency, which is consistent with basic circuit theory [44, 45]. Average current values for frequencies above 100 MHz can be linearly extrapolated from these results. Table 2.6 is the summary of the measurement results for the propagation delay and maximum average current for the full test circuits. Table 2.6: Results of performance measurements for the test circuits under digital excitation Circuit Propagation Delay (ns) Maximum Frequency (MHz) Average Current at maximum frequency (mA) Single Inverter 1.67 592 MHz 5.5 Inverter Chain 2.90 340 MHz 5.6 JK Flip Flop 6.92 140 MHz 3.2 4 Bit Counter 7.10 140 MHz 3.2 46 The results in table 2.6 will serve as a benchmark for comparison with the voltage and current characteristics measured in the HPM experiments. 47 Chapter 3 : Experimental Approach 3.1 Introduction This chapter provides a detailed description of the experimental method developed to evaluate HPM effects in the test circuit. The objective of the experimental work is to characterize HPM signal transfer characteristics of the test circuits at the circuit terminals in order to determine the primary mechanisms of HPM effects and to facilitate the development of effects models. A great deal of importance is placed on precisely knowing input terminal voltages with respect to the observed output behavior. Great care is taken in all experimental measurements to minimize and account for the inevitable parasitic impedances introduced when taking measurements. Direct injection of HPM signals to circuit terminal and board traces are used to minimize any ambiguities in determining the terminal voltages, and provide an accurate means of controlling test parameters. Similar methods have been employed in many previous experiments used to study EMI effects and HPM effects [29, 30, 38, 42, 50]. 48 3.2 Direct Injection Experiments A schematic of the experimental setup for direct injection measurements is shown in Figure 3.1. Figure 3.1: Schematic of the experimental setup for direct injection experiments The signal generator used to create an HPM signal in the experiments is an Agilent E8257 D analog signal generator. The generator is capable of producing signals with frequencies ranging from 250 kHz to 40 GHz with various modulation schemes. To increase the power output capability of the test signal, the signal generator is fed into one of two RF amplifiers. Two different model amplifiers are used to cover the entire test frequency range. An OPHIR model 5303065 amplifier with a gain of 34 dB was used for the frequency range of 100 MHz to 1 GHz, and OPHIR model 5303053 with a gain of 31 dB was used for frequencies from 1 GHz up to 4 GHz. Each amplifier has a gain variation of +/- 2 dB. A 20 dB attenuator was connected between the signal generator and the amplifiers. This was done to decrease the sensitivity of the total output power to very small adjustments of the signal 49 generators output power. The output of the amplifier is attach to a 100 MHz high pass filter, which is meant to block any spurious DC bias from the amplifier from feeding to the input of the circuit. The bias network is an arrangement of resistors chosen such that the input signal could be sampled while at the same time preventing the measurement probe from loading the RF input signal. A schematic of the biasing network is given in figure 3.2. Figure 3.2: Schematic of bias network for probing input signals The network is put together on a printed circuit board with surface mount resistors, and the traces made as short as possible to minimize any parasitic effects. The connection to the input is made through an SMA terminal attach to a T junction, which is in the main signal line. The ground connection is made to a metal plane on the printed circuit board. The probe attaches to the network via pins soldered directly to the board to minimize parasitic inductance. This method of probing the input was chosen so that information such as frequency content could be acquired at the input terminal along with input DC values. The traditional method is use to a commercial 50 bias T network; however, these devices only allow for DC measurements. The resistor creates a voltage divider with the measurement probe that needs to be accounted for to obtain accurate voltage information. The bias network is connected to a Cascade Microtech FPC - 1000 ground signal ground (GSG) probe, which injects the RF signal into the DUT. The probe is mounted on a micrometer controlled precision positioner. Using a probe such as this offers several advantages over standard SMA connection. From a mechanical perspective, the probe easily positioned to various inputs of a test board. Also, the probes are very well matched to 50 ?s and have impedance standards for calibrating a vector network analyzer for S-parameter measurements of board trace elements. A picture of the high pass filter bias network and RF probe is shown in figure 3.3. Figure 3.3: Photograph of the RF probe, bias network, and high pass filter The probe positioner is attached to a 2.5' X 2.5' optical breadboard that serves as a mounting platform for the device under test (DUT) and any probe components. The DUT is mounted on a level plane that is attached to a micrometer positioner that allows for adjustments in the x, y, and z planes. A Zeiss Stemi 2000-C Stereo RF Probe Bias Network High Pass Filter FET Probe 51 Microscope is positioned above the platform and is used primarily for probe positioning. Figure 3.4 is a photograph of the breadboard mounting platform. The platform is easily configured to also accommodate on silicon probing, DC probing and device characterization, and 2 port VNA measurements using RF probes. Figure 3.4: Photographs of the breadboard probing station Three power supply units are mounted near the probe station to provide power to the two amplifiers and the DUT. A Keithley model 6487 picoammeter is connected to the power supply through the current return path of the DUT for current measurements. The picoammeter is capable of measuring average currents as small as 2 nA. There are two FET oscilloscope probes used to take measurements on the output, and the input though the bias network. The two probes available are the Tektronix P7240 active probe and the Tektronix P7504 tri-mode probe. Both probes introduce a load capacitance of approximately 0.9 pF and have a measurement bandwidth of 4 GHz. The P7240 is connected to the bias network and used to measure the input signal. The P7504 is provided with connections that are made to DUT P7504 tri-mode oscilloscope probe 52 solder directly to the measurement point on a printed circuit board. The solder connections are designed to keep the probe head as close as possible to the measuring point while greatly reducing any excess parasitic inductance introduced to the circuit. The P7504 probe can be seen in the photographs in figure 3.4. The probes feed buffered signals to the inputs of a Tektronix model DPO 71254 digital oscilloscope for time domain signal measurements. The oscilloscope is capable of sample rates up 50 G/s. A photograph of the entire experimental apparatus is shown in figure 3.5. Figure 3.5: Photograph of the complete experimental setup 3.3 Printed Circuit Board Design The printed circuits boards (PCBs) used to mount the test IC's were custom designed using the commercial software PCB Artist. The design philosophy for the PCBs is to create realistic circuit boards designed as if the test circuit were going to 53 be used under normal operating conditions. This is done to incorporate realistic parasitic elements into the test measurements in order to account for their contribution to HPM effects. The board itself is standard FR4 with copper metal layers. The PCBs were laid out using common design conventions. One important convention is the use of a metal layer as the ground plane. All ground connections to the test chip occur through vias to a metal backplane to eliminate the problem of ground bounce, especially at frequencies above 1 GHz. The power connection to the circuit is made through a short trace from a SMA connection. A surface-mount capacitor is connected between the power trace and ground through a via located very close to the power pin connection on the chip. This is a local by-pass capacitor that provides transient current to the circuit during a change in state. The value of the capacitance used on all the test circuits is 0.1 ?F. The signal traces are 0.6 mm wide and trace lengths range from 1 cm to 3 cm. At the end of each trace is a GSG probe pad with a 1 mm pitch to match the Cascade RF probes. The input traces also have a surface mount 10 k? pull down resistor attached in parallel to prevent an input that is not being probed from floating. The traces themselves are not designed to be match to 50 ?. When the circuit is operating at normal frequencies, the wavelength is many times the length of the circuit traces and matching is not required. A photograph of a test board is shown in figure 3.6. 54 Figure 3.6: Photograph of a test PCB design for a chip containing the JK flip flop and the 4 bit counter Throughout the entire test setup, great care was taken to eliminate and minimize any impedance introduced to the measurements by the apparatus. One of the greatest areas of concern was the power leads from the power supply to the DUT. The by-pass capacitor should eliminate much of this concern; however, to ensure measurements were not overly influenced by these impedances, a battery attachment was made for use on the DUT. No current measurements could be made with this attachment, so the battery was used as a means to verify that the input and output behavior is a result of legitimate circuit dynamics and not caused by unrealistic power line impedances. A photograph of the battery attachment is shown in figure 3.7. Figure 3.7: Battery attachment for the DUT By-pass capacitor Input GSG pad Chip ground connection Power connection Pull down resistor DUT 55 3.4 Experimental Methods 3.4.1 Instrument Control and Data Acquisition All of the electronic instruments described above are connect to a central control computer through a GPIB bus. The front panel control of each instrument was managed using Agilent VEE pro software. VEE pro is a graphical based programming language intended for external instrument control. Functional blocks that serve specific tasks such as a loop counter, instrument control, or output display are connected to each other through flow control and data wires. The routine is designed by attaching the appropriate wires to the terminals of each of these blocks in order to perform a desired task. The basic programming blocks are essentially visual forms of common programming languages such as C and C++. Instrument control blocks communicate though the GPIB bus using the command language specific to that instrument. An example VEE program is shown in figure 3.8. The VEE programs control the flow of the experimental measurements by incrementing frequency and output power, recording data from the instruments, and saving data to comma- delimited text files. 56 Figure 3.8: Example program written in Agilent VEE Pro. 3.4.2 Measurement Procedure This sub-section describes the experimental measurement procedure used for the vast majority of data presented in this work. The experimental measurements begin with the injection signal generated by the RF source, which is directed into the test circuit input trace. A pulsed modulated signal is always used to prevent thermal effects in the DUT. The modulation pulse width was typically set between 3 and 10 ?s and the repetition period was 100 ?s to keep the duty factor low. The carrier frequency and power were stepped in increments of 5 MHz and 0.5 dBm from 0.1 GHz to 4 GHz and -20 to 20 dBm, respectively, and the digitized waveforms were recorded at each drive setting. The typical frequency increments were as follows: 100 MHz, 200 MHz, 400 MHz, 600 MHz, and 800 MHz on the low frequency amplifier and 1 GHz to 4 GHz in steps of 500 MHz on the high frequency amplifier. The experimental range was chosen based on observations made in previous HPM studies [5, 38, 40, 42]. Programming blocks Instrument control block File I/O block 57 The pulse modulation envelope is fed out to synchronize both the oscilloscope and the picoammeter. The picoammeter was triggered so that the current measurement coincided with the injected RF pulse. The instrument can be set to integrate an integer multiple or a fraction of a power line cycle period (~16 ms). An appropriate line cycle fraction was chosen to integrate over as much of the RF pulse as possible. The oscilloscope recorded input and output voltage waveforms for each power and frequency setting for a given experiment. The sample rate was set to 25 Gs/s in order to record some of the higher harmonics generated by nonlinear effects in the circuits. The data was written to a text file along with the appropriate frequency and output power information. Record lengths of the waveforms were typically 200000 points. 58 Chapter 4 : Input Analysis and ESD-HPM Interaction 4.1 Introduction The following chapter presents experimental measurements performed to characterize the nonlinear response of ESD protection devices when excited by large voltage amplitudes associated with HPM signals. How ESD circuits respond to high- frequency large-signal excitation is an important aspect of HPM effects, since they are found in virtually all modern integrated circuits. When HPM signals interact with the ESD devices the primary effect observed is an increase in the average DC voltage level at the input [42]. The shift in the DC voltage at the input of the CMOS test circuits on its own has been shown to be a source of logical bit errors depending on whether or not the severity of the DC shift rises above the noise margin[42]. However, the response of these devices may also be responsible for other effects observed in commercial devices [38]. If these and a host of other complex effects are just consequences of ESD response then circuit models and simulations can be formulated based on a simple mechanism. 4.2 Theoretical Background ? PN Junction Transient Analysis The primary device of interest in the ESD protection circuits is the diode created by the drain body PN junction of the gate grounded (ggNMOS) and the gate grounded (ggPMOS), which is shown in Figure 4.1. 59 Figure 4.1: Drain body PN junction for a ggNMOS To develop an understanding of how the diode behaves when excited by large signals it is important to evaluate how the PN junction behaves as the terminal voltage swings from a forward bias condition to a reverse bias condition. The quasi-static approximation for a diode assumes that the carriers within the junction redistribute in a time that is short compared to transients in applied voltage [51]. In other words, the approximation assumes that the junction potential follows the applied voltage perfectly as the applied voltage transitions from forward to reverse bias levels. Under these conditions a sinusoidal waveform produces an ideal half wave rectified voltage drop across the diode junction. If the applied voltage transitions very rapidly from forward to reverse bias, the quasi-static approximation begins to break down and the time it takes for the junction voltage to reach steady state reverse bias must be considered. This is referred to as non-quasistatic (NQS) regime of operation and the transition from forward bias to reverse bias is referred to as the reverse recovery time [51-53]. For the case of high frequency sinusoidal excitations under NQS conditions, the signal is not rectified in the ideal sense as described above. However, as with any nonlinear circuit element, a 60 DC component will continue to be generated until the frequency is high enough that the change in junction voltage from its forward bias state is negligible. Useful insight into the operation of the drain body diode under large signal high frequency excitation can be developed from theory by using some of the typical analytical approximations established by the basic semiconductor physics. The following analysis will focus on the dynamics of the transient response of the PN junction as the applied voltage shifts abruptly from forward bias to reverse bias. 4.2.1 Linear Approximations and Initial Steady State The dynamic behavior of the PN junction is best understood in terms of the minority carrier concentrations and how those concentrations change versus time as a junction is driven from forward bias to reverse bias. In forward bias, either side of the PN junction is flooded with minority carriers and the diffusion of minority carriers at the junction boundary accounts for the forward bias diode current. For the purpose of this analysis, it is sufficient to assume a planar abrupt PN junction. Under this assumption the depletion region is devoid of any mobile carriers and consists only of fixed ion charges. This is often referred to as the depletion approximation[51-53]. Consider the ggNMOS device shown in figure 4.1. In the process technology used for the test circuits created for this study, the n+ source region is degeneratively doped with impurity concentrations on the order N d ? 10 20 per cm 3 and the p-type bulk has a doping concentration of approximately N a ? 10 16 per cm 3 [43]. As a result the conductivity of the n+ region is much great than the p-type substrate. Therefore, for the case of forward bias, the minority carrier concentration in the n+ region is negligible and the depletion region is located almost entirely in the p-type bulk 61 region. The minority carriers in the n+ region can be neglected, which simplifies the analysis. The source ground contact for the ggNMOS is 0.9?m and is much shorter than the diffusion length of minority electrons in the p-type bulk, which is on the order of 10?m [52]. Since the ground contact is such a short distance from the PN junction, it is appropriate to apply the short-base diode approximation. The excess minority electron concentration in the steady state forward bias condition for a short base diode is described by equation (4.1) [52]. 0 () ( 1)(1 ) a qV p kT pp B x x nx n e W + =?? (4.1) where W B is the distance from the junction boundary to the source contact, k is the Boltzmann constant, T is the temperature in Kelvin, x p is the location of the depletion region edge with respect the junction boundary, ? i is the built in potential of the junction, V a is the applied voltage, and n p0 is the steady zero bias minority carrier concentration defined as, 0 i q kT pd nNe ?? = (4.2) The current at the junction boundary is entirely due to minority carrier diffusion. Since the minority carrier concentration in the n+ region is neglected, the total current density for steady state forward bias can be calculated by solving the steady state diffusion equation (eq. 4.3) at the depletion boundary, with the minority carrier concentration at the boundary described by equation (4.4) [51-53]. 0 () p tn x dn x JqD dx = =? (4.3) 0 (0) ( 1) a qV kT pp nne= ? (4.4) 62 Figure 2 shows the single-sided junction and illustrates the minority carrier concentration of the p-type region in steady state forward bias. Figure 4.2: One sided step junction in steady state forward bias The reverse bias condition of a PN junction occurs when the voltage drop across the depletion region is nearly equal to the applied voltage. Under these conditions, the depletion region expands, the concentration of excess minority carriers drastically decreases, and almost no current flows though the diode (there is always a degree of reverse current due to generation in the depletion region but this is ignored under the depletion approximation) [51-53]. This is in contrast to the forward bias condition, in which very little voltage is dropped across the depletion region and there is, relatively speaking, a large amount of excess minority carriers. The change in minority carriers does not happen instantaneously and evaluating the transient behavior of the minority carriers is the key to understanding the reverse recovery process. 0 () ( 1)(1 ) a qV p kT pp B x x nx n e W + =?? contact 63 4.2.2 Reverse Recovery Transient Once the applied voltage switches to from forward bias to reverse bias the excess minority carriers transit away from the junction boundary until they recombine and are effectively removed from the bulk. The time it takes for the excess carriers to recombine can be broken into two phases. During the first phase, excess minority carriers at the junction boundary maintain the gradient necessary to allow current to flow through the device. Immediately after switching, a reverse current will flow through the diode limited only by the impedance of the external circuit. This current will flow until the all the excess minority carriers have diffused away from the junction boundary. During this period the junction voltage changes by a very small amount. This phase is commonly referred to as the storage phase. The second phase is defined by the time needed to evacuate the remainder of the stored excess minority carriers. During this phase the reverse current will decay because the minority carrier gradient at the boundary is no longer present to maintain the reverse current. As the current decays the junction potential approaches the applied bias potential until the steady state reverse bias is reached. Figure 4.3 illustrates the behavior of the reverse current versus time. The length of time that defines the second phase or recovery phase is determined by the point at which the reverse current reaches 10% of its initial value. The reverse recovery time is defined as t rr = t1 + t2. 64 Figure 4.3: Reverse current vs time. t1 is the length of time for the storage phase and t2 is the time of the recovery phase defined by the point at which the reverse current reaches 10% of its initial value. The junction potential during the reverse recovery process is defined by the following expressions: ? 0t = junction fb VV= (4.5) ? 01tt<< 0 (0, ) ln p junction p nt kT V qn = (4.6) ? 1tt? junction bias kT VV q