ABSTRACT Title of dissertation: INTEGRATED CMOS CAPACITANCE SENSOR AND MICROACTUATOR CONTROL CIRCUITS FOR ON-CHIP CELL MONITORING Somashekar Bangalore Prakash Doctor of Philosophy, 2008 Dissertation directed by: Professor Pamela Abshire Department of Electrical and Computer Engineering \Cell Clinics," CMOS/MEMS hybrid microsystems for on-chip investigation of biological cells, are currently being engineered for a broad spectrum of appli- cations including olfactory sensing, pathogen detection, cytotoxicity screening and biocompatibility characterization. In support of this efiort, this research makes two primary contributions towards designing the cell-based lab-on-a-chip systems. Firstly it develops CMOS capacitance sensors for characterizing cell-related properties including cell-surface attachment, cell health and growth. Assessing these properties is crucial to all kinds of cell applications. The CMOS sensors measure substrate coupling capacitances of anchorage-dependent cells cultured on-chip in a standard in vitro environment. The biophysical phenomenon underlying the ca- pacitive behavior of cells is the counterionic polarization around the insulating cell bodies when exposed to weak, low frequency electric flelds. The measured capaci- tance depends on a variety of factors related to the cell, its growth environment and the supporting substrate. These include membrane integrity, morphology, adhesion strength and substrate proximity. The demonstrated integrated cell sensing tech- nique is non-invasive, easy-to-use and ofiers the unique advantage of automated real time cell monitoring without the need for disruptive external forces or biochemical labeling. On top of the silicon-based cell sensing platform, the cell clinics microsystem comprisesMEMSstructuresforminganarrayofliddedmicrovialsforconflningsingle cells or small cell groups within controllable microenvironments in close proximity to the sensor sites. The opening and closing of the microvial lids are controlled by actuator hinges employing an electroactive polymer material that can electro- chemically actuate. In macro-scale setups such electrochemical actuation reactions are controlled by an electronic instrument called potentiostat. In order to enable system miniaturization and enhance portability of cell clinics, this research makes its second contribution by implementing and demonstrating a CMOS potentiostat module for in situ control of the MEMS actuators. The original contributions of this dissertation include: ? First generation single electrode capacitance sensors based on charge shar- ing for establishing proof of concept for the on-chip cell sensing approach. Demonstration of novel cell sensing applications including cell adhesion char- acterization, viability monitoring and proliferation tracking. ? Second generation fully-difierential rail-to-rail capacitance sensors with on- chip gain tuning capability for achieving improved performance in terms of higher sensitivity, capacitance resolution, dynamic range and noise immunity. Shielded current routing bus architectures for incorporating the capacitance measurement circuit in high density sensor arrays and conserving individual sensor performance. Mismatch compensation and sensor output ofiset cance- lation by employing in-circuit oating gate trimming. ? An integrated CMOS potentiostat module custom designed for in situ control of the microactuators housed in cell clinics. Demonstration of potentiostat operation for control of ofi-chip and on-chip electroactive polymer-based mi- croactuators. INTEGRATED CMOS CAPACITANCE SENSOR AND MICROACTUATOR CONTROL CIRCUITS FOR ON-CHIP CELL MONITORING by Somashekar Bangalore Prakash Dissertation submitted to the Faculty of the Graduate School of the University of Maryland, College Park in partial fulflllment of the requirements for the degree of Doctor of Philosophy 2008 Advisory Committee: Professor Pamela Abshire, Chair/Advisor Professor Elisabeth Smela Professor Keith Herold Professor Martin Peckerar Professor Romel Gomez c Copyright by Somashekar Bangalore Prakash 2008 Dedication To my parents, grandparents and everyone in my family! ii Acknowledgments I would like to express my sincere gratitude to everyone who has made this dissertation possible and because of whom my doctoral research has been a great learning experience. Firstly I thank my advisor, Dr. Pamela Abshire for her uncompromising sup- port as an intellectual guide and an excellent resource provider during the entire course of my graduate research. I thank her for providing me this invaluable op- portunity to work on an extremely interesting and challenging project that is right at the interface of engineering and science. I thank my previous advisor Dr. Ralph Etienne-Cummings for having introduced me to this very exciting research area, and for his constant support and encouragement all these years. I thank my co-advisor Dr. Elisabeth Smela for her enlightening guidance that enabled me to overcome several hurdles during the execution of this multidisciplinary project. It has been a great pleasure to work with all of them. I thank my dissertation committee comprising Dr. Pamela Abshire, Dr. Mar- tin Peckerar, Dr. Romel Gomez, Dr. Elisabeth Smela and Dr. Keith Herold for the various technical discussions, for agreeing to serve on my dissertation committee and for sparing their precious time reviewing this manuscript. I also thank Dr. Marc Cohen for ofiering me many helpful suggestions during the course of my research. I would like to acknowledge the help and support from several of my colleagues at the Integrated Biomorphic Information Systems Laboratory and the Laboratory for Microtechnologies. Nicole Nelson, Honghao Ji, Mario Urdaneta, Marc Christo- iii phersen and Marc Dandin deserve a special mention for their signiflcant contribu- tions towards the success of this project. Without their expertise in areas including cell culture, IC testing, biocompatible chip packaging and electrochemistry, this dis- sertation could not have been realized. I thank all my other lab mates including Makeswaran Loganathan, Suvarcha Malhotra, Yanyi Wong, Peng Xu, Yiming Zhai, David Sander, Alfred Haas, Timir Datta, Anshu Sarje and Babak Nouri for all the fruitful and fun-fllled interactions that we had while working together at the IBIS lab. I also thank the undergraduate students including Joel Van Sickel, Victor Jeng, Eric Chen, Harneet Khurana and Armstard Skipwith for their individual contribu- tions through the summer projects. I wish all of them the very best in all their future endeavors. I would also like to thank all the stafi members including Peg Jayant and Carlos Luceno for computer/IT support, Jay Renner for serving as the MOSIS point of contact, Shyam Mehrotra for lab equipment, Beverly Dennis for lab facilities and the ECE business o?ce for taking care of all the lab purchases. I am greatly indebted to my parents who have always loved and cared for me, stood by me and guided me through the difierent phases of my life. There are not enough words to express my gratitude towards them. I would also like to thank my grandparents, uncles, aunts and cousins for all the love and support I have always received from them. I thank all my dear friends including Narayanan, Ashok, Shyam, Prasanth, Rengarajan, Adarsh, Abhirami, Lavanya, Vijayakala, Buvaneswari, Kavitha, Sid- dharth, Datta, Shiv, Gaurav and many others for making my graduate school ex- iv perience at College Park an enjoyable and memorable one. I would like to acknowledge flnancial support from the National Science Foun- dation (NSF) and the Laboratory for Physical Sciences (LPS), for all the projects that I have been a part of at the IBIS lab. I thank MOSIS service for providing chip fabrication through their educational programme. I thank the University of Mary- land Bioprocess Scale-Up Facility (BSF) and Dr. Sameer Shah for being generous in providing cell culture facilities. I also thank Dr. Anjan Nan and Dr. Hamid Ghandehari for providing technical assistance with cell culture. There are several others who have directly or indirectly contributed to this work, the names of whom are not mentioned here. I would like to thank all of them for all their contributions. Finally, I thank God for everything! v Table of Contents List of Tables ix List of Figures x 1 Introduction 1 1.1 Cell clinics overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Integrated electronic sensing of biological cells . . . . . . . . . . . . . 2 1.3 Research contributions . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1 Design and characterization of CMOS-only capacitance sen- sors for on-chip cell monitoring . . . . . . . . . . . . . . . . . 4 1.3.2 Design and demonstration of a CMOS potentiostat for control of integrated MEMS actuators . . . . . . . . . . . . . . . . . . 6 I Integrated Capacitance Sensing for On-Chip Cell Monitoring 8 2 Capacitance Sensing Using CMOS Technology 9 2.1 Sensor basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 A review on CMOS capacitance sensors . . . . . . . . . . . . . . . . 13 2.2.1 Amplitude based capacitance measurement . . . . . . . . . . . 15 2.2.2 Frequency based capacitance measurement . . . . . . . . . . . 15 2.2.3 Time based capacitance measurement . . . . . . . . . . . . . . 17 2.2.4 Charge based capacitance measurement . . . . . . . . . . . . . 19 2.2.4.1 Fingerprint sensing . . . . . . . . . . . . . . . . . . . 20 2.2.4.2 Interconnect capacitance characterization . . . . . . 21 2.2.4.3 Particle detection . . . . . . . . . . . . . . . . . . . . 23 3 Cell Adhesion, Viability, Proliferation, Techniques & Biophysics 25 3.1 Characterizing cell adhesion . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 Assessing cell viability . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3 Assessing cell proliferation . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4 Previous efiorts towards characterizing cell-related properties using electronic sensing techniques . . . . . . . . . . . . . . . . . . . . . . 29 3.4.1 Electric cell-substrate impedance sensing (ECIS) . . . . . . . . 29 3.4.2 Micro uidic capacitance cytometry . . . . . . . . . . . . . . . 31 3.5 Our approach using integrated capacitance sensing . . . . . . . . . . 31 3.6 Biophysics of cell-substrate capacitance . . . . . . . . . . . . . . . . . 33 3.6.1 Correlating capacitance with cell-substrate interaction . . . . 34 4 First generation capacitance sensors for establishing proof of con- cept 37 4.1 Single electrode capacitance sensor: design and operation . . . . . . . 37 4.2 Sensed capacitance modeling . . . . . . . . . . . . . . . . . . . . . . . 39 vi 4.2.1 Cell layer capacitance Ccell . . . . . . . . . . . . . . . . . . . . 39 4.2.2 Passivation layer capacitance Cox . . . . . . . . . . . . . . . . 41 4.2.3 Interfacial capacitance Cint . . . . . . . . . . . . . . . . . . . . 42 4.2.4 Fringe capacitance Cf . . . . . . . . . . . . . . . . . . . . . . 42 4.2.5 Growth medium capacitance Cgm . . . . . . . . . . . . . . . . 43 4.2.6 Baseline capacitance Cbase . . . . . . . . . . . . . . . . . . . . 44 4.2.7 Efiective sensed capacitance Csensed . . . . . . . . . . . . . . . 45 4.3 Chip design, fabrication and bench testing . . . . . . . . . . . . . . . 48 4.4 Sensor resolution analysis . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5 In vitro experiments demonstrating sensor response to cell phenomena 53 4.5.1 Tracking cell adhesion . . . . . . . . . . . . . . . . . . . . . . 55 4.5.1.1 Experiment 1: Averaged sensor response to cell ad- hesion . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5.1.2 Experiment 2: Online tracking of cell adhesion . . . 57 4.5.2 Monitoring cell viability . . . . . . . . . . . . . . . . . . . . . 58 4.5.2.1 Experiment 1: Averaged sensor response to changes in cell viability and sensor response validation using Neutral Red . . . . . . . . . . . . . . . . . . . . . . . 58 4.5.2.2 Experiment 2: Online monitoring of cell viability and sensor response validation using Alamar Blue . . 60 4.5.2.3 Experiment 3: Long term monitoring of cell viability in a closed undisturbed environment . . . . . . . . . 63 4.5.3 Tracking cell proliferation . . . . . . . . . . . . . . . . . . . . 65 4.5.3.1 Experiment and results . . . . . . . . . . . . . . . . 65 4.5.3.2 Estimating cell doubling time . . . . . . . . . . . . . 71 4.5.4 Detecting cell detachment . . . . . . . . . . . . . . . . . . . . 74 4.5.5 Notes on experiments characterizing capacitance sensor re- sponse to cell phenomena . . . . . . . . . . . . . . . . . . . . 76 4.5.5.1 Repeatability, reusability and control experiments . . 76 4.5.5.2 Capacitance uctuations . . . . . . . . . . . . . . . . 78 4.5.5.3 In uence of biocompatible chip package on baseline capacitance . . . . . . . . . . . . . . . . . . . . . . . 79 4.6 A capacitance imager chip based on the flrst generation sensor . . . . 80 4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5 Second generation fully difierential rail-to-rail capacitance sensors for improved performance 84 5.1 Motivation for a fully difierential sensor . . . . . . . . . . . . . . . . . 84 5.2 Implementable capacitance compensation schemes . . . . . . . . . . . 86 5.2.1 Stray capacitance compensation scheme . . . . . . . . . . . . 86 5.2.2 Standing capacitance compensation scheme . . . . . . . . . . . 87 5.2.3 Standing capacitance overcompensation scheme . . . . . . . . 88 5.3 Fully difierential rail-to-rail capacitance sensor: design and operation 89 5.4 Shielded current routing bus architectures for implementing difieren- tial capacitance sensor arrays . . . . . . . . . . . . . . . . . . . . . . 93 vii 5.5 Test chip version 1: Individual sensor characterization . . . . . . . . . 99 5.5.1 Sensor design and simulation . . . . . . . . . . . . . . . . . . 99 5.5.2 Chip fabrication and testing . . . . . . . . . . . . . . . . . . . 101 5.6 Test chip version 2: Sensor array and shielded current bus testing . . 104 5.6.1 Chip design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.6.2 Chip fabrication and testing . . . . . . . . . . . . . . . . . . . 105 5.7 Test chip version 3: Capacitance sensor incorporating oating gate trimming for mismatch compensation . . . . . . . . . . . . . . . . . . 111 5.7.1 Sensor circuit design incorporating oating gate transistors . . 114 5.7.2 Chip fabrication and testing . . . . . . . . . . . . . . . . . . . 118 5.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6 Conclusions: Part I 126 II A CMOS Potentiostat for Control of Integrated MEMS Actuators129 7 Research Background 130 7.1 First generation cell clinics . . . . . . . . . . . . . . . . . . . . . . . . 130 7.1.1 Cell clinics microstructure: conflguration and operation . . . . 131 7.1.2 Prototype testing . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.2 Potentiostat basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2.1 Electrochemical cell . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2.2 Potentiostat instrument . . . . . . . . . . . . . . . . . . . . . 135 8 Integrated Potentiostat Design 136 8.1 Implemented potentiostat architecture . . . . . . . . . . . . . . . . . 137 8.2 Wide swing op-amp design for microactuator control . . . . . . . . . 139 8.3 Potentiostat test chip . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9 CMOS/MEMS Integration & Testing 144 9.1 Validating potentiostat operation by cycling an ofi-chip PPy(DBS) fllm in a standard electrochemical cell . . . . . . . . . . . . . . . . . . 144 9.2 Potentiostat testing for control of an ofi-chip array of PPy(DBS)/Au lidded microactuators in a standard electrochemical cell . . . . . . . 146 9.3 Demonstrating in situ control of on-chip PPy(DBS)/Au lidless mi- croactuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.3.1 Chip postprocessing . . . . . . . . . . . . . . . . . . . . . . . 148 9.3.2 Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.3.3 In situ PPy(DBS) actuation . . . . . . . . . . . . . . . . . . . 150 9.3.4 In situ PPy(DBS) deposition . . . . . . . . . . . . . . . . . . 152 9.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 10 Conclusions: Part II 154 Bibliography 156 viii List of Tables 2.1 Integrated capacitance sensing approaches using CMOS circuits . . . 14 4.1 Initiation time Ti, duration time Td, and overall change ?C values obtained from sensed capacitance plots for all 16 monitored sensors across the three sensor groups. Cell loading performed at t = 0 hr. . . 68 4.2 Capacitance drop values ?Cdrop recorded by the three sensor groups after trypsinization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3 Standard deviations of capacitance uctuations . . . . . . . . . . . . 79 5.1 Summary of the difierential input capacitances corresponding to the 16 test structures in every column. . . . . . . . . . . . . . . . . . . . 106 5.2 Difierential input capacitance values corresponding to test structures 13 to 16 as estimated from measurement results. . . . . . . . . . . . 124 8.1 Performance metrics of the operational amplifler . . . . . . . . . . . . 142 ix List of Figures 1.1 Conceptual visualization of the cell clinics microsystem (flgure cour- tesy of Dr. E. Smela, Dr. P. Abshire and M. Urdaneta). . . . . . . . . 1 2.1 (a)Parallel plate capacitor (b)coplanar plate capacitor creating fring- ing electric fleld. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Generic capacitance sensor conflguration. . . . . . . . . . . . . . . . . 13 2.3 Capacitance measurement using synchronous demodulation. . . . . . 15 2.4 Capacitance measurement using oscillator circuit. . . . . . . . . . . . 16 2.5 Capacitance measurement using pulse width modulation. . . . . . . . 18 2.6 (a)Feedback capacitive sensing scheme. (b)Implemented sensor circuit. 21 2.7 Left, capacitance measurement test structure. Right, nonoverlapping switching waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.8 CBCM circuit for particle detection. . . . . . . . . . . . . . . . . . . 24 3.1 A schematic of the ECIS system. . . . . . . . . . . . . . . . . . . . . 30 3.2 Schematic of the micro uidic device for capacitance cytometry. . . . . 31 3.3 Cellular counterionic polarization in the presence of external electric flelds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 Cell dielectric layer formation in the presence of weak, low-frequency electric flelds: sedimentation phase (top), initiation of adhesion (mid- dle), adhesion and proliferation phases (bottom). . . . . . . . . . . . 35 4.1 Cell-substrate capacitance sensor: design and operation. . . . . . . . 38 4.2 Models of sensed capacitance during the difierent phases of the in- teraction process between cells and substrate: (a)pre-adhesion phase, (b)post-adhesion phase. . . . . . . . . . . . . . . . . . . . . . . . . . . 40 x 4.3 (a) Photomicrograph of the fabricated sensors showing the three sen- sor groups with sensing electrode areas: 20?20 ?m2, 30?30 ?m2 and 40?40 ?m2. (b) Photograph of a biocompatibly packaged ca- pacitance sensor chip. (c) Photomicrograph of MDA-MB-231 human breast cancer cells cultured in vitro on top of a capacitance sensor chip. 49 4.4 Variation of the sensor voltages with electrode distance. . . . . . . . . 50 4.5 Sensor distance resolution as a function of object proximity. . . . . . 52 4.6 (a)Photographofacellloadedchipmountedonthetestboard. (b)Photograph of the data acquisition setup. . . . . . . . . . . . . . . . . . . . . . . 54 4.7 Averaged sensor response to cell adhesion. The data points show the average output voltage difierences and standard deviation values across the sensors in each of the three groups. The horizontal lines plotted are the average sensor recordings with the chip exposed to growth medium alone before the sensor well was loaded with cells and have been plotted here across the time frame for comparing with the averaged sensed capacitances that were recorded in response to cell adhesion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.8 Online tracking of cell adhesion process by six 40?40 ?m2 sensors. . . 57 4.9 Averaged sensor response to changes in cell viability. . . . . . . . . . 59 4.10 Online monitoring of cell viability with concurrent measurements us- ing Alamar Blue dye. Alamar Blue % reduction values obtained from spectrophotometric analysis are shown above the times corresponding to extraction of the microsample. . . . . . . . . . . . . . . . . . . . . 61 4.11 Long term measurement of cell capacitance with cells monitored in a closed undisturbed environment for a period of four days. . . . . . . . 64 4.12 Sample capacitance plots showing sensor response to MDA-MB-231 cell adhesion; sensors a and b have a sensing electrode area of 30?30 ?m2; sensors c and d have a sensing electrode area of 20?20 ?m2. . . 67 4.13 Sample capacitance plots showing sensor response to MDA-MB-231 cell proliferation. The 10 squares in each panel display the relative locations of the 10 40?40 ?m2 sensors. The term \pre-proliferation phase" refers to the period before cell proliferation during which the sensors were not coupled to any cells. . . . . . . . . . . . . . . . . . . 70 4.14 A plot of cumulative number of sensors that recorded capacitance increase(CS)vs. incubationtime. Atotalof16sensorsweremonitored. 72 xi 4.15 Sample capacitance plots showing sensor response to MDA-MB-231 cell detachment upon trypsinization; sensors b and 5 correspond to the same 2 sensors referred to in Figs. 4.12 and 4.13 respectively. . . 75 4.16 Capacitance sensor response to adhesion of human colonic adenocar- cinoma cells (Caco-2) on the chip surface. All sensors measure 30?30 ?m2. Cell density employed for the experiment ? 1?106 cells/mL. . . 76 4.17 Capacitance sensor response with sensor well loaded with growth medium alone, without any cells. Sensors 1 and 2 measure 40?40 ?m2, sensors 3 and 4 measure 30?30 ?m2, sensors 5 and 6 measure 20?20 ?m2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.18 Photograph of the fabricated capacitance imager chip. . . . . . . . . . 80 4.19 (a) Schematic of the Correlated Double Sampling (CDS) unit shared by a column of sensor pixels. (b) Timing diagram showing the control signals for sensing and readout. The signals reset and reset are the same as shown in Fig. 4.1 that control the sensor operation. . . . . . 81 4.20 Imager output representing the capacitance proflle of a metal probe placed in contact with the chip surface. . . . . . . . . . . . . . . . . . 82 5.1 Fully difierential sensor block diagram and associated capacitances. . 85 5.2 Implementable capacitance compensation schemes: (a) stray capaci- tance compensation scheme, (b) standing capacitance compensation scheme and (c) standing capacitance overcompensation scheme. . . . 87 5.3 Fully difierential rail-to-rail capacitance measurement circuit design with sensor conflgured for standing capacitance compensation. . . . . 90 5.4 Timing diagram illustrating the relation between the clock phases and sensor outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.5 A fully difierential capacitance sensor array with a column parallel architecture based on a shielded current routing bus. (b) Schematic of the sensor pixel. (c) Timing diagram for pixel readout. (d) Horizontal view of the shielded current bus. . . . . . . . . . . . . . . . . . . . . . 95 5.6 A fully difierential capacitance sensor array with a single SEM archi- tecture based on a shielded current routing bus. (b) Schematic of the sensor pixel. (c) Timing diagram for pixel readout. (d) Horizontal view of the shielded current bus. . . . . . . . . . . . . . . . . . . . . . 98 5.7 The custom wide-swing op-amp used for bufiering the sensor output. 99 xii 5.8 (a) Simulated transient response of the difierential sensor for ?Ci between 0 and 20 fF. (b) Simulated sensor static response curves with corresponding calibration curves for Tint = 60 ns and 195 ns. . . 100 5.9 Chip photomicrographs showing (a) a test structure with stray ca- pacitance compensation for measuring the standing capacitance of a metal3 electrode, (b) a test structure overcompensating for the stand- ing capacitance of an interdigitated metal3 (top-most layer) electrode using an interdigitated metal1 (bottom-most layer) electrode. . . . . . 102 5.10 Test results showing the mean and standard deviations of the mea- sured sensor output voltages in correspondence to the standing ca- pacitances of metal3 electrodes for the 5 test structures across the 5 chips. The inset shows the ouput noise levels as measured from one of the sensor chips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.11 A single stage rail-to-rail amplifler circuit comprising class-AB difier- ential cells employed for bufiering the sensor output. . . . . . . . . . 104 5.12 (a) Photograph of the fabricated difierential capacitance sensor test array employing column parallel shielded current bus lines. (b) Pho- tomicrograph of a single Sensor Evaluation Module (SEM). . . . . . . 105 5.13 Recorded transient responses from one of the fabricated capacitance measurement circuits. The numbers in the parenthesis correspond to the test structures listed in Table 5.1. . . . . . . . . . . . . . . . . . . 108 5.14 Measured transfer functions corresponding to the 8 SEMs from one of the test chips with sensor gain set to 200 mV/fF. . . . . . . . . . . 109 5.15 Averaged transfer functions across all the SEMs across all the 5 fabri- cated chips corresponding to sensor gains of 100, 150 and 200 mV/fF. The error bars indicate the spread in the sensor outputs due to process and device mismatch efiects. The insets display the mean ?(?Vo) and standard deviation (?Vo) values of the sensor outputs correspond- ing to test structure 7 (with ?Ci = 0 fF) as listed in Table 5.1. The dotted red lines are the linear calibration curves used to estimate the sensor gain values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.16 (a) Representing output ofiset current in a PMOS transistor as a gate ofiset voltage. (b) Conceptual illustration of a oating gate transistor. 112 xiii 5.17 Schematic of the oating gate capacitance measurement circuit with injection/tunneling (I/T) structures. Control signals employed in the I/T structures include: (a)sample, for synchronizing oating gate trimming process with sensing clock cycle, (b)I=T, for selecting be- tweeninjectionortunnelingprocesses, (c)PE?, forenablingthetrim- ming process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.18 Schematicshowingthedesignandoperationoftheinjection/tunneling (I/T) structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.19 Photomicrograph of the modifled version of the Sensor Evaluation Module incorporating the oating gate transistors and the I/T struc- tures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.20 Measured transfer functions from two of the test chips after oating gate trimming at the operating point corresponding to test structure 7.121 5.21 Averaged transfer functions across the 4 SEMs in each of the 5 chips after oating gate trimming. The error bars indicate the spread in the sensor outputs after programming. The insets display the mean ?(?Vo) and standard deviation (?Vo) values of the sensor outputs corresponding to test structure 7. The dotted red lines are the linear calibration curves employed to estimate the ?Ci values corresponding to structures 13 to 16. . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.1 (a) Schematic illustration of a lidded microvial with bilayer hinge. Dark layer represents PPy [Illustration based on an original flgure courtesy of Y. Liu and Dr. E. Smela]. (b) Photomicrograph of the fab- ricatedcellclinicsmicrovials[PhotomicrographscourtesyofDr.M.Christo- phersen and Dr. E. Smela]. . . . . . . . . . . . . . . . . . . . . . . . . 131 7.2 Prototypemicrostructures fabricated onacustom CMOS bioamplifler chip [Photographs courtesy of Y. Liu and Dr. E. Smela]. . . . . . . . 133 7.3 An illustration showing an electrochemical cell connected to a poten- tiostat instrument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.1 (a)A model for the interelectrode impedance. (b) Potentiostat circuit for integration with the microactuators. . . . . . . . . . . . . . . . . . 138 8.2 Rail-to-rail operational amplifler constituting the potentiostat. . . . . 141 xiv 8.3 (a) Photomicrograph of the fabricated chip comprising the poten- tiostat module integrated with the microelectrodes constituting the electrochemical cell. (b) Photograph of a fully packaged potentiostat test flxture after postprocessing. . . . . . . . . . . . . . . . . . . . . . 142 9.1 Color change observed during cycling of the PPy(DBS) fllm using the on-chip potentiostat [Photographs were captured along with M. Ur- daneta]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.2 Cyclic voltammograms obtained during electrochemicalcycling at100 mV/sec of a PPy(DBS) fllm using the on-chip potentiostat and an external potentiostat (EcoChemie pgstat30) [Cyclic voltammograms were recorded along with M. Urdaneta]. . . . . . . . . . . . . . . . . . 146 9.3 Photomicrographs of a portion of the actuated array of actuators [Photomicrographs and videos were captured by Dr. M. Christo- phersen]. Top, lids open (at ?1 V vs. Ag/AgCl) and bottom, lids closed (at 0 V vs. Ag/AgCl). . . . . . . . . . . . . . . . . . . . . . . 147 9.4 In situ cycling of PPy(DBS) fllms on gold-plated WEs using the on- chip potentiostat connected to an external waveform generator [Pho- tomicrographswerecapturedalongwithM.UrdanetaandDr.M.Christo- phersen]. Left, PPy(DBS) in the oxidized state. Right, PPy(DBS) in the reduced state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.5 Cyclic voltammograms recorded during in situ oxidation and reduc- tion of PPy(DBS) fllms [Cyclic voltammograms were recorded along with M. Urdaneta and Dr. M. Christophersen]. . . . . . . . . . . . . . 152 xv Chapter 1 Introduction 1.1 Cell clinics overview Integrated sensor and actuator systems can ofier versatile solutions for complex biosensing problems involving the acquisition of responses from individual cells. This lab-on-a-chip approach to cell biology has potential for enabling a wide spectrum of applications, including studies of speciflc biochemical mechanisms, fast medical diagnosis, pharmaceutical tests, and detection of biochemicals of military or envi- ronmental relevance [1{4]. vial CMOS chipcomprising sensors andsignal processingcircuitry microactuatorlid hinge cell sensingelectrodes cells Lab-on-a-chip Figure 1.1: Conceptual visualization of the cell clinics microsystem (flgure courtesy of Dr. E. Smela, Dr. P. Abshire and M. Urdaneta). 1 Motivated by its many potential applications, cell clinics, a CMOS/MEMS hy- brid microsystem for capturing and performing in-situ investigation of living cells, aims at providing an integrated, automated, and high-speed solution for cell mon- itoring applications. CMOS sensors are being developed for extracellular signal ampliflcation, cell-substrate capacitance sensing, contact imaging, and uorescence detection. The MEMS platform provides an array of lidded microvials for confln- ing living cells in close proximity to the CMOS sensors and isolating them within controllable microenvironments. Fig. 1.1 provides a conceptual illustration of the microsystem being developed. The biolab SoC (System-on-Chip) comprises elec- trodes, sensors, microstructures for isolating and containing living cells, and CMOS circuitry for on-chip signal conditioning of sensor responses to cells [5,6]. 1.2 Integrated electronic sensing of biological cells The electrical properties of biological cells and tissues have a strong correlation with their morphological and physiological states [7,8]. For example, the existence of the membrane potential is a feature that can be used to distinguish between living and non-living cells. In special cell types such as neurons and muscle cells, the time-varying electrical potential across the cell membrane re ects changes in the cellular environment and serves as a mechanism for both intra- and inter-cellular communication. Impedance measurements can be used to sense cell morphology and motion [9], to monitor cell adhesion and growth [10], to measure transepithelial and transendothelial electrical resistances of cultured cell monolayers [11], and also 2 to difierentiate between normal and abnormal cell types [12]. Miniaturized electronic biosensing techniques have many advantages to ofier in comparison to traditional biochemical detection approaches. Firstly, it is possi- ble for complex measurements to be minimally disruptive in that the responses of living cells can be monitored in real time without altering the biochemical compo- sition of the extracellular environment. This prevents unnecessary modiflcation of the in vitro cellular environment which can interfere with the analysis procedure and produce unintended side efiects. In addition, microfabrication technologies can readily produce sensing interfaces with physical dimensions matched to the living samples under study, including single cells or even subcellular structures [13]. This enables novel measurement methodologies with capability for exquisite sensitivity and spatial resolution. Electronic biosensing also ofiers the exibility of probing liv- ing samples over time scales varying over many orders of magnitude and tailored to the speciflc application. Further, lab-on-a-chip microsystems may provide versatile solutions to complex biosensing problems by automating the sensing and analy- sis procedures. Such automated, integrated systems ofier the potential to reduce infrastructure and cost requirements and, ultimately, to make such sophisticated measurements possible outside the conflnes of a cell biology laboratory. 3 1.3 Research contributions 1.3.1 Design and characterization of CMOS-only capacitance sensors for on-chip cell monitoring The primary contribution of this research involves development of CMOS-only capacitance sensors for on-chip cell sensing applications including characterizing cell adhesion, monitoring cell viability and tracking cell proliferation by sensing the ca- pacitive coupling between sensing electrodes and the cellular matrix. The proposed technique employs electrodes arranged in a planar conflguration within the substrate of the growth chamber and insulated from the growth medium using the passivation layer of the chip. The underlying biophysical phenomenon is that, on exposure to low frequency, low strength electric flelds, living cells in growth medium behave as insulating structures surrounded by ionic clouds compensating flxed charges present in their membranes [14]. An electric fleld polarizes the counterionic cloud, giving rise to electric dipoles which are the dominantfactor responsible for the low frequency ca- pacitive behavior of cells. Healthy cells with well formed plasma membranes sustain stronger electric dipoles than dead or unhealthy cells with compromised membrane structures, so the measured capacitance is higher for healthy cells [15,16]. In ad- dition, healthy cells adhere more tightly to a surface in comparison with dead or unhealthy cells, which results in stronger capacitive coupling between the cells and underlying electrodes. Both of these properties can be exploited to monitor the health and growth of cells, and also their interaction with substrates. 4 The proof of concept for the integrated capacitance sensing approach was es- tablished through the design of single electrode sensors that operated based on the charge sharing principle [17{21]. The sensors were tested on-bench and character- ized with living cells cultured on the chip surface. The sensors were demonstrated to track the cell adhesion and proliferation processes. Also promising correlations were obtained between the variations in sensed capacitance and changes in cell viabil- ity. In addition to delivering encouraging experimental results, the flrst generation sensors posed a set of problems related to parasitic capacitance efiects, interference noise coupling, limited output dynamic range and limited spatial resolution. In response to the above mentioned problems, a second generation fully difier- ential rail-to-rail capacitance measurement circuit was designed based on the charge based capacitance measurement (CBCM) technique [22,23]. The design extends pre- viously reported CBCM circuits with single-ended output conflgurations [24{27] to a difierential output architecture. The difierential sensor achieves improved perfor- mance by compensating for parasitic capacitances, by suppressing correlated noise and by providing a higher output dynamic range. Novel array architectures based on a shielded current routing bus were developed for incorporating the difierential capacitance measurement circuit in sensor arrays. Apart from improving sensor spa- tial resolution, the shielded current bus also conserves sensor evaluation speed and provides protection from junction leakage in large sensor arrays. The sensor employs a 3-phase clocking scheme for enabling on-chip gain tuning and also for limiting out- put voltage ofisets. The difierential sensor in combination with the shielded current bus exhibits a maximum sensitivity of 200 mV/fF, a maximum achievable resolution 5 of 15 aF and an output dynamic range of 65 dB. In addition to this, another novel difierential sensor circuit incorporating oating gate transistors for output ofiset can- celation was also designed and fabricated. Output ofiset cancelation was achieved using a combination of impact ionized channel hot electron injection and Fowler- Nordheim tunneling. Both versions of the difierential sensor circuits incorporated in test arrays using the shielded current routing bus were successfully fabricated and tested [28]. 1.3.2 Design and demonstration of a CMOS potentiostat for control of integrated MEMS actuators The microvial lids in the cell clinics microsystem are opened and closed using electrochemically controlled bilayer actuators. The actuators comprise an electroac- tive polymer layer in combination with a gold contact layer. The polymer layer has the property of changing volume due to electrochemical oxidation and reduction. At the macro-scale, such electrochemical reactions are controlled using an instrument known as a potentiostat. In the flrst generation of cell clinics the bilayer actuators were controlled using an external potentiostat instrument. In addition to developing the capacitance sensing platform for on-chip cell sensing, another contribution of the current research was to integrate the necessary potentiostat circuitry for control of and integration with the microactuators on top of the CMOS chip. This efiort has enabled miniaturization and enhanced portability of the cell clinics system. The potentiostat module was tailored in accordance with the driving require- 6 ments of the microactuators [29,30]. The design was optimized in terms of on-chip area requirements for the cell clinics application. A test chip comprising the control circuit connected to on-chip electrodes was designed and fabricated. The electrode set comprised: counter, reference and working electrodes, necessary for the opera- tion of the electrochemical actuators. Tests were performed for validating the control circuit for actuation of ofi-chip polymer fllms and lidded microactuators [29]. The operation of the integrated potentiostat was also successfully demonstrated for in situ actuation of lidless microactuators fabricated on top of the CMOS chip [30]. 7 Part I INTEGRATED CAPACITANCE SENSING FOR ON-CHIP CELL MONITORING 8 Chapter 2 Capacitance Sensing Using CMOS Technology Capacitance sensing involves (i) exposing an object or system under analysis to electric flelds, (ii) performing current, voltage or charge based measurements and (iii) computing the capacitance value of the given object or system from the measured data. The measured capacitance is a parameter that can be employed for a variety of applications involving detection of material properties, sensing location, proximity and motion of either conductive, dielectric or semi-insulating objects. The design and development of cell clinics, a cell-based lab-on-a-chip tech- nology, poses several requirements concerning manipulation of cells and sensing of difierent aspects of cell morphology, growth and physiology. From an electrical perspective the cellular environment is a complex heterogeneous system compris- ing ionic conductors and organic dielectrics. In addition to this the system also exhibits temporal changes due to cell activity (e.g., adhesion, proliferation, move- ment). Understanding the behavior of such complex systems requires extensive characterization through various biochemical and biophysical techniques. In this direction, capacitance sensing can serve as a useful technique for integrated sensing, characterization and monitoring of biological systems at the cellular level. Capacitance sensors have several inherent features that favor their utility in cell sensing. They can be tailored to perform non-contact sensing. This can be 9 an extremely critical requirement while sensing biological samples. These sensors generally operate at low power. Capacitance sensing being highly amenable to inte- gration enables array-based sensing. They also provide better temperature stability in comparison with piezoresistive and piezoelectric sensors, easier A/D conversion, better reliability and lower cost when batch fabricated. Capacitance sensing ofiers additional advantages in comparison to other cell sensing modalities such as opti- cal detection [31], uorescence sensing [32] and frequency based measurements [33]. These include reduced system complexity, elimination of ofi-chip optics, no post- fabrication requirements, and prevention of electrochemical side-efiects which are prominent in electrode based sensors with sensing surfaces exposed directly to the cell medium. One of the flrst efiorts towards sensing microscopic cell capacitances employed micro uidic ow cytometry, with measurements performed using an external ca- pacitance bridge [34]. Capacitance changes in the fF range were evoked by pass- ing individual cells through a 1 kHz electric fleld across a pair of microelectrodes. Another lab-on-a-chip system employed capacitance sensing in combination with dielectrophoretic actuation for short-term cell detection and manipulation, with the cells suspended in a microchamber and the capacitances measured in between the on-chip microelectrodes and an external conductive glass lid [35]. Detection and manipulation were performed in a modifled in vitro environment using mannitol instead of growth medium. An aqueous solution of 280 mM mannitol provided the low conductivity conditions required for detection and manipulation, and pre- served the osmotic pressure required for the cells to survive. This work, in contrast, 10 employs integrated capacitance sensors for long-term monitoring of anchorage de- pendent cells in a standard in vitro environment using normal cell growth medium. Since many living cells need to be attached to a solid surface before they can grow and proliferate, this approach can be applied for monitoring a wide spectrum of cell types. Through this research, we have demonstrated the utility of this technique for characterizing adhesion, monitoring viability and tracking proliferation of living cells cultured on the sensor chips [17{21]. This approach in contrast to previous efiorts does not require specialized 3D arrangement of electrodes and is well suited to monitoring cells in a standard cell culture environment by employing on-chip passivated coplanar microelectrodes. 2.1 Sensor basics The capacitance as seen by the sensor arises from the combination of a drive electrode, a sense electrode and the material under test (MUT). The electric fleld lines travel across the drive and sense electrodes, passing through the MUT. The measured capacitance is determined by the geometrical conflguration of the drive and sense electrodes, and the dielectric properties and spatial orientation of the MUT. A CMOS-only sensor, constrained by the planar nature of its fabrication process, is restricted to coplanar electrode conflgurations. Coplanar electrodes of- fer the additional advantage of one-sided access for biological sensing applications, leaving the other side open to the isolated and sterile biological environment. The electric fleld resulting from the excitation of coplanar electrodes is entirely fringing 11 (a) (b) Figure 2.1: (a)Parallel plate capacitor (b)coplanar plate capacitor creating fringing electric fleld. in contrast to a direct normal fleld inside an ideal parallel plate capacitor. Fig. 2.1 illustrates this distinguishing feature. The penetration depth of the fringing electric fleld above the coplanar electrodes is proportional to the spacing between the cen- terlines of the sense and drive electrodes. This is an important aspect to consider while designing sensors for biological samples (e.g., tissues, cells, microbes, proteins, DNA) whose dimensions scale across several orders of magnitude. Typical cellular dimensions being at the micron scale, are easily sensed by microelectronic sensors comprising integrated microelectrodes. Fig. 2.2 illustrates the equivalent circuit of the most basic capacitance sensor conflguration [36]. The flgure shows a parallel guard plane underlying the sense and drive electrodes. The drive electrode is connected to the excitation source. The sense electrode is connected to the measurement and signal processing circuitry. The interelectrode conductances G10, G20 and G12, the interelectrode capacitances C10, C20 and C12, and the input capacitance of the measurement circuit CL, comprise the impedance network excited by the source VS. The guard plane driven by a potential VG = VL, serves to nullify the impedance formed by G20 and C20. This eliminates their efiect on the circuit response and enhances sensitivity. 12 VS VL CL C10 G12 C20G10 C12 G20 substrate driveelectrode sense electrode guard electrode material undertest VG Figure 2.2: Generic capacitance sensor conflguration. 2.2 A review on CMOS capacitance sensors Integrated CMOS capacitance sensors have been previously employed for a variety of applications including flngerprint sensing [37], position sensing [38], inter- connect characterization [39], humidity sensing [40], and particle detection [27]. The goal of this research is to demonstrate the application of this technology for on-chip cell sensing applications including adhesion characterization, viability monitoring and proliferation tracking. Capacitance sensing techniques using CMOS technology can be broadly classifled under four categories: (i) amplitude based, (ii) frequency based, (iii) time based and (iv) charge based measurements. These techniques are discussed in the following sections. Table 2.1 gives a brief overview of each of these approaches. 13 Table 2.1: Integrated capacitance sensing approac hes using CMOS circuits Approac h: Amplitude Frequency Time Charge based based based based Transduction capacitance to capacitance to capacitance to capacitance to typ e: ac amplitude frequency pulse duration charge storage or motion Measuremen t sync hronous oscillators integrators switc hed circuit: demo dulators capacitors Adv an tages: ?precision ?precision ?precision ?small on-c hip ? exibilit y ?linearit y ?linearit y area (suitable ?noise ?noise for arra y-based imm unit y imm unit y applications)?lo w po wer Disadv an tages: ?high on-c hip ?high on-c hip ?high on-c hip ?sensitivit y or on-b oard area area to stra y area capacitances?lo w noise imm unit y Applications: position sensing, pro ximit ydetection, flngerprin tsensing, accelerometry ,pressure sensing, particle detection, humidit ysensing, pro cess con trol interconnectcharacterization 14 CS CR bandpass filter amplifier -1 lowpass filterVin Vout Figure 2.3: Capacitance measurement using synchronous demodulation. 2.2.1 Amplitude based capacitance measurement The amplitude based measurement approach involves excitation of a capacitive network comprising a reference capacitor CR and the sensed capacitance CS by a high frequency excitation signal (10kHz - 1MHz) followed by ampliflcation and synchronous demodulation of the capacitively modulated signal [41]. Fig. 2.3 shows a block diagram of a full-wave demodulation scheme, with both positive and negative half-cycles of signal contributing to the output. The bandpass fllter is added to limit the noise bandwidth. Commercially available high-quality ampliflers and fllters can be used for on-board implementation of the synchronous demodulator required to implement precise and low-noise capacitance measurements. 2.2.2 Frequency based capacitance measurement The frequency based approach involves translation of sensed capacitance val- ues to frequencies or digital pulses using oscillator circuits. In the oscillator based capacitance sensors, the sensed capacitor replaces the tuning element in the oscil- lator. Sensors comprising discrete components can employ RC or LC oscillators, where for an RC oscillator, the frequency is proportional to 1=RC and for an LC oscillator frequency is proportional to 1=pLC. Integrated oscillator circuits imple- 15 Vdd I I CS VC Vout comp1 comp2 Vtr- Vtr+ 1 0 s Figure 2.4: Capacitance measurement using oscillator circuit. mented in CMOS involve charging and discharging of the sensed capacitor using transistors acting as controlled current sources. For example, Ferri et al. designed an oscillator as a capacitive sensor interface mapping a capacitance range of 10 fF - 100 pF to a frequency span of 300 Hz - 3 MHz [42]. Fig. 2.4 shows the block diagram of the designed oscillator. The circuit comprises a hysteresis comparator and a current starved inverter in a loop. The sensed capacitor CS is charged and discharged with constant currents I from the current starved inverter. The hysteresis comparator comprises two traditional com- parators with difierent threshold voltages Vtr+ and Vtr?. The comparator converts the triangular voltage across CS into a square wave of output frequency: fosc = I2(V tr+ ?Vtr?) ? 1C S (2.1) The chip area was reported to be 0.2 mm2. Frequency measurement or pulse count- ing would require additional on-chip or ofi-chip circuitry. The frequency based technique ofiers a wide range of measurable capacitances. 16 Since the oscillators can be designed to produce digital outputs, the sensors can operate under noisy conditions. 2.2.3 Time based capacitance measurement This approach employs a linear relationship to map the sensed capacitance to the pulse width of the output signal. Based on this technique, Bruschi et al. designed a capacitance-to-pulse width converter that generates a pulse width mod- ulated (PWM) signal in accordance to the sensed capacitance [43]. Fig. 2.5 shows a schematic of the implemented system along with the relevant waveforms. The sensed capacitance is represented by the capacitance CS along with the parasitic capacitances CP1 and CP2. The measurement circuit comprises three in- tegrators INT1-3. The transconductance amplifler OTA2 has 2 identical, in-phase, current output ports. CMP is a comparator. CR and CI are reference capacitors. Currents IRMP, ISH and IDIS are obtained from precision current mirrors and are scaled according to: ISH = k1 IRMP; IDIS = k2 IRMP (2.2) k1 and k2 being scaling constants. When clock (CLK with period TCLK) is low, IRMP is integrated by INT1 resulting in a flnal output voltage of Vf, Vf = TCLK IRMP2C R (2.3) 17 CLKIRMP CR CLK INT1 INT2 INT3 GM GM OTA2 CS CP1 CP2 sensedcapacitance network VX VRMP I1 I2 ISH CLK IDIS VPW VPW CI VI CMP CLK VPW TPW CLK TCLK /2 TCLK tV X = VRMP VI t t VPWVImaxsignal waveforms GM Figure 2.5: Capacitance measurement using pulse width modulation. INT2 forms a negative feedback loop around OTA2. Since VRMP and VX track each other from 0 to Vf, Z TCLK=2 0 I2 dt = CS Vf = TCLK IRMP2 C S CR ? (2.4) Concurrently, the current I1 ? ISH is integrated by INT3. Assuming I1 = I2, the charge stored on CI, at the end of CLK low can be computed as QI = TCLK IRMP2 C S ?k1 CR CR ? (2.5) CMP output is high during the entire CLK low phase. When CLK goes high, I1?ISH is disconnected from INT3, and CI is discharged by IDIS. When VI = 0 after discharging, CMP output goes low and the discharge stops. From the above discussion, the PWM signal duration TPW can be evaluated 18 as: TPW = QII DIS = TCLK2k 2 C S CR ?k1 ? (2.6) TPW is proportional to CS. The ratio TPW=TCLK depends on the current ratio k1=k2 and the capacitance ratio CS=CR. The measurement circuit exhibits low sensitivity to temperature and process variations because these variations are largely canceled by the computation of the ratio. 2.2.4 Charge based capacitance measurement The approaches described above for capacitance measurement ofier several ad- vantages including high precision, good linearity, noise immunity, wide signal range and low temperature sensitivity. However, the measurement circuitry employs sev- eral signal processing or conditioning modules which increases their on-chip area. Since the sensor for the current application needs to be tailored for on-chip cell sensing, employing any of the above approaches would lead to very few sensing sites. In contrast to the above approaches, charge based techniques have proven to result in sensors having minimal on-chip footprints and resolution in the aF range. These factors have favored the adoption of the charge based capacitance measure- ment approach for the cell sensing application demonstrated here. Recently, charge based capacitance measuring circuits have been employed for several applications including flngerprint sensing, interconnect characterization of fabricated chips and particle detection. This section brie y reviews related architectures reported in the literature. 19 2.2.4.1 Fingerprint sensing Charged based capacitance sensor arrays have been used to sample flngerprint patterns by detecting the electric fleld variation induced by the skin surface. The sensing electrodes are covered by a dielectric material on top of which a flnger is placed. The presence of a flnger above the sensing electrode produces a capacitor. The ridge and valley patterns on the flngers translate to the capacitive patterns sensed across the array. Tartagni et al. designed a flngerprint sensor based on a feedback capacitive sensing scheme [44]. Fig. 2.6(a) illustrates the sensing technique. Each sensor cell comprises two coplanar plates interacting with the overlying flnger surface. This is shown in the flgure as the feedback capacitance Cf connected across the amplifler input and output terminals. Cf is formed by the two coplanar electrodes facing a third electrode modeling the flnger surface. If the input capacitive node is discharged by a ?Q amount of charge, the output voltage ?Vo can be derived as: ?Vo = ?QC i Ao + 1+ 1A o ? Cf (2.7) where Ao is the gain of the charge amplifler OP. Cf can be approximated as: Cf ? ?0S2d (2.8) where S is the plate overlap area and d is the distance between the coplanar elec- trodes and the third electrode. If Ao 1, the output voltage signal ?Vo can be 20 + - Vo Cf Ci?Q d S Ac reset reset Cf VoCi (a) (b) Ac Figure 2.6: (a)Feedback capacitive sensing scheme. (b)Implemented sensor circuit. approximated as: ?Vo ? ?QC f = 2?Q? 0S d (2.9) The charge amplifler Ac is implemented as a high gain inverter as shown in 2.6(b). The sensing operation proceeds in two phases. During the reset phase, the charge amplifler is reset by shorting the input and output using the reset switch, so that the input and output are set to VT, the logical threshold of the inverter. During the evaluation phase, a voltage step is applied across an input capacitance Ci, resulting in an output voltage signal proportional to the feedback capacitance as shown in Eqn. 2.9 [44]. 2.2.4.2 Interconnect capacitance characterization Interconnect capacitance characterization in conjunction with simulations dur- ing design phases can provide circuit designers an accurate assessment of speed and noise issues arising due to interconnect capacitances. Sylvester et al. developed a 21 V1 C A A Vdd (no cap) Vdd (cap) I? I V2 0 Vdd 0 Vdd V1 NMOS V2 PMOS Time T Figure 2.7: Left, capacitance measurement test structure. Right, nonoverlapping switching waveforms. charge based capacitance measurement (CBCM) technique for interconnect charac- terization [39,45]. Fig. 2.7 shows a schematic of the test structure used. It comprises complimentary pairs of NMOS and PMOS transistors. The struc- ture on the left is identical to the one on the right except for the test capacitance to be measured. Both structures are driven by two nonoverlapping signals V1 and V2. Turning on the PMOS transistor charges the interconnect capacitance which is subsequently discharged by the NMOS transistor. Ammeters are used to measure the average values of the charge/discharge currents. The difierence between the two average currents I and I0 is used to extract the value of the interconnect capacitance to be measured. I0 ?I = Inet (2.10) Inet = C:Vdd:f (2.11) 22 For the purpose of extracting capacitance values, Inet is plotted as a function of Vdd for speciflc frequencies. C is extracted by dividing the slope of the fltted line by the corresponding frequency. The resolution of this technique is limited by the mismatch in the drain junction and the overlap capacitances of the left and right transistor pairs. 2.2.4.3 Particle detection Microelectronic capacitance transducers can be used in miniaturized electri- cal tomography systems for industrial applications. In this direction Evans et al. designed a CMOS capacitance sensor for detecting dispersed particles in an oil medium [27]. They extended the previously developed CBCM technique by in- corporating a measurement circuit along with the CBCM sensing front-end, instead of using external current measurement instrumentation. The sensor circuit is shown in Fig. 2.8. As in CBCM, the sensed capacitance, the stray capacitances (para- sitic capacitances arising from the measurement circuitry) at the sensing node and the standing capacitance (capacitance ofiered by the sensing electrodes themselves) of the sensing electrodes are charged through Q1 when Clk1 is low and discharged through Q2 when Clk2 is high. Clk1 and Clk2 are nonoverlapping clocks. A current mirror comprising Q3 and Q4 mirrors, amplifles and integrates the charging current over a capacitor Cint. Q6 and Q7 bufier the resulting voltage. Q5 resets the sensing node after every measurement cycle. The relation between the sensing node voltage 23 Clk1 Cx Vdd Gnd Q1 Q2 Q3 Q4 Q5 Q6 Q7 Clk2 Clk2 Cint Vbias Vout x int sensingnode integrationnode Figure 2.8: CBCM circuit for particle detection. Vx and the output voltage Vint can be derived as: Vint Vx = CxR I4 dt CintR I3 dt = Cx(W4=L4) Cint(W3=L3) (2.12) Cx represents the sum of the sensed, stray and standing capacitances at the sensing node. The voltage at the sensing node rises to within one threshold voltage of the power supply, after which Q3 is cut-ofi and the sensor output voltage evaluates to: Vint = Cx(W4=L4)C int(W3=L3) (Vdd ?jVtpj) (2.13) Vdd is the supply voltage and Vtp is the threshold voltage of the PMOS transistor. The equation exhibits a linear relation between the sensor output voltage and the sensed capacitance. Circuit simulation predicted a sensitivity of 42 mV/fF, with a mirror gain of 10 and an integrating capacitor of 1.2 pF. 24 Chapter 3 Cell Adhesion, Viability, Proliferation, Techniques & Biophysics Interaction with a substrate plays a crucial role in the lifecycle of a majority of cell types. This is because most cells are anchorage-dependent, that is, they need to be attached to a solid surface before they can grow and proliferate [46,47]. The mechanisms by which living cells adhere to substrates and their subsequent viability and proliferation have been extensively studied in cell biology [46,47]. In addition to its physiological signiflcance, understanding cell adhesion and growth has many practical applications in the flelds of medicine, bioengineering and environmental sciences. For example, the formation of biofllms (complex aggregations of microor- ganisms on solid surfaces) is important in a variety of applications in food and water quality assessment and treatment [48]. Studying and enhancing cell adhesion to body implants is extremely important for improving biocompatibility, reliability, lubrication and self-regeneration of the adjacent tissues [49]. 3.1 Characterizing cell adhesion Living cells exhibit a variety of modes of attachment to substrates [50]. Cell adhesion is a complex process that results from interplay between many molecular and macro-molecular forces including receptor mediated forces, membrane elasticity 25 and difierent kinds of interfacial forces including electrostatic, undulation, van der Waals interaction and hydration forces [46]. The diversity of mechanisms underlying cell adhesion ultimately enables cells to adapt to difierent kinds of surfaces and living conditions. The factors in uencing the interactions between cells and their substrates can be characterized by quantifying cell adhesion. In this direction, previous efiorts employed techniques like centrifugation and shear ow measurements [51], wherein cells cultured on a substrate are subjected to centrifugal and ow forces respectively. The adhesion strength is related to the fraction of cells that become detached from the surface during mechanical manipu- lation. Such macroscopic measurements on entire cell populations provides limited information regarding individual cell behavior and the statistical variations among cells, and are inherently disruptive of the cell-substrate coupling. Bowen et al. used atomic force microscopy to measure the adhesive force of a yeast cell by immobiliz- ing it at the end of a cantilevered beam and making force-distance measurements for cell retraction from the surface [52]. Barbee et al. developed a thickness shear mode piezoelectric sensor for continuous measurement of interfacial processes be- tween endothelial cells and gold electrodes [53]. Fan et al. studied the adhesion and viability of central neural cells on silicon wafers with difierent surface roughness conditions using scanning electron microscopy [54]. 26 3.2 Assessing cell viability Quantiflcation of cell viability has become an essential requirement for cell based studies. Viability sensors may be useful for optimization of cell culture con- ditions and also for a variety of commercial applications such as drug screening and biocompatibility characterization of implants. Cell viability can be measured either directly by counting the number of healthy cells in a sample or indirectly by measuring an indicator of cell health and proliferation. Most existing methods for estimation of cell viability can be classifled into two categories. The flrst class is based on quantifying the metabolic activity of cells [55,56]. This is accomplished by incubating cells along with an indicator dye or a tetrazolium salt that is reduced to a colored compound only by metabolically active cells. Color development is a function of the number of metabolically active cells, and gives a measure of cell viability. Quantiflcation is normally accomplished using spectrophotometry. The other class of cell viability methods probe the cell membrane integrity using dye-exclusion techniques [56]. This approach takes advan- tage of the fact that healthy cells with well formed plasma membranes exclude dyes such as trypan blue, whereas dead and unhealthy cells with compromised membranes allow dyes to stain internal cellular components. Microscopic analysis is required in order to count only healthy cells and reject unhealthy cells in the sample. 27 3.3 Assessing cell proliferation Quantifying cell growth is essential for many applications in cell biology and biotechnology. It is required for optimizing cell culture conditions, for studying substances that inhibit or promote cell growth, for studying cancer progression, for drug screening, for cytotoxicity testing of anticancer agents, and also for engineering biocompatible implants [57{59]. Assessment techniques for cell proliferation measure the number of actively dividing cells in a sample. A majority of existing proliferation assays measure DNA synthesis as a direct indicator of cell growth [60]. Assessment involves addition of a labeled DNA precursor to the cell culture medium, followed by sample incubation and then quantiflcation of the labeled DNA precursor which has been incorporated intogenomicDNAduringreplicationbymeansofspectrophotometry. Otherindirect techniques for proliferation assessment involve measuring the activity of molecules that regulate the cell division cycle [61]. Most traditional proliferation assays are label-based endpoint assays that require sample preparation and sophisticated lab equipment. Time-lapse microscopy is an example of a well-established, alternative, label-freetechniquethatiscurrentlybeingemployedforautomatingcellproliferation studies. This involves microscope translation, auto-focusing, optical flltering, image acquisition and sophisticated image processing [62]. This can serve as a very useful technique for validating the operation of the integrated sensors that are currently under development for on-chip monitoring of difierent kinds of cell phenomena. 28 3.4 Previous efiorts towards characterizing cell-related properties us- ing electronic sensing techniques 3.4.1 Electric cell-substrate impedance sensing (ECIS) The most well established form of \whole cell" biosensing using electrical means has been impedance-based measurements. The technique of electric cell- substrate impedance sensing was flrst introduced by Keese and Giaver [9,63]. It involves small signal impedance measurement of gold detecting electrodes immersed in the cell culture medium. When the cells attach and spread on the detecting electrode, the measured electrical impedance changes. This is due to the insulating nature of the cell membrane and the formation of adhesion contacts to the electrode, both of which impedes current ow. Changing impedance reveals information re- garding cell morphology and behavior which in turn depends upon coordination of many biochemical reactions sensitive to parameters such as pH, temperature and chemical compounds. Fig. 3.1 illustrates the measurement setup. The gold detecting electrodes have a diameter of 250 ?m. The current returns through a larger area counter electrode (area ? 100 mm2). A 1 V sinusoid of a particular frequency is applied to the sample through a 1 M? resistance. Since the electrode resistance is a few k?s, the current ow is approximately constant. An external lock-in amplifler is used to measure the magnitude and phase of the voltage across the sample. The in-phase voltage is proportional to the series resistance and the out-of-phase voltage is proportional 29 cell culture medium (electrolyte) cells detectingelectrode counterelectrodesignal source1 M? lock-inamplifier data acquisitionsystem Figure 3.1: A schematic of the ECIS system. to the series reactance of the sample. The measured impedance is formed by the electrode/electrolyte interface [64] and the cell layer over the electrode. The resistive component of the cell layer results from the ionic current under and between the cells. The reactive component results from the capacitive current ow across the cell membranes. Giaver and Keese used impedance sensing to monitor cell proliferation, mor- phology, and motility [9,63]. Since then there have been several reports of impedance measurements addressing a variety of cell sensing applications. Ehret et al. mon- itored impedance changes of cells cultured on interdigitated electrodes during cell adhesion and growth [10]. Lin et al. used this technique to difierentiate between normal and abnormal cell types [12]. Xiao et al. used ECIS for on-line assessment of cell cytotoxicity [65]. 30 3.4.2 Micro uidic capacitance cytometry A recent efiort towards measuring microscopic cellular capacitances employs ow cytometry in a micro uidic channel. Sohn et al. detected capacitance changes evoked by the passage of individual cells across a 1 kHz electric fleld in a micro uidic channel [34]. The capacitive change has been attributed to the polarization response of a cell as it passes through an electric fleld region. The authors also found an interesting linear relation between the DNA content of eukaryotic cells and the change in capacitance. Fig. 3.2 shows a schematic of the micro uidic system. It comprises a pair of gold microelectrodes (50 ?m wide) on a glass substrate separated by a distance of 30 ?m. The micro uidic channel was made of polydimethyl siloxane (PDMS) and measured 30 ?m in height. Capacitance measurements were performed using a commercial capacitance bridge. Distinct capacitive peaks in the range of 3 fF - 12 fF were detected corresponding to ow of cells past the electrodes. electrode fluid in PDMSchannel fluid out Figure 3.2: Schematic of the micro uidic device for capacitance cytometry. 3.5 Our approach using integrated capacitance sensing All the traditional approaches mentioned in section 3.1 for characterizing cell adhesion and section 3.2 for monitoring cell viability employ specialized techniques 31 and processes. In addition, most of them require sophisticated laboratory equip- ment. Almost all of the cell viability assessment techniques involve an inherent process of sampling which may not be feasible for samples with extremely small volumes. With reference to nontraditional electronic sensing techniques discussed in sec- tion 3.4, although ECIS employs integrated electrodes for cell sensing, it still requires external measurement instruments such as lock-in ampliflers and LCR-meters. The measurements are also subject to electrochemical side-efiects, since the electrodes are directly exposed to the culture medium, an aqueous ionic solution. The elec- trodes require custom fabrication for biocompatibility and electrochemical corrosion resistance purposes. The integrated micro uidic capacitance cytometry approach, although impressive in terms of its sensitivity, still uses an external capacitance bridge for making measurements. In contrast to the previous efiorts, CMOS sensors can integrate passivated electrodes with the capacitance measurement circuitry on the same substrate over- coming the above mentioned limitations and also eliminating the need for exter- nal instruments. This work has developed integrated capacitance sensors that can be designed and fabricated using conventional CMOS technology, for inexpensive, portable and reproducible characterization of cell adhesion and viability properties, without the need for extensive laboratory infrastructure. The integrated cell sens- ing approach presented here ofiers the unique advantage of long term continuous cell monitoring in a standard culture environment without any modiflcation, and without the need for disruptive external forces or biochemical agents employed in 32 the traditional techniques. 3.6 Biophysics of cell-substrate capacitance In the presence of low frequency, low strength electric fleld excitations, living cells behave as insulating structures embedded in an electrically conductive growth medium which is an aqueous ionic solution [14]. Cell surfaces generally carry a surface charge density, which can be positive or negative depending upon the cell type [14]. The majority of cell surfaces are negatively charged. This induces a counterionic cloud around the cells in the surrounding medium. When exposed to an external electric fleld these counterions are displaced tangentially around the cell surface giving rise to an induced dipole moment as illustrated in Fig. 3.3. Both the insulating nature of cells at low excitation frequencies and the counterionic polarization are responsible for the low frequency capacitive behavior of cells [14]. At low excitation frequencies, the plasma membrane shields out the cell interior, and therefore all charges and dipoles present inside the cell have no in uence on the dielectric properties of cells [14]. insulating cell suspended in a conductive growth medium cell surface charge counterionic charge cell growth medium induced polarization on exposure to an electric field induced cell dipole electric field counterionic polarization cell Figure 3.3: Cellular counterionic polarization in the presence of external electric flelds. 33 3.6.1 Correlating capacitance with cell-substrate interaction Next we examine the behavior of a cell suspension when it comes into contact with a solid biocompatible substrate. Upon contact with a solid substrate, proteins in the growth medium spontaneously adsorb onto the substrate. The interaction be- tween cells and substrate begins with the sedimentation phase when the suspended cells gradually drift downwards and settle on the surface. This is followed by the adhesion phase when cells anchor themselves to the surface through various mecha- nisms at both molecular and cellular levels [46]. This is accompanied by a signiflcant change in cell morphology wherein the cells exhibit a spreading behavior. Under favorable conditions there is a proliferation phase during which cells divide and pro- liferate. In the presence of weak, low frequency electric flelds all three phases can be modeled as a process of cell dielectric layer formation as shown in Fig. 3.4. The capacitance arising from this dielectric layer successively increases in the phases described above. The capacitance between cells and substrate is lowest in the sedimentation phase since the cells are far from the surface and the cellular dielectric layer is not yet completely formed. The conductive growth medium screens out the suspended cells from the electric flelds. Once the cells completely settle on the substrate and start attaching to the surface, they undergo polarization on account of being exposed to the electric flelds. This gives rise to the cell-substrate capacitance. During the adhesion phase there is a remarkable decrease in the dielectric layer thickness due to cell spreading and anchoring mechanisms. In addition, the efiective dielectric constant of the cell layer increases due to increasing cell membrane surface 34 suspended cells electric field substrate growth medium sedimentation cells settled on the surface growth medium growth medium substrate substrate polarized electric field electric field cell adhesion & proliferationcellular dielectric layer formation cells adhering & proliferating Figure 3.4: Cell dielectric layer formation in the presence of weak, low-frequency electric flelds: sedimentation phase (top), initiation of adhesion (middle), adhesion and proliferation phases (bottom). area and increasing cell dipole density. Both factors contribute to a steady increase in the cell dielectric layer capacitance. Once the cells have adhered to the surface and adjusted to the culture conditions, the proliferation phase begins and the measured capacitance re ects ongoing cellular activity. In cases of adverse conditions, the growthphasesdescribedabovemaybesupersededbyacelldeathphaseduringwhich the plasma membranes begin to disintegrate, causing a reduction in capacitance of the cell dielectric layer. The above discussion regarding correlating the sensed capacitance with the cell-substrate interaction process provides an explanation for the observations made during the experiments that were performed with actual biological cells cultured on fabricated capacitance sensor chips. Several experiments involving three difierent 35 cell types have been performed with the sensor chips and the results have been found to be in agreement with the model presented here. These experimental results are presented in the next chapter. This model is entirely based upon the low frequency dielectric properties of living cells as discussed in [14]. 36 Chapter 4 First generation capacitance sensors for establishing proof of concept 4.1 Single electrode capacitance sensor: design and operation A custom CMOS capacitance sensor for the cell sensing application was de- signed using the topology shown in Fig. 4.1 [20,66]. The flrst generation capacitance sensor employed a single electrode conflguration. The passivation layer of the CMOS fabrication process was used for electrical insulation and biochemical isolation of the sensing electrode from the aqueous ionic cell medium. The single electrode conflg- uration provides maximum penetration depth for a given excitation fleld. Since the already available passivation layer of the chip is used as the insulating cover for the sensing electrode which is approximately 1 ?m thick, penetration depth is an important factor to consider in the sensor design. For a single electrode capacitance sensor that functions as a proximity detector, output voltage is non-linearly related to object proximity which results in an increase in sensitivity with proximity of the sensed object to the chip surface [17]. This characteristic of the sensor makes it appropriate for monitoring anchorage dependent cells that are directly coupled to the chip surface. The sensor operation is based upon the charge sharing principle. The sensor 37 CN1 CN2 N1 N2 M1 M3M2 Vdd Vss reset resetreset unity gain buffer metal 2shield metal 3 sensing electrode N3 M4 Vdd output buffer reset Control Signals reset reset passivation layer growth medium adherent & proliferating cell Cm3m2 ionic polarization on exposure to an electric field tangential flow of compensating ionic charges fixed ionic charges VN Figure 4.1: Cell-substrate capacitance sensor: design and operation. circuit has two nodal parasitic capacitances CN1 and CN2 whose charging and dis- charging are controlled by a set of three MOSFET switches M1, M2 and M3. The sensor operates in two phases. In the reset phase, switches M1 and M3 are turned on, charging node N1 to Vdd and node N2 to Vss, while M2 is ofi. In the evaluation phase, M2 is turned on, while M1 and M3 are ofi, redistributing the charges between CN1 and CN2. The joint nodal voltage VN is a function of the sensed capacitance Csensed as a result of the charge redistribution. VN = (CN1 +Csensed)Vdd+CN2VssC N1 +CN2 +Csensed (4.1) 38 Here Csensed refers to the efiective capacitance value of the capacitive network as seen by the sensing electrode in Fig. 4.1. The topmost metal layer, metal3, forms the sensing electrode. Sensitivity and dynamic range of the measurement is maximized by minimizing the nodal parasitics. For this purpose, the substrate coupling capacitance of the sensing electrode is shielded by means of a larger area metal2 plate in the lower layer. The large capacitance Cm3m2 between the sensing electrode and the shield is canceled by driving the metal2 shield with a potential that tracks the sensing electrode potential using a unity-gain bufier. Sensor input dynamic range improves with increasing sensing electrode area. 4.2 Sensed capacitance modeling Several factors in uence the capacitance measured at the sensing electrode by the circuit. 4.2.1 Cell layer capacitance Ccell As discussed in the previous chapter, after sedimentation the cells form a complex dielectric layer at the growth medium-passivation layer interface. Ionic conductances are neglected in the model since the cell environment is exposed to weak electric flelds with no conduction current ow (the sensing electrode is totally insulated from the cell environment using the chip passivation layer, a very good insulator). Thus the cell layer is regarded as purely capacitive. In reality, the cells form a heterogeneous layer which exhibits both spatial and temporal variation of 39 (a) passivation layer growth medium bulk sensing electrode storing charge ionic screen shielding the medium interior including cells CfCint unpolarised cell Cbase Cox Cgm on-chip sensing microelectrode CintCf Cint passivation layer CcellCf? Cf?cell ionic screen shielding the interior of the medium charge stored on the sensing electrode increases with the cell polarization capacitance on-chip sensing microelectrode electric field growth medium bulk (b) Cgm Cint Cint Cint Cint Cox Figure 4.2: Models of sensed capacitance during the difierent phases of the interac- tion process between cells and substrate: (a)pre-adhesion phase, (b)post-adhesion phase. dielectric properties. Results from capacitance cytometry experiments have previ- ously reported capacitances on the order of a few fF?s on account of the polarization response of the cells as they pass through an electric fleld across microelectrodes [34]. Therefore the cell layer capacitance is on the order of magnitude of 0.01 fF/?m2. It is important to note that this capacitance is the whole cell capacitance which is 40 difierent from the cell membrane capacitance which is on the order of magnitude of 10 fF/?m2 [67]. 4.2.2 Passivation layer capacitance Cox The passivation layer of the fabrication process electrically isolates the sensing electrode from the cell environment. The chip passivation layer comprises silicon dioxide (dielectric constant: 4) and silicon nitride (dielectric constant: 7.5). So the efiective dielectric constant of the passivation layer was assumed to be 6. For a passivation layer with uniform thickness of 1 ?m and a dielectric constant of 6, the capacitance per unit area is approximately 0.05 fF/?m2. In the sensed capacitance network Cox and Ccell appear in series, and their order of magnitudes are comparable. Thus in order to increase the input dynamic range of the sensor, the insulation layer above the sensing electrode should be as thin as possible. The value of Cox can be increased, and overall dynamic range enhanced, by thinning the passivation layer over the electrodes. However, this would require custom process development, raising signiflcant practical issues as well as associated cost, and would limit the generality of the technique. The chip was fabricated in a commercially available CMOS technology, so the sensor design was constrained by the limitations imposed by the process technology. 41 4.2.3 Interfacial capacitance Cint The passivation layer (a solid surface) is in direct contact with the cell growth medium (an aqueous ionic solution), resulting in a layered polarized interface accord- ing to Gouy-Chapman-Stern theory [68]. The adhesion process of cells introduces additional solid-liquid interfaces. In addition to the electrifled interface there is also a difiuse layer capacitance arising from the difiuse charge extending from the interface to the liquid electrolyte bulk. The spatial extent of this space-charge re- gion is characterized by the Debye length which, for a univalent electrolyte, can be expressed as [68]: LDE = (?ekT=2n0q2)1=2 (4.2) where ?e is the electrolyte permittivity and n0 is the ionic density. The Debye length in the electrolyte is normally lesser than 10 ?A for electrolytes with concentrations greater 10?5 M [68]. Both the interfacial and the difiuse layer capacitances occur in series and end up being on the order of 100 fF/?m2, 3-4 orders of magnitude larger than the passivation layer capacitance [68]. 4.2.4 Fringe capacitance Cf The electric fleld originating from the sensing electrode can be resolved into vertical and lateral components. The vertical component dominates at the electrode center while the lateral component dominates at the electrode periphery. The lateral coupling gives rise to fringe capacitances. The interlayer fringe capacitances inside the chip (derived using the process parameters provided by the vendor) are on the 42 order of 10 aF/?m. The fringe capacitances arising from the lateral coupling of the sensing electrode with all the neighboring metal lines through the passivation layer, cells and growth medium will be on the same order of magnitude and therefore their efiect cannot be ignored. 4.2.5 Growth medium capacitance Cgm The growth medium, a strong electrolyte, produces an ionic screen that shields its interior from the sensing fleld as shown in Fig. 4.2(a). Due to this, the sensor responds to cell-related phenomena only after the cells are inside the ionic screen and exposed to the sensing fleld as shown in Fig. 4.2(b). This happens when they settle onto the surface and form physical contacts with it during adhesion and proliferation. Under equilibrium conditions the bulk of the growth medium is electrically neutral and is free of potential gradients, and can be considered as an ideal ionic conductor. This conductor above the cell layer is capacitively coupled to all the neighboring conductors (including metal lines for power, voltage biases and a grounded metal case housing the sensor flxture) resting at DC potentials, excluding the sensing electrodes. The sum total of all these capacitances evaluates to Cgm. The self capacitance of the ionic conductor places a lower bound on Cgm and is on the order of pF when the dimensions of the sensor well are in the cm range. For example, the self-capacitance of a conducting sphere of radius R (capacitance between the conducting sphere and another grounded hollow sphere of inflnite radius and centered on the conducting sphere) is given by C = 4??0R. So in our case, the 43 bulk of the growth medium is the ionic conductor which is capacitively coupled to the grounded metallic case housing the sensor test flxture. This capacitance will be greater than the self capacitance of the isolated growth medium bulk which is on the order of pF. Cgm is expected to vary for difierent conflgurations of the sensor well. As long as the total volume of the growth medium is on the order of 100s of ?Ls (or higher), as in the reported sensor conflguration, Cgm is on the order of pF?s (or higher) and will not in uence sensor operation. 4.2.6 Baseline capacitance Cbase The baseline capacitance represents the capacitance due to dielectric prop- erties of residual materials on top of the passivation layer. These include surface residues resulting from the polymer used for encapsulation of the bond wires and from adsorption of materials from the growth medium onto the surface. The ini- tial capacitance recording obtained from each of the sensors, at the start of every experiment (when the sensor chip was tested with biological cells) as soon as the sensor well was loaded with the cell culture suspension, is dominated by this baseline capacitance. On compiling the data obtained from all the experiments, the initial capacitance sensed by a 40?40 ?m2 sensor was found to vary between sub-fF values to approximately 10 fF (for a 30?30 ?m2 sensor, between sub-fF values to approx- imately 2 fF, and for a 20?20 ?m2 sensor, between sub-fF values to approximately 1 fF). We attribute these variations in initial sensed capacitances to difierent values 44 of Cbase at the start of difierent experiments. Cbase is sensitive to a variety of fac- tors including surface residues on the passivation layer, microscopic air bubbles and hydrodynamic disturbances. 4.2.7 Efiective sensed capacitance Csensed From the above discussion, the capacitance as seen by the sensing electrode equates to the efiective capacitance ofiered by the network of passivation layer, cell layer, fringe parasitics and all interfacial capacitances between various liquid- solid boundaries. The sensed capacitance must be modeled separately for the pre- adhesion and the post-adhesion phases, since during the adhesion phase the interface between the growth medium and the substrate undergoes a drastic change in its structural and dielectric properties resulting in an appreciable variation in the sensed capacitance. Both models of sensed capacitance are illustrated in Fig. 4.2. During the pre-adhesion phase of Fig. 4.2(a), the growth medium produces an ionic screen in response to the electric fleld originating from the sensing electrode. The ionic screen at the boundary between the growth medium and the substrate shields the interior of the solution including the suspended cells as a result of elec- trostatic induction. The sensed capacitance network comprises the passivation layer capacitance Cox and interfacial capacitances Cint in series with the baseline capaci- tance Cbase and Cgm. The fringe capacitance Cf appears in parallel with Cbase (see Fig. 4.2(a)). The reference potential for the fringe capacitance originates from adjacent 45 metal interconnects resting at DC potentials. Under equilibrium conditions the bulk of the growth medium is electrically neutral and is free of potential gradients, and can therefore be regarded as an ideal ionic conductor. The reference potential for the capacitances associated with vertical electric fleld coupling originates from all nearby conductors resting at DC potentials (mainly the grounded metallic case housing the sensor test flxture) to which the bulk of the growth medium is capacitively coupled to. When a ground electrode was introduced in the growth medium, we observed the sensor outputs to saturate, which indicates the presence of a grounded conducting plane on the chip surface. This can be explained by the grounding of the surface conductances that are formed at the passivation layer-growth medium interface, that efiectively screen out all the components of the sensed capacitance network except for the passivation layer capacitance. This way the sensed capacitance is limited to just the passivation layer capacitance. In the absence of a ground electrode in the growth medium, the surface conductances are oating which prevents the screening of the sensed capacitance network. The combined efiect of all the difierent contributions towards the sensed ca- pacitance can be visualized using the capacitance network shown in Fig. 4.2(a), with the sensed capacitance expressed as: 1 Csensed = 1 Cbase +Cf + 1 Cox + 1 Cint + 1 Cgm (4.3) Considering the relative orders of magnitude of the various capacitances, the efiective value of pre-adhesion sensed capacitance can be modeled as: 46 1 Csensed ?= 1 Cbase +Cf + 1 Cox (4.4) The cells do not in uence the cell-substrate capacitance until they have set- tled on the substrate below the ionic screen (that arises as a result of electrostatic induction), and are exposed to the varying electric flelds (see Fig. 4.2(b)). This happens during the adhesion phase when the cellular dielectric layer begins to form on the surface of the passivation layer. So the space between the ionic screen and the solid surface can be viewed as being permeated with cellular dipoles enhancing its dielectric constant. This efiect is modeled by replacing Cbase with Ccell, as illus- trated in Fig. 4.2(b). During this process Cf is also in uenced by the cells present in neighboring regions. This efiect is incorporated into the model by replacing Cf with Cf0. Again comparing the relative orders of magnitude of the various capacitances in the sensed capacitance network, the efiective value of post-adhesion phase sensed capacitance can be modeled as: 1 Csensed ?= 1 Ccell +Cf0 + 1 Cox (4.5) ItisimportanttonotethatCbase, Ccell, Cf andCf0 representlumpedparameter values of their corresponding capacitances which are actually distributed in nature duetotheirheterogenousandtime-varyingcharacteristics. Asmentionedpreviously, the cell layer capacitance Ccell is a function of many factors in uencing its structural and dielectric properties [7,8,69]. These include membrane integrity, membrane potential, cell morphology, adhesion strength, extra-cellular ionic distributions and 47 also number and surface area coverage of cells above the sensing electrode. The above discussed models for the pre-adhesion, adhesion and post-adhesion phases have been developed to explain the observations made during the experiments that were performed with actual biological cells cultured on fabricated capacitance sensor chips. Several experiments involving three difierent cell types have been per- formed with the sensor chips and the results have been found to be in agreement with the models presented here. The experimental results are presented in the fol- lowing sections. The models are based upon the low frequency dielectric properties of living cells as discussed in [14]. 4.3 Chip design, fabrication and bench testing The capacitance sensor was designed using the Cadence Design Suite by em- ploying the technology parameters for a commercially available 0.5 ?m standard CMOS process. The sensor circuit was designed for a 3 V supply and for an op- erating frequency of 1 kHz. The design was simulated using the Cadence Spectre Simulator by employing the parametric analysis feature for varying the input sensed capacitance. The sensor chip layout was drawn using the Cadence Virtuoso Lay- out software. The layout information was then submitted to the MOSIS service for chip fabrication. The sensor chip measuring 1.5?1.5 mm2 was fabricated in a commercially available 0.5 ?m, 2-poly, 3-metal standard CMOS technology. Sensor dynamic range improves with increasing sensing electrode area. For studying the in uence of this dependence on the sensor response to cells, three 48 (a) (b) (c) 20 ?m 30 ?m 40 ?m 30 ?m sensor chip DIP40 package well for containing cell culture polymer patterened for bond wire insulation Figure 4.3: (a) Photomicrograph of the fabricated sensors showing the three sen- sor groups with sensing electrode areas: 20?20 ?m2, 30?30 ?m2 and 40?40 ?m2. (b) Photograph of a biocompatibly packaged capacitance sensor chip. (c) Photomi- crograph of MDA-MB-231 human breast cancer cells cultured in vitro on top of a capacitance sensor chip. sensor groups with electrode areas of 20?20 ?m2, 30?30 ?m2 and 40?40 ?m2 were designed and tested. The chip comprised an array of 28 sensors (9 sensors of size 20?20 ?m2, 9 sensors of size 30?30 ?m2 and 10 sensors of size 40?40 ?m2) conflned within an area of 400?400 ?m2. Fig. 4.3(a) shows a photomicrograph of the fabricated sensors. The chip was bench tested by calibrating the sensors as proximity detectors [bench testing was performed along with J. Van Sickel]. Calibration was performed by using an external metal electrode whose vertical positioning was controlled by means of a piezoelectric micropositioner. The micropositioner was controlled by means of a hand terminal that specifled the vertical distance through which the 49 0 5 10 15 20 25 300 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Distance of the electrode from the chip surface (?m) Sensor Voltage (V) 20x20 ?m2 sensor Experimental data 30x30 ?m2 sensor Experimental data 40x40 ?m2 sensor Experimental data Simulation Parameters: Passivation layer thickness = 1 ?m Dielectric constant = 6 CN1=20 fF, CN2=18 fF Figure 4.4: Variation of the sensor voltages with electrode distance. metal electrode was to be translated. The metal electrode was an insulated nee- dle held by the translation stage comprising the micropositioner. The needle was electrically oating and was not connected to any DC source or the ground. So for the proximity detection application, the environment is employed as the return path for the capacitive current [41]. Fig. 4.4 shows the test results superimposed on the simulated sensor voltages. The symbols represent experimental values of sensor voltage obtained by moving the micropositioned electrode in steps of 2 to 3 ?m. The output voltage ranges for the 20x20, 30x30 and 40x40 ?m2 sensors were found to be 100 mV, 200 mV and 400 mV respectively. The solid curves are the sensor outputs simulated using the charge sharing relation Eqn. 4.1 for the three sensor groups. Upon knee-fltting the bench test results with the simulated curves using the least squares technique, the nodal parasitic capacitances CN1 and CN2 were estimated using least squares flts to be 20 fF and 18 fF respectively [17]. 50 In order to translate the sensor outputs to sensed capacitance values, the output voltages during the evaluation phase are subtracted from their corresponding voltages during the reset phase for ofiset cancelation. In some cases, this results in negative values of sensed capacitances due to small voltage uctuations. The inverse relation for Csensed as a function of this voltage difierence can be derived from (4.1) as Csensed = (Vdd?Vss)CN2 ?Vdiff(CN1 +CN2)V diff (4.6) where Vdiff = Vreset?Veval and Vreset = Vdd. Here both Vreset and Veval refer to the voltages before the readout bufier. 4.4 Sensor resolution analysis For the single electrode capacitance sensor functioning as a proximity detector, sensitivity is a function of object proximity. Sensor sensitivity increases with object proximity to chip surface as can be seen from the simulated plots in Fig. 4.4. This characteristic is appropriate for the present application, since the cells are directly coupled to the chip surface. Due to the nonlinear relation between proximity and the sensor output, the distance resolution varies with the object proximity. The distance resolution R(di) at a distance d = di from the chip surface can be computed using the relation: R(di) = noise@V diff @d (di) (4.7) where noise is the sensor output noise level and 51 0 1 2 3 4 50 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Distance from the chip surface (?m) Distance resolution ( ?m) 20 x 20 ?m2 sensor30 x 30 ?m2 sensor 40 x 40 ?m2 sensor Simulation Parameters: Passivation layer thickness = 1 ?m Dielectric constant = 6 CN1=20 fF, CN2=18 fF Noise level = 5 mV Figure 4.5: Sensor distance resolution as a function of object proximity. Vdiff = Vreset ?Veval = Vdd? ?(C N1 +Csensed)Vdd+CN2Vss CN1 +CN2 +Csensed ? = CN2(Vdd?Vss)C N1 +CN2 +Csensed (4.8) Distance resolution improves with increasing proximity to the surface, increasing electrode area and decreasing noise level. So for a given sensor with a flxed sensing electrode area, the best possible resolution is achieved when the object is in contact with the chip surface. Fig. 4.5 shows a plot of distance resolution for the three sensor groups with difierent electrode areas as a function of proximity, for a measured noise level of 5 mV (standard deviation of the output voltage uctuations). The sensors exhibit a distance resolution of 3 nm when the sensed object is in contact with the chip surface (R(di = 0 ?m) = 3 nm in Fig. 4.5). The corresponding capacitance resolution was evaluated to be 135 aF, with a maximum sensor gain of 37 mV/fF 52 (this is the maximum sensor gain as was derived from the simulated plots shown in Fig. 4.4). 4.5 In vitro experiments demonstrating sensor response to cell phe- nomena For the purpose of testing the sensors in vitro, the sensor chip in a DIP40 ceramic carrier was encapsulated using a biocompatible polymer for bond wire insu- lation and isolation of cells from toxic materials of the DIP40 chip carrier [biocom- patible chip packaging was performed by M. Urdaneta]. The encapsulation material is a photopatternable polymer (Loctite 3340, Henkel) [70]. A well (diameter = 1.5 cm, height = 0.5 cm) was glued on top of the packaged chip for containing the cell culture medium. Fig. 4.3(b) shows a photograph of the flnal test flxture. Fresh unused chips possessing clean surfaces without any additional surface modiflcation or functionalization were used for all the experiments. Prior to cell loading, the biocompatibly packaged chip was rinsed with deionized water, sterilized using UV light, and then rinsed with the corresponding cell growth medium. The UV light does not afiect the capacitance characteristics of the chip (sensor outputs did not change before and after exposure to UV light) and was used for sterilization only before the sample is loaded. In every experiment, 500 ?L of the cell suspension was loaded into the sensor well using standard aseptic techniques. The sensor well was sealed using either a cover slip or a gas permeable Breathe-Easy membrane (Fisher Scientiflc). Fig. 4.3(c) shows a photomicrograph of MDA-MB-231 human breast 53 (a) (b) Figure 4.6: (a)Photograph of a cell loaded chip mounted on the test board. (b)Photograph of the data acquisition setup. cancer cells cultured on a capacitance sensor chip. To date, the sensor chips have been tested with three difierent cell types namely: bovine aortic smooth muscle cells (BAOSMC), human breast cancer cells (MDA-MB-231) and human colonic adenocarcinoma cells (Caco-2). The sensor chip with cells loaded into the well was then mounted on a test board with a data acquisition interface. The board was placed inside a grounded metal case (functioning as a Faraday shield) and was powered using a regulated supply. The chip was monitored using a laptop running LabVIEW 7.1 (National Instruments) and interfaced to the test board using a PC-CARD-DAS16/16AO data acquisition card (Measurement Computing). A shielded PCMCIA cable was used to connect the data acquisition card to the test board. The test flxture containing the sensor chip was maintained at 37?C, 5% CO2 inside an incubator during the monitoring period. The above described procedure was common to all the experiments involving 54 monitoring sensor responses to cells cultured on the chip surface. These experiments are described in the following sections. 4.5.1 Tracking cell adhesion 4.5.1.1 Experiment 1: Averaged sensor response to cell adhesion This experiment was performed with bovine aortic smooth muscle cells [bio- compatible chip packaging and cell loading was performed by N.M. Nelson]. The cells were cultured in a T25 ask in growth medium (pH 7.4 and bufiered for CO2) in a commercially prepared medium supplemented with serum, growth factors and antibiotics (Cell Applications Inc.). The cells were allowed to grow in the ask un- til they were con uent and were then detached by using a cell scraper. After cell detachment a suspension with an approximate density of 1?106 cells/mL was pre- pared. The sensor chip was flrst calibrated by adding the BAOSMC growth medium alone without cells and measuring the capacitive coupling between the solution and electrodes. The well was then loaded with the high density BAOSMC suspension so that all the sensors in the test array were exposed to similar conditions. The sensor outputs were monitored over a period of 24 hours. This experiment was conducted before the above described data acquisition system was developed and therefore the sensor measurements were recorded manually. In between measurements the flxture was maintained inside an incubator at 37?C, 5% CO2. Coupling of cells to every sensor was conflrmed through visual observation [visual observation was performed along with N.M. Nelson]. 55 0 10 20800 900 1000 1100 1200 1300 1400 1500 Sensor Voltages Time (h) Voltage Difference(mV) 0 5 10 15 20 250 5 10 15 20 25 Computed Capacitance Time (h) Sensed Capacitance (fF) reference voltage difference 20x20 growth medium 30x30 growth medium 20x20 cells 30x30 cells 40x40 growth medium 40x40 cells 40x40 cells 40x40 growth medium 30x30 cells 20x20 cells 30x30 growth medium 20x20 growth medium Figure 4.7: Averaged sensor response to cell adhesion. The data points show the average output voltage difierences and standard deviation values across the sensors in each of the three groups. The horizontal lines plotted are the average sensor recordings with the chip exposed to growth medium alone before the sensor well was loaded with cells and have been plotted here across the time frame for com- paring with the averaged sensed capacitances that were recorded in response to cell adhesion. The sensed capacitances were computed as discussed previously. Fig. 4.7 shows a plot of the average voltage difierences for the three sensor groups. Error bars indicate the standard deviation in response between all sensors of the same size. The voltage difierences for all three sensor groups decreased with time, tracking the adhesion process as expected and indicating an increase in capacitive coupling between the cells and the on-chip electrodes after they were allowed to settle on the chip surface over a period of time. Based upon these measurements the computed average sensed capacitances increased by 5.1 fF, 6.9 fF and 13.2 fF for the 20x20, 56 0 2 4 6 80 10 20 0 2 4 6 80 10 20 0 2 4 6 8 0 10 20 0 2 4 6 80 10 20 0 2 4 6 80 10 20 0 2 4 6 80 10 20Sensed Capacitance (fF) Time (h) sensor 1 sensor 3 sensor 5 sensor 2 sensor 4 sensor 6 adhesion pre?adhesion Figure 4.8: Online tracking of cell adhesion process by six 40?40 ?m2 sensors. 30x30 and 40x40 ?m2 sensor groups respectively as shown in Fig. 4.7. 4.5.1.2 Experiment 2: Online tracking of cell adhesion In this experiment the previously described data acquisition system was set up for online monitoring of the sensor responses to BAOSMC loaded on top of the chip surface and placed inside an incubator. BAOSMC loading and incubation were performed using standard aseptic techniques [biocompatible chip packaging was performed by M. Urdaneta]. The test flxture containing the sensor chip was maintained at 37?C, 5% CO2 inside an incubator during the monitoring period. The sensor readings were recorded every 5 minutes with the cells exposed to electric fleld excitations only during the short recording intervals. Fig. 4.8 shows the sensed capacitances as recorded concurrently by six 40?40 57 ?m2 sensors during the flrst 8 hours of cell incubation. The capacitance plots are indicative of the pre-adhesion and adhesion phases as discussed in the previous chapter (experimental observation agrees with the proposed model). The cells took around2.5-4.75hourstoinitiateadhesionaftersedimentationandaround30minutes to 1.5 hours to adhere (pre-adhesion: 3.29?1.05 hours, adhesion: 1.08?0.34 hours). The flgure also shows phase delays in the initiation of cell adhesion as recorded by sensors in difierent locations. The capacitance uctuations observed throughout the monitoringinterval(predominantlyinthepost-adhesionphase)havebeenattributed to interference noise coupling to the sensing node during the sensor evaluation phase. This is discussed further in Section 4.5.5. 4.5.2 Monitoring cell viability 4.5.2.1 Experiment 1: Averaged sensor response to changes in cell viability and sensor response validation using Neutral Red This experiment with BAOSMC monitored the sensor response to changes in cell viability. For this the procedure in section 4.5.1.1 was repeated but this time with BAOSMC stained with Neutral Red in a colorless growth medium [biocompat- ible chip packaging was performed by M. Urdaneta and cell loading was performed by N.M. Nelson]. The sensors were monitored over a period of 48 hours. This ex- periment too was conducted before the data acquisition system was developed and therefore the sensor measurements were recorded manually. Cell viability was as- sessed independently through visual inspection of the stained cells. Living healthy 58 0 10 20 30 40 50900 1000 1100 1200 1300 1400 1500 Sensor Voltages Time (h) Voltage Difference(mV) 0 10 20 30 40 500 2 4 6 8 10 12 14 16 18 20 Computed Capacitance Time (h) Sensed Capacitance (fF) reference voltage difference 20x20 base line 30x30 base line 20x20 cells 30x30 cells 40x40 base line 40x40 cells 40x40 cells 40x40 base line 30x30 cells 20x20 cells 30x30 base line 20x20 base line Figure 4.9: Averaged sensor response to changes in cell viability. cells have the characteristic property of taking up and retaining Neutral Red stain whereas non-viable cells do not retain the stain [47]. Fig. 4.9 shows the averaged response of the three sensor groups over the 48 hour period. Over the flrst day the cells were able to retain the stain (conflrmed along with N.M. Nelson through visual observation: colorless medium remained colorless) and the sensors showed an increase in capacitive coupling between cells and sensor electrodes. On the second day, however, it was observed that the cells no longer retained the stain and had released the dye into the growth medium (visual conflrmation was performed along with N.M. Nelson), an indication of non-viability. Accordingly the sensors showed a decrement in the measured capacitance values. The compromised cell viability was attributed to the gas-impermeable cover slip that was used to seal the sensor well after cell loading in order to maintain sterility. 59 4.5.2.2 Experiment 2: Online monitoring of cell viability and sensor response validation using Alamar Blue In this experiment the data acquisition system was set up for online monitor- ing of the sensor responses to changes in BAOSMC viability [biocompatible chip packaging was performed by M. Urdaneta]. The sensor responses were continuously acquired every 5 minutes for a period of 29 hours with BAOSMC incubated on top of the chip surface. For validation purposes cell viability was conflrmed using Alamar Blue (obtained in aqueous form from Biosource International), a cell viability dye. Alamar Blue is commercially available in an oxidized, blue, non uorescent form (re- sazurin), which becomes gradually reduced to its pink uorescent form (resorufln) in a medium containing viable cells [56]. The dye molecules are reduced by a class of enzymes called reductases found in mitochondrial membranes and the cytosol [71]. Reduction of Alamar Blue is directly correlated with the number of viable cells, incubation time and temperature. The resazurin reduction test has increasingly been used in cytotoxicity assays for high-throughput screening in pharmacological applications [72] because it is nontoxic and nonterminal, that is, it does not require that the cells in the sample be killed in order to make the measurement. BAOSMC loading and incubation were performed as in the previous experi- ments, with Alamar Blue mixed into the growth medium in a 1:10 ratio by volume. The culture well has a sample capacity of approximately 500 ?l. Fig. 4.10 shows the sensed capacitances as recorded concurrently by three of the on-chip sensors, one representative trace from each sensor group with difierent sensing electrode area. 60 0 5 10 15 20 25 30 0 10 20 30 40 0 5 10 15 20 25 30 0 5 10 15 20 0 5 10 15 20 25 30 0 5 10 15 Time (h) Sensed Capacitance (fF) sample 0 0% sample 1 58.5% sample 2 73.8% day 1 sample 0 0% replenished growth medium sample 1 0.95% sample 2 7.15% day 2 40x40 ?m2 sensor 30x30 ?m2 sensor 20x20 ?m2 sensor Alamar blue % reduction values loaded cells Figure 4.10: Online monitoring of cell viability with concurrent measurements using Alamar Blue dye. Alamar Blue % reduction values obtained from spectrophotomet- ric analysis are shown above the times corresponding to extraction of the microsam- ple. The fraction of Alamar Blue in reduced form was evaluated by measuring the ab- sorbance of the growth medium at 570 nm and 600 nm. This was accomplished by performing spectrophotometric analysis on 20 ?L samples extracted from the sensor well at instances during the monitoring period denoted by the vertical time lines in Fig. 4.10. The sensed capacitance values tracked the pre-adhesion and adhesion phases as in the previous experiments. After adhesion the sensed capacitances remained 61 high until the 9th hour of incubation, which is indicative of viability. Alamar Blue was gradually reduced to its pink form during this 9 hour interval, conflrming posi- tive cell viability. According to spectrophotometric readings, the fraction of Alamar Blue in reduced form was found to be 0%, 58.5% and 73.8% at 0, 4 and 9 hours, respectively, with reference to the initial cell loading time. Over the next 15 hours, however, the sensed capacitances began to fall gradually, which is indicative of com- promised viability. This decrease is attributed to oxygen deprivation resulting from the presence of a gas impermeable glass cover slip over the sensor well. The cover slip served to maintain sterility of the sample well during the extended observation period. In order to conflrm the observed reduction in cell viability, the sensor well was replenished at the beginning of the second day with a fresh solution of growth medium and Alamar blue. As seen in Fig. 4.10, over the next 1 hour interval the capacitances increased and stabilized, possibly due to the fresh oxygen and nutrient supply. However, over the next few hours the capacitances decreased again, which is indicative of compromised viability. This result is conflrmed by the concurrent Alamar Blue measurements: minimal color change was observed, in contrast to mea- surements of the previous day. Alamar Blue % reduction values were found to be 0%, 0.95% and 7.15% at 0, 4 and 8 hours, respectively, with reference to the growth medium replenishment time on the second day. The transient drops in the sensed capacitance values at the microsample extraction times can be attributed to hydro- dynamic disturbances created by introducing the micropipette tip inside the culture well. Hydrodynamic efiects have the potential to disturb the ionic equilibrium re- sponsible for the biophysical origin of the cell-substrate capacitance. (The parasitic 62 capacitances inside the circuit are flxed and are not in uenced by disturbances in the ofi-chip environment. Therefore they are not responsible for the observed transient drops.) In this experiment, good correlation was observed between on-chip measure- ments of the capacitance between cells and substrate, and the Alamar Blue reduction measurements of cellular metabolism. 4.5.2.3 Experiment 3: Long term monitoring of cell viability in a closed undisturbed environment In this experiment BAOSMC were continuously monitored in a closed, undis- turbed environment on top of the sensor chip, without growth medium replenish- ment for a period of four days [biocompatible chip packaging was performed by M. Urdaneta]. This experiment was mainly performed to test the reliability of the biocompatible package and also consistency in the experimental results in compar- ison to the previous experiments with the bovine cells. This experiment was again performed using the gas-impermeable cover slip for sealing the sensor well. Fig. 4.11 shows a four day plot of the sensed capacitance as recorded by a sensor with a sensing electrode area of 40?40 ?m2. As shown in the flgure, the capacitance tracked the initial pre-adhesion and adhesion phases over the flrst few hours. Then the capacitance exhibited many uctuations, indicating ongoing cell activity. Over the last two days the time averaged value of the measured capacitance leveled out, indicating compromised viability and inactivity due to starvation and lack of oxygen. 63 0 20 40 60 80 1000 5 10 15 20 25 Computed Sensed Capacitance (fF) Time (h) pre?adhesion adhesion cells active & healthy cells compromised Figure 4.11: Long term measurement of cell capacitance with cells monitored in a closed undisturbed environment for a period of four days. The above interpretation of the experimental results is entirely based on the results obtained from previous experiments performed with BAOSMC wherein the initial capacitance increase within the flrst 8 hours of incubation was attributed to cell adhesion, sensed capacitances remaining high was attributed to good cell health and a decrease in sensed capacitance was attributed to compromised viability. These correlations between the time varying characteristics of the sensed capacitance, and the adhesion and viability properties of cells have already been established through visual observation and validation using Neutral Red and Alamar Blue dye tests performed in the previous experiments. 64 4.5.3 Tracking cell proliferation 4.5.3.1 Experiment and results This experiment was performed with MDA-MB-231 human breast cancer cells [cells acquired from Dr. H. Ghandehari and Dr. A. Nan] with the purpose of tracking cancer cell proliferation using the integrated capacitance sensors. So for this, flrstly a low cell density suspension was employed (in comparison to a cell density of 1?106 cells/mL employed in the previous experiments) in order to ensure that all the sensors do not get coupled to the cells during the adhesion phase. Secondly, the gas-impermeable cover slip was replaced with a gas permeable Breathe-Easy membrane (Fisher Scientiflc) allowing for gas exchange so that cell viability was not compromised due to oxygen deprivation [employing Breathe-Easy membrane was suggested by Dr. W.E. Bentley]. MDA-MB-231 human breast cancer cells are actively dividing cells with a short doubling time of 26 hours. MDA-MB-231 cells were cultured in a T25 ask in growth medium (pH 7.4 and bufiered for CO2) comprising 94.7% improved minimum essential medium (IMEM; Invitrogen), 5.0% fetal bovine serum (Invitrogen), and 0.3% penicillin-streptomycin (100x) (Invitrogen) by volume. The cells were allowed to grow in the ask until they were well into their exponential growth phase, which requires around 48 hours for the MDA-MB-231 cells. The cells were then detached by using 0.25% Trypsin/EDTA (Invitrogen). After cell detachment a suspension with an approximate density of 1?105 cells/mL was prepared. Cell density was determined using a hemocytometer. The sensor well was loaded with the cancer cell suspension using the procedure 65 stated at the beginning of this section. The sensor well was sealed using a gas permeable Breathe-Easy membrane (Fisher Scientiflc) allowing for gas exchange. Fig. 4.3(c) shows a photomicrograph of MDA-MB-231 cells cultured on the sensor chip. A total of 16 sensors (5 sensors of size 20?20 ?m2, 5 sensors of size 30?30 ?m2 and 6 sensors of size 40?40 ?m2) were monitored over a period of 18 hours. Fig. 4.12 shows sample responses obtained from 4 of the monitored sensors. For those sensors the time averaged value of the sensed capacitances remained low until the 6th hour of incubation which is indicative of the pre-adhesion phase during which the cells settle onto the surface passively, but have not yet made any adhesion contacts with the chip surface. The capacitance plots then showed increases during the 6th, 7th and 8th hours with difierent phase delays in the capacitance increases at the difierent sensor locations. The capacitance uctuations observed throughout the monitoringinterval(predominantlyinthepost-adhesionphase)havebeenattributed to interference noise coupling to the sensing node during the sensor evaluation phase. This is discussed further in Section 4.5.5. Table 4.1 displays the initiation time Ti, duration time Td, and overall change ?C, for the capacitance increases as observed from recordings of the 16 monitored sensors. For extracting Ti and Td values the sensor data was flrst smoothed using an algorithm employing Hamming flltering with a window size of 10 samples. Ti re ects the time at which the adhesion phase began and was quantifled as the flrst time point at which the sensed capacitance exceeded its starting value by more than two standard deviations: 66 0 2 4 6 8 10 12 14 16 180 24 68 1012 14 0 2 4 6 8 10 12 14 16 180 24 68 1012 14 0 2 4 6 8 10 12 14 16 180 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 180 2 4 6 8 10 12 Sensed Capacitance (fF) Time (h) sensor a sensor b sensor c sensor d pre?adhesion (Ti) adhesion (Td) Figure 4.12: Sample capacitance plots showing sensor response to MDA-MB-231 cell adhesion; sensors a and b have a sensing electrode area of 30?30 ?m2; sensors c and d have a sensing electrode area of 20?20 ?m2. Ti = tn () C(tn)??start ? 2 start for Tstart < tn < Tend (4.9) whereC(tn)isthesensed capacitance attimet = tn, Tstart andTend arethebeginning and ending of the observation period, and ?start and start are the mean and standard deviation of the capacitance during the time period t = 0 to Tstart. The gradients of all the sensed capacitance measurements vs. time were consistently observed to flrst rise, attain a peak value, and then fall over the periods during which the capacitances increased. Td was chosen to be the time interval after which the gradient @C=@t of the sensed capacitance dropped to zero or below after having attained its peak at t = tmax: Td = tn ?Ti () @C(tn)@t ? 0 for tn > tmax;Tstart < tn < Tend (4.10) 67 ?C values were computed from the difierence in the means of 10 capacitance samples acquired before and after the capacitance increase. Table 4.1: Initiation time Ti, duration time Td, and overall change ?C values obtained from sensed capacitance plots for all 16 monitored sensors across the three sensor groups. Cell loading performed at t = 0 hr. 20?20 ?m2 sensors 30?30 ?m2 sensors 40?40 ?m2 sensors Ti Td ?C Ti Td ?C Ti Td ?C (h) (min) (fF) (h) (min) (fF) (h) (min) (fF) 5.83 30 4.48 5.92 50 4.58 5.75 45 17.90 5.83 30 4.59 6.25 55 6.12 9.92 85 26.66 5.92 45 3.43 6.58 40 6.88 10.58 70 21.66 5.92 50 5.71 7.58 50 6.22 11.17 105 19.98 6.33 50 4.90 7.58 105 5.90 14.83 110 18.03 * * * * * * 16.17 110 22.59 All 5 of the 20?20 ?m2 sensors, all 5 of the 30?30 ?m2 sensors and just 1 of the 40?40 ?m2 sensors recorded a capacitance increase around the 6th, 7th and 8th hours of incubation. The sensor response to cell adhesion was similar to those recorded in previous experiments with BAOSMC. For example, in the experiment reported in section 4.5.1.2 a cell suspension of higher concentration was employed to ensure that all the sensors were covered with cells during adhesion, as a result of which all sensors recorded an increase in capacitance within the flrst 5 hours of incubation with a 3 hour spread in the Ti values Fig. 4.13 shows sample responses as obtained from 4 of the 6 40?40 ?m2 sensors that were monitored. The inset also shows relative positions of all the 40?40 ?m2 sensors (both monitored and not monitored) that are distributed over 68 an on-chip area measuring 120?400 ?m2. The location corresponding to each of the sensing electrodes where the capacitance increase was recorded has been indicated by the shaded squares in the respective sensor panels. Electrode locations with dashed outlines were not monitored during the experiment. As indicated from the plots and the timing information in Table 4.1, the sensed capacitances as recorded by sensors 2 to 6 of the 40?40 ?m2 sensor group remained low during the flrst 10 hour interval while all the sensors in the other two groups and 1 of the 40?40 ?m2 sensors (sensor 1) recorded a capacitance rise by the end of the 8th hour. This indicates that no cells had adhered to locations above sensors 2 to 6, since the cell density of the suspension was not high enough to cover the entire active area of the chip with cells. Sensors 2 to 6 then recorded capacitance increases during the 10th, 11th, 12th, 15th and 17th hours of incubation with a wider distribution in Ti values (spread over a period of 6.25 hours) which is suggestive of cell proliferation. This agrees well with the fact that MDA-MB-231 breast cancer cells are actively dividing cells with a short doubling time of approximately 26 hours [73]. As expected, the cells began to proliferate once they adhered to the surface. An interesting observation can be drawn from the sensed capacitance values recorded by sensors 3, 5 and 6. These sensors are located adjacent to each other on the chip. In Fig. 4.13 it can be seen that the sensed capacitance plots indicate a proliferation wavefront traveling from sensors 3 and 5 towards 6, over a span of 6 hours. Such a progression in the responses of the sensors located in a very small area over a relatively long duration is clearly suggestive of an underlying process of cell proliferation in that area. 69 0 2 4 6 8 10 12 14 16 180 5 10 15 20 25 30 0 2 4 6 8 10 12 14 16 180 5 10 15 20 25 30 0 2 4 6 8 10 12 14 16 180 5 10 15 20 25 30 0 2 4 6 8 10 12 14 16 180 5 10 15 20 25 30 sensor 3 sensor 4 sensor 5 sensor 6 Sensed Capacitance (fF) Time (h) proliferation (Td) pre?proliferation (Ti) sensors monitored sensors detecting capacitance increasesensors not monitored 123 6 45 123 456 123 456 123 456 Figure 4.13: Sample capacitance plots showing sensor response to MDA-MB-231 cell proliferation. The 10 squares in each panel display the relative locations of the 10 40?40 ?m2 sensors. The term \pre-proliferation phase" refers to the period before cell proliferation during which the sensors were not coupled to any cells. In this experiment, validation of the sensor response to cell proliferation was carried out through microscopic analysis at the end of the 18 hour long monitoring period. At that time it was found that all sensors were covered by well attached, adherent cells. Due to technical constraints, this microscopic analysis was per- formed only at the end of the monitoring because it imposed conditions which inter- rupted the ongoing measurement. Microscopic imaging of cells on the chip requires re ectance-mode optics. Fluid above the chip surface introduces optical distortion, so it must be removed prior to imaging, thus disrupting the experimental continuity. 70 4.5.3.2 Estimating cell doubling time Summarizing the experimental results, a total of 16 sensors (5 sensors of size 20?20 ?m2, 5 sensors of size 30?30 ?m2 and 6 sensors of size 40?40 ?m2) were monitored. Out of these 16 sensors, all 5 of the 20?20 ?m2 sensors, all 5 of the 30?30 ?m2 sensors and just 1 among the 40?40 ?m2 sensors recorded capacitance increases indicating cell adhesion. Later on, the remaining 5 of the 40?40 ?m2 sensors (sensors labeled 2 to 6 in Fig. 4.13) recorded capacitance increases during the 10th, 11th, 12th, 15th and 17th hours of incubation which are suggestive of cell proliferation. The Ti and Td values listed in Table 4.1 for the 40?40 ?m2 sensors provide an indirect measure of the cell proliferation rate and the sensed capacitance plots provide temporal traces of the actual proliferation process. The narrow 1.83 hour spread in the Ti values corresponding to the 20?20 ?m2 sensors, the 30?30 ?m2 sensors and sensor 1 in the 40?40 ?m2 group suggests an underlying process of cell adhesion occurring in those locations, while a wider 6.25 hour spread in the Ti values corresponding to sensors 2 to 6 suggests an underlying process of cell proliferation. Td values can be compared for sensors only within a group because of varying dynamic ranges across the three groups. The growth curve of the cells growing over the sensor region can be assessed by monitoring the cumulative number of sensors that have recorded capacitance increases with respect to incubation time, denoted by CS. Fig. 4.14 shows such a plot as obtained using the 16 sensors monitored during the experiment. Note 71 that the initial rise between hours 6 and 8 indicates adhesion, while only the later changes during hours 10 to 18 can be attributed to proliferation. The total number of sensors that record capacitance increase in response to cell adhesion (Na) is directly proportional to the initial number of cells that were seeded into the sensor well. The time required for the cumulative number of sensors that record capacitance increase in response to cell proliferation (Np) to equal Na (or CS = 2Na), can be considered to be an estimate for the cell doubling time. The following analysis assumes that a homogeneous array of equally distributed sensors on the chip was exposed to a homogeneous cell suspension. The statistical accuracy of the doubling time estimate and the growth curve for the entire on-chip cell population improves with the total number of sensors that are monitored (Nt). 6 8 10 12 14 160 2 4 6 8 10 12 14 16 18 Incubation time (h) CS = Cumulative number of sensors recording capacitance increase adhesion proliferation Na Figure 4.14: A plot of cumulative number of sensors that recorded capacitance increase (CS) vs. incubation time. A total of 16 sensors were monitored. In the current experiment, a total of 16 sensors (Nt = 16) with difierent electrodesizesandinter-electrodedistances weremonitored. The20?20?m2, 30?30 72 ?m2 and 40?40 ?m2 sensors have efiective inter-electrode distances of 82 ?m, 79 ?m and 88 ?m respectively. For simplicity, we approximate the set of 16 monitored sensors to be a homogeneous array of equally distributed sensors with an average inter-electrode distance of 83 ?m and an average electrode area of 30?30 ?m2. In Fig. 4.14, the value of Na for this experiment was found to be 11 at the end of flrst 10 hours of incubation. At the end of the next 8 hours of incubation the remaining 5 sensors detected an increase in capacitance that was attributed to the proliferation process (Np = 5). As a flrst order estimate, the rate of detecting capacitance increase (R) during the proliferation phase can be evaluated to be 5/8 sensors/hour. Here R is representative of the proliferation rate of the cells growing over the small on-chip area that corresponds to the monitored sensor locations. Assuming homogeneous proliferation, it would require another 9.6 hours for Np = Na = 11. This projects a value of 27.6 hours for the cell doubling time as measured from the initial cell loading time t = 0 hr. In order to measure the cell doubling time experimentally, the total number of sensors monitored (Nt) should be greater than or equal to twice the number of sensors detecting cell adhesion (Na). If this condition is met, the time required for the number of sensors detecting cell proliferation (Np) to equal Na re ects the actual cell doubling time irrespective of whether the cells are undergoing symmetrical or asymmetrical cell divisions. In the current analysis, the assumption of homogeneous cell proliferation was used only to project a value for cell doubling time, since in this experiment Nt (= 16) < 2Na (= 22). Often cells proliferate asymmetrically, especially in the case of cancer cells which are not contact inhibited. 73 It should be noted that the above analysis is speciflc only to the cells growing over the monitored region conflned to an area of 400?400 ?m2 (just 0.1% of the total sensor well area) where the sensors are located. The data obtained are not representative of the entire cell population in the sensor well. This is because cells growing at difierent locations in the sensor well (both on-chip and ofi-chip) might be proliferating at difierent rates depending upon their local microenvironment and their state in the cell division cycle. So the accuracy of this technique for quantifying proliferation of the entire on-chip cell population and estimating parameters such as cell doubling time can be signiflcantly improved by increasing the number of monitored sensors. 4.5.4 Detecting cell detachment In continuation with the previous experiment with the MDA-MB-231 cells, after the 18 hour monitoring period the cells were treated with 0.25% Trypsin/EDTA and the sensor chip was monitored for the next 4 hours. It was found that all the sensors recorded a decreased capacitance after treatment with trypsin which indicates cell detachment from the chip surface. Fig. 4.15 shows sample capacitance plots as recorded by 2 of the sensors before and after trypsinization. Table 4.2 displays the capacitance drop values as recorded by the 16 monitored sensors. This further conflrms the fact that cells were coupled to the chip surface at all monitored sensor locations prior to trypsinization. From Table 4.2 it can be seen that for some of the sensors, the capacitance drop values were greater than 74 0 5 10 15 200 5 10 15 20 250 5 10 15 20 0 5 10 15 Time (h) Sensed Capacitance (fF) sensor b sensor 5 post-trypsinization adhesion proliferation Figure 4.15: Sample capacitance plots showing sensor response to MDA-MB-231 cell detachment upon trypsinization; sensors b and 5 correspond to the same 2 sensors referred to in Figs. 4.12 and 4.13 respectively. Table 4.2: Capacitance drop values ?Cdrop recorded by the three sensor groups after trypsinization 20?20 ?m2 sensors 30?30 ?m2 sensors 40?40 ?m2 sensors ?Cdrop (fF) ?Cdrop (fF) ?Cdrop (fF) 4.26 5.34 10.87 4.51 7.03 11.21 4.85 5.42 11.55 7.26 5.80 9.49 5.44 5.42 8.70 * * 8.47 the capacitance rise values in Table 4.1. This is because those sensors recorded a gradual increase in the time averaged capacitance during the interval between the capacitance rise and fall. Also, the sensed capacitances do not return to their initial pre-adhesion levels after trypsinization. This could possibly be due to the residual 75 0 3 6 9 12 15 180 3 6 9 12 150 3 6 9 12 15 18 0 3 6 9 12 15 0 3 6 9 12 15 180 3 6 9 12 15 0 3 6 9 12 15 180 3 6 9 12 15 Sensed Capacitance (fF) Time (h) pre?adhesion adhesion sensor a sensor b sensor c sensor d Figure 4.16: Capacitance sensor response to adhesion of human colonic adenocar- cinoma cells (Caco-2) on the chip surface. All sensors measure 30?30 ?m2. Cell density employed for the experiment ? 1?106 cells/mL. materials that are deposited onto the chip surface by the cells. 4.5.5 Notesonexperimentscharacterizingcapacitancesensorresponse to cell phenomena 4.5.5.1 Repeatability, reusability and control experiments The proximity sensitivity of the capacitance sensors along with the shielding efiect of the growth medium produce responses to phenomena occurring only on the chip surface. The sensor chip has been tested with bovine aortic smooth muscle cells (BAOSMC) [17{20], human breast cancer cells [21] and human colonic adeno- carcinoma cells (Caco-2) (see Fig. 4.16). The sensor response to adhesion of cells on 76 0 5 10 15 200 1 2 0 5 10 15 200 1 2 0 5 10 15 200 1 2 0 5 10 15 200 1 2 0 5 10 15 200 1 2 0 5 10 15 200 1 2 sensor 1 sensor 2 sensor 3 sensor 4 sensor 5 sensor 6 Sensed Capacitanc e (fF) Time (h) Figure 4.17: Capacitance sensor response with sensor well loaded with growth medium alone, without any cells. Sensors 1 and 2 measure 40?40 ?m2, sensors 3 and 4 measure 30?30 ?m2, sensors 5 and 6 measure 20?20 ?m2. the chip surface has been consistent among the difierent cell types. In control ex- periments involving monitoring of chips without cells inside the incubator, with the sensor well containing the growth medium alone, and in actual experiments wherein it was found that there were no cells coupled to the chip surface, the sensors did not show any capacitance increase. For example, Fig. 4.17 shows sample sensor re- sponses from a control experiment in which the sensors were monitored with growth medium alone for a period of 22 hours inside an incubator. As can be seen, the sensed capacitance values remained below 1.5 fF throughout the monitoring period. The sensor responses exhibiting distinct capacitance risings as is shown in Figs. 4.8, 4.10, 4.11, 4.12, 4.13, 4.16 are characteristic of only the experiments in which the cells were present on the chip surface. 77 Cell culture on the chip results in strongly attached surface residues which greatly in uence baseline capacitance readings. Chip reusability for integrated cell capacitance sensing requires thorough cleaning of the chip surface and also a reli- able biocompatible package. The packaging technique using the photopatternable polymer that has been employed in this work has been found to be reliable for a maximum period of only four days. Alternate packaging strategies [by Dr. E. Smela, M.P. Dandin, M. Piyasena] for long-term reliability and chip surface cleaning solu- tions [by Dr. P. Abshire] are currently being explored for enabling chip reusability. 4.5.5.2 Capacitance uctuations In most of the experiments described previously, the sensed capacitances ex- hibited non-periodic uctuations before and after the adhesion phase (see Figs. 4.8, 4.10, 4.11, 4.12, 4.13 and 4.15). These uctuations were evaluated under difierent conditions for the three sensor groups; Table 4.3 summarizes the standard devia- tions ( 40, 30 and 20) as computed from measurements obtained in one of the experiments. The uctuations in response to cells after adhesion are 1-2 orders of magnitude higher than when the sensors were exposed to just growth medium or air. Such uctuations were consistently observed in the presence of cells. This has been attributed to increased capacitive crosstalk between the metal interconnects and the sensing node (node in the sensor circuit to which the sensing electrode is connected to in Fig. 4.1), due to increased dielectric constant of the passivation layer surface after cell adhesion. The sensing node during the evaluation phase is a 78 high impedance node and is therefore susceptible to interference noise coupling. The origin of the interfering noise responsible for the non-periodic uctuations in the capacitance recordings was traced back to the data acquisition card that was used to generate the clock signal for the sensor operation. This noise has now been eliminated by employing a clean clock signal generated using a function generator. Fig. 4.16 shows capacitance traces with signiflcantly reduced noise that were obtained in response to adhesion of Caco-2 cells on the chip surface. Table 4.3: Standard deviations of capacitance uctuations Stimulus 40 (fF) 30 (fF) 20 (fF) air 0.067 0.085 0.091 growth medium without cells 0.164 0.361 0.314 cell culture (pre-adhesion) 0.344 0.798 0.745 cell culture (post-adhesion) 3.463 2.454 2.511 4.5.5.3 In uence of biocompatible chip package on baseline capaci- tance The baseline capacitance readings have always been sensitive to the employed packaging technique and the packaging material. For example, the baseline capac- itances recorded at the start of the experiments presented in sections 4.5.1.1 and 4.5.2.1 were much higher than in the remaining experiments. This is because the material employed for packaging the chips in these experiments was not photopat- ternable, so they had to be manually patterned which resulted in residues on the 79 capacitance sensor array row cyclicshift register CDS units column cyclicshift register & timing control 200 ?m Figure 4.18: Photograph of the fabricated capacitance imager chip. chip surface (see Figs. 4.7, 4.9). In the remaining experiments, chips packaged using the photopatternable polymer were employed, which resulted in much cleaner chip surfaces and low baseline capacitance readings (see Figs. 4.8, 4.10, 4.11, 4.12, 4.13 and 4.15). 4.6 A capacitance imager chip based on the flrst generation sensor A capacitance imager test chip incorporating the flrst generation sensors in an array format was designed and fabricated. Fig. 4.18 shows a photograph of the fabricated chip. This is a tiny chip measuring an area of 1.5?1.5 mm2 and comprising an array of 400 sensors with a sensing electrode area of 30?30 ?m2. In addition to the sensor array the chip also comprised row and column cyclic shift registers for addressing the sensor pixels. All sensor pixels in a column are multiplexed onto a common column line by incorporating a rowselect switch in the sensor circuit output bufier. Below every sensor column is placed a CDS unit for readout. Fig. 4.19(a) shows a schematic of the CDS unit [74]. The purpose of the 80 CsVin sample sample phi_clamp V_clamp row_select reset phi_clamp sample evaluation phase (column select) (a) (b) reset Vout Figure 4.19: (a) Schematic of the Correlated Double Sampling (CDS) unit shared by a column of sensor pixels. (b) Timing diagram showing the control signals for sensing and readout. The signals reset and reset are the same as shown in Fig. 4.1 that control the sensor operation. CDS unit is to subtract the evaluated output voltage from reset output voltage so that only the difierence between the two is measured instead of the absolute value of the evaluated signal. This cancels DC ofiset errors in the readout path and also reduces low frequency correlated noise. The imager follows a row-wise select and a column-wise readout architecture. Fig. 4.19(b) shows the timing relation between 81 all the control signals responsible for the sensor operation and pixel readout. 0 5 10 15 20 05 1015 202 2.2 2.4 2.6 2.8 Row numberColumn number Imager output (V) Figure 4.20: Imager output representing the capacitance proflle of a metal probe placed in contact with the chip surface. The imager chip was bench tested by placing a metal electrode on the chip surface using a piezoelectric micropositioner. All the timing signals were generated using a SX microcontroller. Fig. 4.20 shows the imager output representing the capacitance proflle of the metal probe tip. 4.7 Summary A flrst generation CMOS capacitance sensor chip was designed to measure cell-substrate capacitance, a sensing modality that can be employed for on-chip investigation of cell phenomena. Biophysical factors contributing to the sensed ca- pacitance were identifled and discussed. Three groups of sensors with electrodes of difierent sizes were bench tested for calibration of the relationship between ca- 82 pacitance and measured voltage. In vitro test results from experiments with bovine heart muscle cells, human breast cancer cells and human intestinal cells showed that the sensors are able to detect cell-substrate capacitive variations in the fF range, with difierent sensing ranges for the three sensor groups. Results from the online monitoring experiments showed that the sensors were efiective in tracking cell adhe- sion, variations in cell viability and cell growth. Sensor response to changes in cell viability was validated by establishing good correlation between on-chip measure- ments of cell-substrate capacitance and concurrent assessments involving Neutral Red dye retention test and Alamar Blue dye reduction measurements. The CMOS-based integrated cell capacitance sensing technique demonstrated here ofiers an important monitoring capability for the development of cell-based miniaturized systems [75,76]. Such systems can be employed for a wide spectrum of applications including medical diagnosis, cytotoxicity assessment, drug screening and biocompatibility characterization. 83 Chapter 5 Second generation fully difierential rail-to-rail capacitance sensors for improved performance 5.1 Motivation for a fully difierential sensor The performance of the flrst generation single-ended sensors for cell capaci- tance measurement was limited by the parasitic efiects resulting from the growth environment and the sensor itself. The main contributors to such parasitics include stray capacitances (Cstray) from the measurement circuit (this includes the parasitic capacitances associated with the transistors and interconnects) and the standing capacitances (Cstanding) of the sensing electrodes along with the cell environment. In other words, sensor sensitivity and dynamic range (deflned as the ratio of the total signal swing to the noise resolution) were limited by the magnitude of the nodal parasitic capacitances CN1 and CN2 shown in Fig. 4.1. Also as mentioned in the previous chapter, the baseline capacitances were greatly in uenced by the residual packaging material on the chip surface which forms a part of the on-chip cell environment. From a futuristic perspective, when this sensor will be incorpo- rated in lab-on-chip (LOC) systems like cell clinics, the standing capacitances of the microstructures will also contribute to the sensing node capacitance causing a signiflcant capacitive ofiset at the input [25], thereby further reducing the sensor 84 Ci? senseelectrode referenceelectrode cell growthenvironment insulator Ci+fullydifferential sensor Vo+Vo? CstrayCstanding Ci+= Cstray+Cstanding+Csensed Csensed coupling fieldcells Figure 5.1: Fully difierential sensor block diagram and associated capacitances. dynamic range. The flrst generation single-ended capacitance sensor described in the previous chapter is based on the charge sharing principle [20]. The sensing node (node N1 in Fig. 4.1) in the measurement circuit is held in a high impedance state during readout (evaluation phase) which makes it susceptible to interference noise coupling. In addition to this, the presence of an aqueous ionic medium above the chip surface further increases capacitive crosstalk with the sensing node (see Section 4.5.5.2). A fully difierential sensor can resolvethe above mentioned problems concerning parasitic capacitance efiects and interference noise coupling arising in single-ended sensors. Fig. 5.1 shows a block diagram representation of the fully difierential sensor along with the associated capacitances. Ci? and Ci+ represent the input nodal capacitances. The difierential input capacitance is given by: ?Ci = Ci+ ?Ci? (5.1) Inthisdiscussionthecellsensingelectrodeandhencethesensedcapacitance(Csensed) will always be connected to node Ci+. Thus the total capacitance at node Ci+ is 85 the sum of Cstray, Cstanding and Csensed as shown in Fig. 5.1. The capacitance at node Ci? depends upon the capacitance compensation scheme implemented by the sensor as discussed below. Under ideally matched conditions, a linear difierential sensor eliminates efiects of Cstray and Cstanding on the sensor response. Difierential readout further improves sensor resolution by suppressing correlated noise and also increasing the output dynamic range. 5.2 Implementable capacitance compensation schemes A difierential capacitance sensor can be conflgured to follow difierent compen- sation schemes depending upon the application. The success of these schemes relies on matching between the various sensor components. In all the schemes discussed below, the capacitance at node Ci+ is as shown in Fig. 5.1. 5.2.1 Stray capacitance compensation scheme In this scheme node Ci? is left unconnected, compensating for Cstray alone [27]. Ci? = Cstray ) ?Ci = Cstanding +Csensed (5.2) This reduces sensor dynamic range as Cstanding at node Ci+ results in a positive capacitive ofiset at the input. This scheme can be employed in array-based applica- tions for cell detection where sensor dynamic range is not a critical requirement. 86 Ci? insulator Ci+fullydifferential sensor Vo+Vo? CstrayCstanding Csensed cells Cstray insulator fullydifferential sensor Cstray Cstanding Csensed CstrayCstanding cells insulator fullydifferential sensor Cstray Cstanding Csensed insulator CstrayCos cells (a) (b) (c) Ci? Ci+ Vo+Vo? Ci? Ci+ Vo+Vo? Figure 5.2: Implementable capacitance compensation schemes: (a) stray capaci- tance compensation scheme, (b) standing capacitance compensation scheme and (c) standing capacitance overcompensation scheme. 5.2.2 Standing capacitance compensation scheme In this scheme identical sensing electrodes are attached to both Ci+ and Ci? nodes [27]. Ci? = Cstray +Cstanding ) ?Ci = Csensed (5.3) This compensates for both Cstray and Cstanding. Replication of microstructures in 87 LOC systems along with the sensing electrodes also compensates for standing ca- pacitances arising from them. In conjunction with a high gain measurement circuit, this can enable very sensitive cellular measurements for applications like on-chip cytometry. The sensor dynamic range is higher than in the previous case. 5.2.3 Standing capacitance overcompensation scheme Instead of replicating sensing structures at both the input nodes, an ofisetting capacitor Cos can be attached to node Ci?. Cos > Cstanding results in a negative capacitive ofiset at the input. Ci? = Cstray +Cos ) ?Ci = Csensed +Cstanding ?Cos (5.4) The value of Cos should be chosen such that Cos?Cstanding is within the sensor input range. Cos can be formed by one of the inter-layer capacitances that ofiers best pos- sible matching in the low fF range. This scheme allows for an even higher dynamic range compared to the previous two schemes. Also, by choosing an appropriate value for Cos, the sensor can be made to operate in its mid-range where the sensor exhibits maximum linearity. This can be useful for applications where dynamic range and linearity requirements are critical. For example, cell viability monitoring requires larger area sensing electrodes which ofier a wider input capacitance range. In such applications, capacitance variations can signal important cell-related responses. 88 5.3 Fully difierential rail-to-rail capacitance sensor: design and op- eration Over the last decade, the charge based capacitance measurement (CBCM) technique has evolved as a popular sensing approach for measuring fF capacitances with aF resolution. The CBCM approach was primarily developed for interconnect capacitance characterization over a decade ago [45]. Since then it has been employed in several other applications including measurement of MOS device C-V characteris- tics [77], particle detection for industrial and biomedical purposes [24{27], and DNA sensing [78]. This work presents a sensor design tailored for on-chip cell monitoring which requires the circuit to measure capacitances over a few 10?s of fFs [20{22]. It extends previously reported CBCM circuits with single-ended output conflgurations [24{27] to a difierential output architecture. The fully difierential measurement circuit com- pensates for parasitic capacitances associated with on-chip cell sensing, increases sensor dynamic range, and suppresses correlated noise for improved assessment of cell phenomena [22,23]. The sensor circuit presented here employs a 3-phase clocking scheme that allows for gain tuning in accordance with the conditions in a partic- ular cell sensing application. These conditions include sensing electrode areas and conflgurations, and the dielectric parameters of the cell-substrate interface and the growth medium. Fig. 5.3 shows a schematic of the capacitance measurement circuit. It com- prises a standard CBCM front-end (M1-M4), a pair of complementary current mir- 89 Vo+ Vcm M1 Vdd Vss resetM2 M5 M7 M13 M8 M12 M11 eval resetreset reset B1Vo? Vcm Ci+Ci? senseelectrodereferenceelectrode Cint? Cint+ ?Io+?Io? couplingfield passivation layer reset B2 N +N? M14 M6 M10 M9 M3 M4 sample sample sample sample cell growthenvironment cells Figure 5.3: Fully difierential rail-to-rail capacitance measurement circuit design with sensor conflgured for standing capacitance compensation. rors (M5-M8 and M10-M13), current subtractors (M8-M9 and M13-M14), integra- tion capacitors (Cint? and Cint+) and rail-to-rail readout bufier ampliflers (B1 and B2). The CBCM unit comprises two identical pairs of minimum size NMOS and PMOStransistors (M1,M3) and(M2,M4), thatareswitchedusingtwonon-overlapping clock signals reset and eval. The sensing operation proceeds in three phases: reset, evaluation and sample. Fig. 5.4 shows the timing control signals corresponding to the three phases and the sensor response waveforms. During reset, Ci? and Ci+ are discharged to Vss through M1 and M2, and Cint? and Cint+ are reset to the common-mode voltage Vcm. During evaluation, Ci? and Ci+ are charged to Vdd?jVthpj through M3 and M4, where Vthp refers to the PMOS threshold voltage. The average values of the charging currents Ic? and Ic+ can be expressed as: 90 reset eval sample Vo+ V o? sensoroutputs Vdd Vss Vdd Vdd Vss Vss Tint Vcm Tsample Figure 5.4: Timing diagram illustrating the relation between the clock phases and sensor outputs. Ic? = Ci? ?Vstep ?f (5.5) where Vstep = Vdd?Vss?jVthpj and f = 1=T is the sensing cycle frequency. Ic? and Ic+ are amplifled by the current mirrors M5-M8 and M10-M13 with gain Ac and then subtracted by the transistors M8-M9 and M13-M14 to yield complementary difierence currents ?Io+ and ?Io?, whose average values can be expressed as: ?Io? = ?Ac ??Ci ?Vstep ?f +Ios? (5.6) where Ios? and Ios+ are the ofiset currents in the current subtractors. Cint? and Cint+ then integrate ?Io? and ?Io+ over a period Tint that is determined by the time interval between the negative edges of eval and sample (see Fig. 5.4) to yield sensor output voltages Vo? and Vo+. Here sample is a variable delay pulse that allows 91 for varying Tint. If the current pulses ?Io? are approximated to be ideal pulses of amplitudes ?Io? and widths Tpw such that the total charge delivered/removed to/from the integration capacitors remains the same, the sensor output voltages can be expressed as: Vo? = 1C int ? Z Tint 0 ?Io?dt+Vcm ??Ac ?Vstep ? TintT pw ? ?CiC int +Vos? +Vcm (5.7) where Tint ? Tpw, Cint is the value of the integration capacitance, and Vos? and Vos+ are the ofiset voltages from integration of Ios? and Ios+. The difierential output voltage ?Vo is given by: ?Vo = Vo+ ?Vo? ? 2?Ac ?Vstep ? TintT pw ? ?CiC int +?Vos (5.8) where ?Vos = Vos+?Vos?. Under ideal conditions when both sides of the difierential sensor are perfectly matched ?Vos = 0. In reality, ?Vos 6= 0 due to device mismatch efiects. From (5.8), Tint being variable allows for gain tuning. The relation between the sensor gain and Tint is actually nonlinear because ?Io? and ?Io+ are transient current pulses and not ideal rectangular pulses as considered above. The sample pulse also limits the sensor output voltage ofisets by limiting the durations over which Ios? and Ios+ are integrated. The sensor output is flnally bufiered by a pair of rail-to-rail bufier ampliflers B1 and B2, the details of which are presented in the later sections. 92 5.4 Shielded current routing bus architectures for implementing dif- ferential capacitance sensor arrays In order to achieve high density, sensor arrays require a small on-chip footprint for the measurement circuit. The area of the sensor circuit presented here can be signiflcant because of the large device sizes necessary for improved matching and for incorporation of additional calibration circuitry. Inorder torealize difierentialsensor arrays, we have developed a current routing bus architecture. Fig. 5.5 illustrates a column parallel array architecture along side the pixel circuit and the timing diagram. In this architecture each sensor pixel comprises four minimum size digital transistors (M1-M4). In Fig. 5.3 nodes N? and N+ connect the CBCM unit to the rest of the circuit, referred to as the sensor evaluation module (SEM). In Fig. 5.5 nodes N? and N+ extend to form current bus lines that allow a column of CBCM pixel units to share a common SEM comprising the complementary current mirrors, subtractors, integration capacitors and output bufiers. The timing diagram shown is for a row-wise select and a column-wise readout addressing scheme. Here row select and sample are active low, and reset is active high. All pixels are reset globally in every clock cycle. In order to address a particular row of pixels for sensing, its corresponding row select goes low enabling all sensors in the row for evaluation. The sampling of the SEM output is triggered by the negative edge of the sample signal. In a large sensor array implementing this architecture, the bus-to-substrate capacitances of the current bus lines and the source-to-bulk junction capacitances 93 Csb?s of transistors M3 and M4 in the sensor pixel contribute to the parasitic ca- pacitances at the nodes N? and N+. All these capacitances can sum up to 100?s of fF which degrades sensor evaluation speed. Also, the source-to-bulk junctions contribute to leakage currents from the current bus. For this purpose a larger area metal shield fabricated in a lower metal layer can be used for isolating the bus line from the substrate as shown in Fig. 5.5. The efiect of the bus-to-shield capacitance, the Csb?s and the source-to-bulk junction leakage are canceled out by driving the shield line and the N-wells of transistors M3 and M4 in each pixel with a potential that tracks the bus line potential. This is achieved using the bufier ampliflers B3 and B4 as shown in Fig. 5.5. This requires transistors M3 and M4 to be placed in individual N-wells. Such shielding also improves immunity of the current bus to substrate noise. In technologies with many metal layers the bus lines can be shielded from both top and bottom. 94 row address decoder (a) SEM Vo+ Vo? SEM SEM SEM SEM SEM sample address control and 3-phase clock generation eval reset address timing diagram reset row selectsample Tint (c) cross sectionof the shielded current bussubstrate Cbus-shield Cshield-sub bus line shieldline buffer (d) N+ N? B3 B4 busline shieldline reset Ci+ Ci?Csb row select Csb sensor pixel M1 M2 M3 M4 (b) N+ N? SEM Vo? Vo+ shieldcontact Vo+ Vo? Vo+ Vo? Vo+ Vo? Vo+ Vo? Vo+ Vo? Figure 5.5: A fully difieren tial capacitance sensor arra ywith acolumn parallel arc hitecture based on ashielded curren trouting bus. (b) Sc hematic of the sensor pixel. (c) Timing diagram for pixel readout. (d) Horizon tal view of the shielded curren tbus. 95 It is important to note that the input capacitances of the bufier ampliflers B3 and B4 used to drive the shield lines of the current bus, add on to the nodes N? and N+ in the capacitance measurement circuit. So the evaluation speed of a sensor incorporated in an array employing a shielded current routing bus will always be lower than that of an individual sensor. The advantages of the shielded current routing bus in terms of conserving the sensor evaluation speed and guarding the bus against leakage will be more prominent in a high density large sensor array, wherein the summation of all the parasitic capacitances associated with the current bus exceeds the value of the bufier input capacitance. The column parallel array architecture although achieves a high spatial res- olution of just four minimum sized digital transistors in every pixel, requires an entire row of SEM modules to be calibrated. The column parallel architecture also poses the challenge of pitch-matching the layout of the SEM module (along with additional calibration circuitry if incorporated) with the layout of a very narrow column of sensor pixels in a high density array scenario. An alternate solution to the problem of incorporating the measurement circuit in a sensor array is to mul- tiplex the entire two dimensional array of pixels onto a single SEM module. This simplifles array calibration and eliminates the challenge of layout pitch-matching, but at the cost of increasing the sensor pixel foot-print and decreasing the array readout speed. Fig. 5.6 illustrates the single SEM sensor array architecture along side the pixel circuit and the timing diagram. In this architecture each sensor pixel comprises six minimum size digital tran- sistors (M1-M4, M3?, M4?). In Fig. 5.6 nodes N? and N+ extend to form current 96 bus lines that allow an entire array of CBCM pixel units to share a common SEM. The timing diagram shown is for a row-wise select and a column-wise readout ad- dressing scheme. Here row select, column select and sample are active low, and reset is active high. All pixels are reset globally in every clock cycle. In order to address a particular pixel for sensing, its corresponding row select flrst goes low followed by the column select enabling the sensor for evaluation. The sampling of the SEM output is triggered by the negative edge of the sample signal. The current bus is shielded in the same way as described in the column parallel architecture case. High density sensor arrays with reduced electrode areas will require thinning of the chip passivation layer in order to improve input signal strength and dynamic range. Capacitance sensor arrays can achieve flll factors (the fraction of surface area covered with sensors) over 90% in advanced CMOS processes with more metal layers since the active elements comprising the measurement circuit can be placed directly underneath the sensing electrodes. Such high density capacitance imager chips can generate a time sequence of capacitance \images" providing more insight into the on-chip cell behavior. Such maps can be used to track the adhesion and growth processes of cells cultured on-chip by 1) monitoring the time-varying signals recorded from sensors that become covered as the cells adhere and show a spreading behavior [20,21] and 2) tracking the cumulative number of sensors that are coupled to cells over time [21]. 97 Vo+ Vo? N+ N? sensor evaluation module busline shieldline B3 B4 row address decoder column address decoder reset Ci+ Ci?Csb row selectcolumn select Csb sensor pixel address control and 3-phase clock generation resetevalsample timing diagram resetrow select column selectsample Tint M1 M2 M3 M4 M3? M4? (a) (b) (c) horizontalcross sectionof the current bussubstrate Cbus-shield Cshield-sub bus line shieldline buffer (d) N+ N? Figure 5.6: A fully difieren tial capacitance sensor arra ywith asingle SEM arc hitecture based on ashielded curren trouting bus. (b) Sc hematic of the sensor pixel. (c) Timing diagram for pixel readout. (d) Horizon tal view of the shielded curren tbus. 98 5.5 Test chip version 1: Individual sensor characterization 5.5.1 Sensor design and simulation The sensor circuit as shown in Fig. 5.3 was designed in a 0.5 ?m, 2-poly, 3- metal standard CMOS technology for operation with a 3 V supply. The circuit was designed and laid out with a mirror gain Ac = 8. A base transistor (M5 and M10 in Fig. 5.3) size of width 1.75 ?m and length 1.75 ?m was chosen for the design. The sensor output was bufiered by a pair of rail-to-rail operational ampliflers connected in voltage follower conflguration. The custom rail-to-rail op-amp was designed using the topology shown in Fig. 5.7. It consists of a rail-to-rail input stage, a summing circuit, and a rail-to-rail output stage with feedforward class-AB control [79]. The op-amp design and operation will be discussed in Chapter 7. Vdd +- +- Vss VoutVin+Vin- Vb1 Vb2 Ibias M1 M2M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 Figure 5.7: The custom wide-swing op-amp used for bufiering the sensor output. 99 22 26 30 ?1 ?0.5 0 0.5 1 Time (?s) Sensor Outputs (V) ?20 ?10 0 10 20 ?2 ?1 0 1 2 Input Capacitance ?Ci (fF) Differential Output Voltage ?V o (V) Tint = 195 ns T int = 60 ns calibration curves (a) (b) Vo+ Vo_ Figure 5.8: (a) Simulated transient response of the difierential sensor for ?Ci be- tween 0 and 20 fF. (b) Simulated sensor static response curves with corresponding calibration curves for Tint = 60 ns and 195 ns. The extracted layout was simulated using Cadence Spectre for an input ca- pacitance range of ?20 fF. Input standing capacitances were assumed to be 10 fF. A sensing cycle period of 10 ?s was used. The circuit employs 200 fF poly1-poly2 integration capacitors. The rail-to-rail bufier ampliflers were designed to drive ofi- chip loads. The bufier op-amp circuit ofiers an input capacitance of ? 140 fF. This results in an efiective integration capacitance Cint ? 340 fF. Fig. 5.8(a) shows the simulated transient response of the sensor after integra- tion and bufiering. ?Ci was varied between 0 fF and 20 fF in steps of size 1 fF. Fig. 5.8(b) shows the static response curves obtained from transient simulations of the extracted layout for Tint = 60 ns and 195 ns. The mid-range sensitivities of the sensor were estimated to be 90 mV/fF and 130 mV/fF for Tint = 60 ns and 195 ns, 100 respectively, from the plots. The flgure also shows corresponding linear calibration curves, which were computed in order to estimate nonlinearity errors for the sensors. The slope of the calibration curve fi = fli, where fli is the slope of the static response curve at the ith simulation point. An estimate of nonlinearity error [24] of the sensor can be expressed as: NLE = q (fli ?fi)2 fi ?100 (5.9) The nonlinearity errors were estimated to be 9.8% and 12.1% for Tint = 60 ns and 195 ns respectively. 5.5.2 Chip fabrication and testing The sensor test chip comprised test structures with the measurement circuit connected to metal3 (top-most metal layer) plates conflgured according to the stray capacitance compensation scheme [22]. Fig. 5.9(a) shows a photomicrograph of one such test structure. The chip comprised 5 such test structures with the metal3 plates varying in dimensions such that the metal3-to-substrate capacitances varied across the input range of 0 to 20 fF. Fig. 5.9(b) shows a test structure connected to interdigitated electrodes. This structure compensates for stray capacitances and overcompensates for standing capacitances such that the operation range of the measurement circuit lies in the linear portion of the static response curve. This can be useful for certain cell monitoring applications with critical linearity requirements [22]. The chip also included 3-phase clock generation circuitry with the reset and 101 Figure 5.9: Chip photomicrographs showing (a) a test structure with stray capaci- tance compensation for measuring the standing capacitance of a metal3 electrode, (b) a test structure overcompensating for the standing capacitance of an interdigi- tated metal3 (top-most layer) electrode using an interdigitated metal1 (bottom-most layer) electrode. eval signals generated using a standard 2-phase nonoverlapping clock generator [80]. The sample signal was generated by delaying the eval signal using a voltage controlled variable delay element comprising a current-starved inverter chain. Five of these chips were fabricated and tested. Fig. 5.10 presents the test results showing the sensor output voltage distribu- tions among the 5 test structures across the 5 chips for Tint = 60 ns and 195 ns. The standing capacitance values of the metal3 plates were estimated using the process run parameters provided by the vendor. The solid lines are the best flt curves for the measured data points, the slopes of which were used to estimate the detection sensitivity. The plots indicate successful sensor operation with mean sensitivities of 91 mV/fF and 126 mV/fF for Tint = 60 ns and 195 ns, respectively. The output 102 0 5 10 15 200 0.5 1 1.5 2 2.5 3 Test Structure Standing Capacitances ?Ci (fF)Measured Differ ential Output Voltage ?V o (V) Tint = 195 ns Tint = 60 ns ?Ci = 3.68 fF ?Ci = 7.62 fF ?Ci = 11.45 fF ?Ci = 15.11 fF ?Ci = 19.01 fF 0 5 15 201.2 1.7 2.2 2.7 3.2 Measured noise (mV) ?Ci (fF) 10 Figure 5.10: Test results showing the mean and standard deviations of the measured sensor output voltages in correspondence to the standing capacitances of metal3 electrodes for the 5 test structures across the 5 chips. The inset shows the ouput noise levels as measured from one of the sensor chips. voltage spread among identical test structures across the difierent chips can be at- tributed to process mismatch. The proposed array architectures require individual calibration for only the SEM components of every chip in order to compensate for such mismatches. The sensor output noise is expected to vary with ?Ci. The inset located in Fig. 5.10 shows the output noise levels recorded from one of the test chips for difierent values of ?Ci with Tint = 195 ns. The minimum and maximum noise levels were measured to be 1.7 mV and 3.0 mV for ?Ci values of 3.68 fF and 11.45 fF respectively which translates to corresponding capacitance resolutions of 14 aF and 24 aF. With a difierential output voltage swing of 5 V, the maximum achievable 103 sensor output dynamic range evaluates to 69.4 dB. 5.6 Test chip version 2: Sensor array and shielded current bus testing 5.6.1 Chip design A second version of the difierential capacitance sensor chip was designed to test the shielded current bus architecture for the sensor array. The column parallel architecture shown in Fig. 5.5 was employed for this purpose. For this chip, the core of the Sensor Evaluation Module (SEM) comprising the complementary current mirrors, subtractors and the integration capacitors was retained as in the previous version. But the bufier op-amps B1 and B2 in Fig. 5.3 were now replaced by smaller, single-stage rail-to-rail ampliflers. The new bufier amplifler circuit is shown in Fig. 5.11. Vdd Vdd Vss VssVin Vout Figure 5.11: A single stage rail-to-rail amplifler circuit comprising class-AB difier- ential cells employed for bufiering the sensor output. 104 It is a single stage amplifler comprising two complementary class-AB difier- ential cells along with current mirroring stages that drive the output node from rail-to-rail [81]. The amplifler is appropriate for bufiering the capacitance sensor because it preserves rail-to-rail operation, has a small on-chip footprint and ofiers a low input capacitance. This is important for conserving sensor sensitivity since the input capacitances of B1 and B2 appear in parallel with the integration capacitors. The bufier amplifler designed in the 0.5 ?m technology ofiers an input capacitance of 60 fF. This results in an efiective integration capacitance Cint ? 260 fF in the capacitance measurement circuit. 5.6.2 Chip fabrication and testing test column current bus sensor evaluation module complementary current mirrors integration capacitors rail-to-rail buffer amplifier (a) (b) 200 ?m 50 ?m Figure 5.12: (a) Photograph of the fabricated difierential capacitance sensor test array employing column parallel shielded current bus lines. (b) Photomicrograph of a single Sensor Evaluation Module (SEM). Fig. 5.12(a) shows a photograph of the fabricated difierential capacitance sensor test array. It follows a column parallel architecture (shown in Fig. 5.5) with 105 Table 5.1: Summary of the difierential input capacitances corresponding to the 16 test structures in every column. Test Test Capacitance Calibration structure capacitance compensation capacitance No. type type ?Ci (fF) 1 m3-sub a stray 0 2 m3-sub stray 5.07 3 m3-sub stray 10.31 4 m3-sub stray 15.38 5 m3-sub stray 20.19 6 m3-sub stray 25.31 7 m3-sub standing 0 8 m3-sub stray -5.07 9 m3-sub stray -10.31 10 m3-sub stray -15.38 11 m3-sub stray -20.19 12 m3-sub stray -25.31 13 2f-m3 b stray ? 14 4f-m3 c stray ? 15 2f-m3 (Ci+) d standing 2f-m1 (Ci?) e overcompensation ? 16 4f-m3 (Ci+) f standing 4f-m1 (Ci?) g overcompensation ? h am3-sub: metal3-substrate coupling capacitance at Ci+ b2f-m3: 2-flnger metal3 interdigitated capacitance at Ci+ c4f-m3: 4-flnger metal3 interdigitated capacitance at Ci+ d2f-m3 (Ci+): 2-flnger metal3 interdigitated capacitance at Ci+ e2f-m1 (Ci?): 2-flnger metal1 interdigitated capacitance at Ci? f4f-m3 (Ci+): 4-flnger metal3 interdigitated capacitance at Ci+ g4f-m1 (Ci?): 4-flnger metal1 interdigitated capacitance at Ci? h?: ?Ci values estimated from test results are listed in Table 5.2 8 test columns. Each column comprises 16 test structures sharing a common SEM placed at the bottom. Each test structure comprises a 4-transistor CBCM front 106 end connected to a test capacitance. Table 5.1 provides details regarding the test capacitances created in each of the 16 structures in every column. Structures 1 to 6 and 8 to 12 were conflgured for stray capacitance compensa- tion and were used for sensor calibration in which the difierential input capacitances varied between -25 fF and +25 fF, the target input range for the difierential sen- sor. These structures comprised single metal3 (top-most metal layer) electrodes of varying sizes as can be seen in Fig. 5.12(a). The values of the single electrode metal3-substrate calibration capacitances were estimated using the process run pa- rameters provided by the vendor. Structures 13 and 14 were also conflgured for stray capacitance compensation, but comprised 2-flnger and 4-flnger metal3 interdigitated electrodes respectively. Structures 15 and 16 were conflgured for standing capac- itance overcompensation. In structure 15, Ci+ node was connected to a 2-flnger metal3 interdigitated electrode and Ci? node was connected to a 2-flnger metal1 (bottom-most metal layer) interdigitated electrode. In structure 16, Ci+ node was connected to a 4-flnger metal3 interdigitated electrode and Ci? node was connected to a 4-flnger metal1 interdigitated electrode. The ?Ci values corresponding to struc- tures 13 to 16 were estimated from test measurement results as will be described in section 5.7. The single stage rail-to-rail amplifler shown in Fig. 5.11, in addition to bufier- ing the sensor output as B1 and B2, was also used as bufiers B3 and B4 (shown in Fig. 5.5) for driving the shield lines in the sensor test array. Therefore every SEM block comprised 4 of these bufier ampliflers (B1-B4). Fig. 5.12(b) shows a photomicrograph of a single SEM block. 107 0.5 1?3 ?2 ?1 0 1 2 3 gain = 150 mV/fF 0.5 1?3 ?2 ?1 0 1 2 3 Time (ms) Differential Output Voltage ?V o (V) 0.5 1?3 ?2 ?1 0 1 2 3 gain = 200 mV/fFgain = 100 mV/fF (1) (2) (3) (4) (5) (6) (8) (9) (10) (11) (12) (1) (1) (2) (2) (3) (3) (4) (4) (5) (5) (8) (8) (9) (9)(10) (10)(11) (11) Figure 5.13: Recorded transient responses from one of the fabricated capacitance measurement circuits. The numbers in the parenthesis correspond to the test struc- tures listed in Table 5.1. In addition to the sensor test array, the chip also included 3-phase clock gen- eration circuitry with the reset and eval signals generated using a standard 2-phase nonoverlapping clock generator [80]. The sensors were operated at a clocking fre- quency of 1 kHz, which is appropriate for monitoring the low frequency capacitive behavior of cells, our current target application. The sample signal was generated by delaying the eval signal using a voltage controlled variable delay element com- prising a current-starved inverter chain. Five of these chips were fabricated and tested. Fig. 5.13 shows the transient responses as recorded from one of the capacitance measurement circuits when the ?Ci was varied between -25 fF and +25 fF, by 108 ?20 ?10 0 10 20?3 ?2 ?1 0 1 2 3 Differential Input Capacitance ?Ci (fF) Measured Differential Output Voltage ?V o (V) sensor 1sensor 2 sensor 3sensor 4 sensor 5sensor 6 sensor 7sensor 8 Figure 5.14: Measured transfer functions corresponding to the 8 SEMs from one of the test chips with sensor gain set to 200 mV/fF. switching across the calibration structures 1 to 6 and 8 to 12. Sensor responses were recorded for the 3 difierent sensor gains of 100, 150 and 200 mV/fF. The sensor gains were varied by delaying the sample pulse by 14 ?s, 38 ?s and 112 ?s respectively. The maximum achievable gain was measured to be 200 mV/fF. Based upon noise measurements, the sensor circuit incorporated in the test array employing the shielded current bus was able to achieve a resolution of 15 aF and an output dynamic range of 65 dB. Fig. 5.14 shows the sensor transfer curves as measured from one of the test chips. The 8 curves correspond to the transfer functions of the 8 SEMs connected to their respective test columns. The data points correspond to calibration structures 109 ?30 ?20 ?10 0 10 20 30?3 ?1.5 0 1.5 3?30 ?20 ?10 0 10 20 30 ?3 ?1.5 0 1.5 3?30 ?20 ?10 0 10 20 30 ?3 ?1.5 0 1.5 3 Test # 7: ?Ci = 0 fF?(?V o) = 151 mV?(?V o) = 585 mV Test # 7: ?Ci = 0 fF?(?V o) = 190 mV?(?V o) = 784 mV Test # 7: ?Ci = 0 fF?(?V o) = 221 mV?(?V o) = 968 mV Differential Input Capacitance Mean Differe ntial Output Voltage Across Sensors (V ) (c) gain = 200 mV/fF (b) gain = 150 mV/fF (a) gain = 100 mV/fF ?Ci (fF) Figure 5.15: Averaged transfer functions across all the SEMs across all the 5 fab- ricated chips corresponding to sensor gains of 100, 150 and 200 mV/fF. The error bars indicate the spread in the sensor outputs due to process and device mismatch efiects. The insets display the mean ?(?Vo) and standard deviation (?Vo) values of the sensor outputs corresponding to test structure 7 (with ?Ci = 0 fF) as listed in Table 5.1. The dotted red lines are the linear calibration curves used to estimate the sensor gain values. 1 to 6 and 8 to 12 as listed in Table 5.1. The curves were recorded with the sensor conflgured to achieve a maximum gain of 200 mV/fF. Fig. 5.15 shows the averaged transfer functions across all the SEMs in all the 5 fabricated chips corresponding to sensor gains of 100, 150 and 200 mV/fF. The error bars indicate the spread in the sensor outputs corresponding to the flxed values of input calibration capacitances corresponding to test structures 1 to 6 and 8 to 12. As can be observed the sensor output spread increases with increasing gain. 110 This is due to the integration of the sensor output ofiset currents Ios? and Ios+ over longer durations for achieving higher gains. The inset located in each of the panels in Fig. 5.15 displays the mean ?(?Vo) and standard deviation (?Vo) values of the sensor outputs corresponding to test structure 7 which is conflgured for standing capacitance compensation with ?Ci = 0 fF. The ?(?Vo) and (?Vo) values can be employed to estimate the average input capacitance ofiset and the average input capacitance ofiset spread across all the fabricated sensors. For example, in the plot corresponding to gain = 200 mV/fF in Fig. 5.15, the ?(?Vo) and (?Vo) values for test structure 7 are 221 mV and 968 mV respectively. These translate into an average input capacitance ofiset of 1.1 fF and an average input capacitance ofiset spread of 4.84 fF respectively. The output ofiset voltage spread across the difierent sensor modules tested above can be unacceptable for applications where in the usable dynamic range of the sensor circuits is critical. Such applications will require output ofiset cancelation for optimizing sensor performance. We next present an approach to solve this problem by incorporating oating gate transistors in the capacitance measurement circuit. 5.7 Test chip version 3: Capacitance sensor incorporating oating gate trimming for mismatch compensation Floating gate transistors have been previously employed for mismatch com- pensation and ofiset cancelation in CMOS imagers [82], current sources [83{85], autozero ampliflers [86,87], adaptive comparators [88] and ADCs [89]. They can 111 Vdd Vss Is Vd Vin Vtun Itun Iinj floating gate transistor Ios M0 Vosg M0 (a) (b) Ccont Ctun Figure 5.16: (a) Representing output ofiset current in a PMOS transistor as a gate ofiset voltage. (b) Conceptual illustration of a oating gate transistor. be employed as in-circuit trimming elements for either creating or canceling ofisets. Advantages of employing oating gate transistors for this purpose include program- ming capability, long-term retention and standard CMOS fabrication. Fig. 5.16(a) provides a conceptual representation of the ofiset cancelation scheme that can be applied to the capacitance measurement circuit presented here. The PMOS transis- tors M9 and M14 in the current subtractors of the sensor circuit (see Fig. 5.3) are represented by the transistor M0 in Fig. 5.16(a). Ios represents the ofiset currents Ios? and Ios+ owing in the corresponding current subtractors. The ofiset current Ios can be translated into the gate ofiset voltage Vosg as shown in Fig. 5.16(a). By modifying M0 to be a oating gate transistor, Vosg and therefore the sensor output ofiset currents Ios? and Ios+ can be canceled. Fig. 5.16(b) provides a conceptual illustration of a oating gate transistor. The gate of this transistor is completely isolated by SiO2, a high quality insulator. This provides a non-volatile charge storage node at the transistor gate. In a 2- 112 poly CMOS process, the poly1 layer is employed for the oating gate and poly2 is employed for the control gate. The control and the oating gates together form the capacitor Ccont. The capacitor Ctun shown in 5.16(b) is a PMOS-capacitor, with its gate connected to the oating gate, and the drain, source and bulk connected to the tunneling terminal Vtun. The oating gate transistor can be programmed using two difierent mecha- nisms: ? Impact Ionization Hot Electron Injection [86,87]: In this mechanism a high source-to-drain voltage is imposed on the transistor because of which electrons are created at the drain edge of the drain-to-channel depletion region via hot- hole impact ionization. These electrons in the presence of a high enough vertical electric fleld, gain su?cient kinetic energy to cross the Si-SiO2 barrier thereby getting injected onto the oating gate. This mechanism results in a negative shift in the gate ofiset voltage Vosg. In Fig. 5.16(b) the rate of injection can be controlled by the source-to-drain current Is. The injection current Iinj is modeled using the empirical relation [90]: Iinj = fi?Is ?exp ? ? fl(V gd +?) 2 +?(Vgd ?Vgs) ? (5.10) where Is is the source-to-drain current, Vgd and Vgs are the gate-to-drain and gate-to-source voltages, and fi, fl, ? and ? are fltting parameters. ? Fowler-Nordheim Tunneling [91]: In this mechanism a very high electric fleld 113 is imposed on the PMOS-capacitor Ctun so that the efiective width of the po- tential barrier between the poly-Si gate and the Si below the gate oxide is reduced to a few nanometers. This allows for the electrons in the conduction band of the poly-Si gate to tunnel through the oxide bandgap to the Si con- duction band on the other side of the oxide. This fleld-assisted tunneling is called Fowler-Nordheim Tunneling. This mechanism results in a positive shift in the gate ofiset voltage Vosg. The tunneling current Itun depends on the gate oxide voltage and can be approximately expressed as [90]: Itun = ?Itun0 ?W ?L?exp ? ? VfV ox ? (5.11) where Itun0 is a pre-exponential current, W and L are the width and length of the PMOS tunneling capacitor, Vox is the gate oxide voltage and Vf is a constant which varies with oxide thickness. 5.7.1 Sensor circuit design incorporating oating gate transistors The capacitance measurement circuit employed in the version 2 chip was mod- ifled to incorporate the oating gate transistors M9 and M14 as shown in Fig. 5.17. Each oating gate transistor is connected to a dedicated injection/tunneling (I/T) structure that programs the sensor output ofiset by enabling and controlling the injection or tunneling processes. 114 Vo+ Vcm reseteval resetB1 Ci+ Ci? Cint + resetreset Vo? Vcm Cint ? B2 samplesample samplesample AVdd Vss sampleI/T PE? Vbinj Vbtun Vss IVdd sampleI/T PE+ Vbinj Vbtun VssIVdd Vfgp Vfgn Control Control M9 M14 injection/tunnelingstructu res reset Figure 5.17: Sc hematic of the oating gate capacitance measuremen tcircuit with injection/tunneling (I/T) structures. Con trol signals emplo yed in the I/T structures include: (a) sampl e, for sync hronizing oating gate trimming pro cess with sensing clo ck cycle, (b) I=T ,for selecting bet ween injection or tunneling pro cesses, (c) PE ?, for enabling the trimming pro cess. 115 The capacitance sensor circuit and the I/T structures employ separate supply rails AVdd and IVdd respectively. During normal operation, both AVdd and IVdd are set to 3 V. During programming, the sensor circuit supply AVdd is retained at 3 V, and IVdd is raised to a higher voltage. Fig. 5.18 illustrates the design and operation of the I/T structure for perform- ing oating gate trimming. The I/T structure employed here was previously devel- oped for performing adaptation in a oating gate quantizer inside a ash ADC [89]. In Fig. 5.18, M9 is the oating gate PMOS transistor in the current subtractor of the capacitance measurement circuit. As can be seen the oating gate is shared by two other transistors Mi1 and Mt1 in the I/T structure. Mi1 is the injection transistor and Mt1 is the tunneling transistor. Mi2 serves as a current source for controlling the rate of injection in Mi1. The capacitor and diode pairs, (Ci, Di) and (Ct, Dt) form charge pumps for generating the high voltages necessary for enabling injection and tunneling. The (Ci, Di) pair forms a negative charge pump for gener- ating a high source-to-drain voltage for Mi1 and the (Ct, Dt) pair forms a positive charge pump for generating a high voltage across the gate oxide of Mt1. The termi- nal Vbtun can be raised above the nominal supply voltage during tunneling. For the test chip presented here the Vbtun pin in the padframe comprised ESD (Electrostatic Discharge) protection diodes. So in order to prevent these diodes from turning on, IVdd also had to be raised along with Vbtun while performing tunneling. In order to further ensure that injection in transistor Mi1 was fully disabled when IVdd was raised to 9 V, the current source transistor Mi2 was turned ofi whenever tunneling was enabled. 116 Vo+ Vcm reset B1 Cint+ reset sample sample AVdd sample I/T PE+ Vbinj Vbtun Vss IVdd Vfgp Control sampleMi2 Mi1Mt1 M9 CiCt Dt Di off-chipcomparator floatinggate ni nicnt ntc DAQ Figure 5.18: Schematic showing the design and operation of the injection/tunneling (I/T) structure. Charge injection and tunneling were performed in small steps in synchrony with the sample phase of the sensing clock cycle. The sample signal served as the control pulse for performing injection or tunneling. The control logic block shown in Fig. 5.18 is responsible for enabling or disabling programming, and for selecting between injection or tunneling. During programming the supply voltage IVdd is raised to 5 V for performing injection and 9 V for performing tunneling. The logic block drives the charge pumps by employing high voltage bufiers that are powered by IVdd. When injection is disabled (or during normal operation when IVdd = 3 V), node nic sits at 5 V (normal operation: 3 V) and node ni is at approximately 0.65 V (built-in potential of the diode Di). With this condition, the source-to-drain 117 voltage across Mi1 is not su?cient to enable impact-ionized hot electron injection. When injection is enabled, node nic goes to ground and ni is pulled to -5 V + 0.65 V. This increases the source-to-drain voltage of Mi1 enabling a small amount of charge to be injected onto the oating gate. The duration over which the node ni stays at -5 V + 0.65 V depends upon the source-to-drain current set by Mi2, since this current gets integrated over the junction capacitance of diode Di thereby continually reducing the source-to-drain voltage of Mi1 until Di turns on. When tunneling is disabled or during normal operation, node ntc sits at ground causing node nt to be at Vbtun - 0.65 V. This does not impose a su?cient voltage across the gate oxide of Mt1 for tunneling to happen. When tunneling is enabled, node Vbtun is set to 8 V, ntc is pulled to 9 V causing nt to be pulled to 8 V - 0.65 V + 9 V. This creates a high enough voltage across the gate oxide of Mt1 to induce tunneling. For the 0.5 ?m CMOS technology employed here, tunneling requires a minimum voltage of around 15 V across the gate oxide. 5.7.2 Chip fabrication and testing The chip designed for testing the oating gate difierential capacitance sensor comprised the same test array as in version 2 but with 4 test columns instead of 8. The chip was fabricated in a 0.5 ?m, 2-poly, 3-metal standard CMOS process. Each column comprised the same 16 test structures as described in Table 5.1, sharing a common SEM incorporating the modifled capacitance sensor with the oating gate transistors and the I/T structures. Fig. 5.19 shows a photomicrograph of a modifled 118 complementary current mirrors and subtractorswith floating gate transistors integration capacitors rail-to-rail buffer amplifier injection andtunneling structures 50 ?m Figure 5.19: Photomicrograph of the modifled version of the Sensor Evaluation Module incorporating the oating gate transistors and the I/T structures. SEM block employed in this version of the chip. Five of these chips were fabricated and tested. The sensor output ofiset cancelation was performed with test structure 7 (con- flgured for standing capacitance compensation with ?Ci = 0 fF, see Table 5.1) se- lected. This was the test case which exhibited an unacceptable spread of 968 mV across the sensor outputs in version 1 of the sensor chip. Before programming, all the chips were exposed to UV radiations in order to erase all existing charges on the oating gate. After this, for every chip, all the 4 SEMs were selected for program- ming with the tunneling mode enabled. For the I/T structure fabricated in the 0.5 ?m CMOS process appreciable amount of tunneling was observed when Vbtun was set to 8 V and IVdd was raised to 9 V. Tunneling was continued until all the sensor outputs Vo? and Vo+ settled to arbitrary voltages well below the common mode voltage Vcm which was set to 1.5 V (mid-supply voltage). Vbtun was otherwise tied 119 to ground during normal operation. Later on injection was enabled sequentially for each of the outputs Vo? and Vo+ for every sensor. For this IVdd was set to 5 V and Vbinj was adjusted to have a low rate of injection in order to visually observe the progress of the output ofiset cancelation on an oscilloscope. Injection was enabled until the output voltages Vo? and Vo+ settled close to Vcm resulting in ?Vo ? 0 V. For programming this version of the chip an ofi-chip strobe comparator (strobed by sample signal) was employed to form the feedback control loop shown in Fig. 5.18 while performing injection. The output of the comparator was continuously monitored by a data acquisition software in order to generate the PE? (program enable) signal for the I=T control block. To summarize the programming procedure, the tunneling mechanism was flrst employed for an initial global course tuning of the output voltages Vo? and Vo+ to arbitrary values below Vcm. This was followed by injection for flne tuning of Vo? and Vo+ to voltages close to Vcm. Fig. 5.20 shows the individual sensor transfer curves as measured from two of the test chips after performing oating gate trimming at the operating point corresponding to test structure 7. The 4 curves in each of the plots correspond to the transfer functions of the 4 SEMs connected to their respective test columns. The data points correspond to test structures 1 to 6 and 8 to 12 as listed in Table 5.1 that are conflgured for stray capacitance compensation, with ?Ci values varying between -25 fF and +25 fF. The curves were recorded with the gain set to 200 mV/fF. On comparing Fig. 5.20 with Fig. 5.14 it can be seen that there is an appreciable degree of mismatch compensation over the entire operating range for all 120 ?20 ?10 0 10 20?3 ?2 ?1 0 1 2 3 ?20 ?10 0 10 20?3 ?2 ?1 0 1 2 3 sensor 1sensor 2 sensor 3sensor 4 sensor 1sensor 2 sensor 3sensor 4 chip 1 chip 4 Measured Differential Output Voltage ?V o (V) Differential Input Capacitance ?Ci (fF) Figure 5.20: Measured transfer functions from two of the test chips after oating gate trimming at the operating point corresponding to test structure 7. the sensors. Also, linearity of the transfer functions has signiflcantly improved after performing oating gate trimming. The sensors in chip 1 exhibited a small degree of gain mismatch in comparison to those in chip 4 due to process mismatch efiects. Fig. 5.21 shows the averaged transfer functions across the 4 SEMs for each of the 5 fabricated chips after oating gate trimming. The error bars indicate the spread in the sensor outputs corresponding to the flxed values of input calibration capacitances corresponding to test structures 1 to 6 and 8 to 12. The insets shown alongside the corresponding curves in Fig. 5.21 displays the mean ?(?Vo) and stan- dard deviation (?Vo) values of the sensor outputs corresponding to test structure 121 7 which is conflgured for standing capacitance compensation with ?Ci = 0 fF. This is the operating point at which the oating gate trimming was performed. On evaluating the data from all the 5 chips, the average values of ?(?Vo) and (?Vo) corresponding to the test structure 7 are 27 mV and 34 mV respectively. Considering a maximum achievable sensor gain of 200 mV/fF, this translates into an average input capacitance ofiset of 0.13 fF with an average input capacitance ofiset spread of 0.17 fF. So the oating gate trimming of the difierential capacitance sensors resulted in an average reduction of 88% in ?(?Vo) and 96.5% in (?Vo) with reference to the result obtained using the previous version of the measurement circuit which did not incorporate oating gate trimming. The average ?(?Vo) and (?Vo) values stated above are indicative of the accuracy and precision of the employed oating gate trimming mechanism. These values can be signiflcantly improved by employing on-chip oating gate comparators with extremely low input ofisets [88] and on-chip generation of the I=T and PE? signals for feedback control during programming. The dotted red lines in each of the panels in Fig. 5.21 are the linear calibration curves for the sensors in each of the test chips. These curves were used to estimate the difierential input capacitance ?Ci values corresponding to test structures 13 to 16. These are listed in Table 5.2. Structures 13 and 14 were conflgured for stray capacitance compensation, and comprised 2-flnger (dimensions: length = 19.6 ?m, width = 9.8 ?m, spacing = 11.2 ?m) and 4-flnger (dimensions: length = 19.6 ?m, width = 4.2 ?m, spacing = 4.9 ?m) metal3 interdigitated electrodes respectively. Structures 15 and 16 were conflgured for standing capacitance overcompensation. 122 ?20 ?10 0 10 20?3 ?1.5 0 1.5 3 ?20 ?10 0 10 20?3 ?1.5 0 1.5 3 ?20 ?10 0 10 20?3 ?1.5 0 1.5 3 ?20 ?10 0 10 20?3 ?1.5 0 1.5 3 ?20 ?10 0 10 20?3 ?1.5 0 1.5 3 Mean Differenti al Output Voltage Across Sen sors In Each Of The 5 Chips (V) Differential Input Capacitance ?Ci (fF) gain = 208 mV/fF Test # 7: ?Ci = 0 fF?(?V o) = -7 mV?(?V o) = 51 mV (a) chip 1 gain = 159 mV/fF Test # 7: ?Ci = 0 fF?(?V o) = 30 mV?(?V o) = 25 mV (b) chip 2 gain = 197 mV/fF Test # 7: ?Ci = 0 fF?(?V o) = 68 mV?(?V o) = 46 mV (c) chip 3 gain = 210 mV/fF Test # 7: ?Ci = 0 fF?(?V o) = 17 mV?(?V o) = 30 mV (d) chip 4 gain = 190 mV/fF Test # 7: ?Ci = 0 fF?(?V o) = 30 mV?(?V o) = 18 mV (e) chip 5 (13) (14) (15) (16) (13) (14) (15) (16) (13) (14) (15) (16) (13) (14) (15) (16) (13) (14) (15) (16) : Calibration points corresponding to test structures 1 to 6 and 8 to 12: ?C i Estimation points corresponding to test structures 13 to 16 Figure 5.21: Averaged transfer functions across the 4 SEMs in each of the 5 chips after oating gate trimming. The error bars indicate the spread in the sensor outputs after programming. The insets display the mean ?(?Vo) and standard deviation (?Vo) values of the sensor outputs corresponding to test structure 7. The dotted red lines are the linear calibration curves employed to estimate the ?Ci values corresponding to structures 13 to 16. 123 Table 5.2: Difierential input capacitance values corresponding to test structures 13 to 16 as estimated from measurement results. Test chip 1 chip 2 chip 3 chip 4 chip 5 # ?Ci (fF) ?Ci (fF) ?Ci (fF) ?Ci (fF) ?Ci (fF) 13 6.99 6.73 7.11 6.93 6.80 14 8.41 8.30 8.55 8.48 8.33 15 -9.65 -9.97 -9.94 -9.89 -9.76 16 -9.19 -9.60 -9.45 -9.42 -9.34 In structure 15, Ci+ node was connected to a 2-flnger metal3 (top-most metal layer) interdigitated electrode and Ci? node was connected to a 2-flnger metal1 (bottom- most metal layer) interdigitated electrode. In structure 16, Ci+ node was connected to a 4-flnger metal3 interdigitated electrode and Ci? node was connected to a 4-flnger metal1 interdigitated electrode. 5.8 Summary A second generation of fully difierential rail-to-rail CMOS capacitance sensors were designed, fabricated and tested. The core sensor circuit employs the CBCM technique for linearly mapping difierential input capacitances to rail-to-rail difier- ential output voltages. The difierential sensor can compensate for all the stray capacitances arising from the cell growth environment and the measurement circuit itself that are responsible for degrading the performance of single-ended sensors. The difierential readout increases output dynamic range and suppresses correlated noise, thereby improving sensor resolution. The presented array architecture based on the shielded current routing bus en- 124 ables the measurement circuit to be employed in high density sensor arrays without compromising performance, and in addition it simplifles calibration and improves immunity to noise and junction leakage. The sensor array architecture with on-chip gain-tuning can provide the capability for readout of heterogeneous sensor arrays, which is potentially useful for simultaneously studying difierent aspects of cell be- havior on a single chip platform. The sensor operation was demonstrated by measuring on-chip test capaci- tances comprising single and interdigitated metal electrodes conflgured using dif- ferent capacitance compensation schemes. The measurement circuit was tested in individual sensor conflguration and also in a test array employing the shielded current routing bus. After successful demonstration of the sensor operation, the measurement circuit was modifled to include oating gate trimming for mismatch compensation. The sensor output ofiset cancelation was performed using a com- bination of impact ionized hot electron injection and Fowler Nordheim tunneling mechanisms. The performance metrics of the sensor including the dynamic range, sensitivity, resolution, post-trimming output voltage ofiset and ofiset spread that were obtained from bench test results have been found to be appropriate for on-chip cell monitoring applications. 125 Chapter 6 Conclusions: Part I On-chip capacitance sensing was demonstrated as a promising label-free tech- nique for integrated cell sensing applications, speciflcally for, characterizing cell- surface attachment, monitoring cell health and tracking cell growth. Several exper- iments were conducted using the flrst generation capacitance sensors, with living cells cultured on the sensor chips. The sensors were observed to consistently exhibit a distinct response to the cultured cells as shown in the experiments described in Chapter 4. A flrst attempt at providing a circuit-based model was made for explain- ing the sensor responses to biological cells as was observed during the experiments. The model was developed based on the low-frequency dielectric properties of cells as discussed in the Biophysics literature. The claims made with regard to the monitoring capabilities of the cell ca- pacitance sensing approach were entirely based on validation results obtained from either post-experiment visual inspection of cells on the sensor chips or standard cell biology techniques (such as Neutral Red retention test and Alamar Blue reduction test ) that were able to assess cell properties without interfering with the capac- itance measurements. A more thorough validation of the cell capacitance sensing technique will require performing time-lapse microscopy of the cells on the sensor chips over long monitoring intervals. Microscopic imaging of cells on the chip re- 126 quires specialized re ectance-mode optics. So a microscope with optics corrected for intervening uid needs to be assembled inside an incubator and suitable chip package needs to be developed for allowing concurrent imaging of cells on top of the chip surface along with sensor response monitoring. In addition to providing encouraging experimental demonstrations, the flrst generation single-ended sensors posed problems with regard to parasitic capacitance efiects and noise coupling. Also the sensor output range was limited to a few 100s of mVs and the sensor spatial resolution was limited by 12 transistors, 4 of which were digital switches and the remaining 8 performed analog operations. In order to resolve the above issues, a second generation fully-difierential rail- to-rail capacitance measurement circuit was developed. In comparison to the flrst generation single-ended sensor, the second generation difierential sensor exhibits lin- ear capacitance versus output voltage characteristic, ofiers higher sensitivity, higher resolution, higher dynamic range and better immunity to interference noise cou- pling. The nonlinear distance versus output voltage characteristic resulting from the single electrode conflguration (employed in the flrst generation sensor operating as a proximity detector) was found to be appropriate for tracking surface attachment of cells. The difierential sensor presented here can also employ the single electrode conflguration to take advantage of this feature. (Employing interdigitated electrodes for on-chip cell sensing will require passivation layer thinning in order to overcome penetration depth limitations imposed by the passivation layer thickness in stan- dard CMOS processes.) The exibility of conflguring the difierential sensor using difierent capacitance compensation schemes ofiers a more versatile solution for the 127 cell sensing problem by allowing custom-tailoring according to the application re- quirements. The shielded current routing-based sensor array architecture developed in this work enables the measurement circuit to be employed in high density sensor arrays without compromising performance. The sensor array architecture in combi- nation with the on-chip gain-tuning feature can provide the capability for readout of heterogeneous sensor arrays, which is potentially useful for simultaneously studying difierent aspects of cell behavior on a single chip platform. The difierential sensor circuit was also modifled to incorporate in-circuit oat- ing gate trimming in order to compensate for the device and process mismatch efiects in the fabricated sensors. The oating gate trimming further improves the sensor performance by canceling output voltage ofisets and linearizing the transfer function characteristics. The integrated cell capacitance sensing platform developed in this disserta- tion can enable cell-based lab-on-a-chip (LOC) systems for high speed, automated and real-time monitoring of biological cells. Such systems can be very useful for performing interesting scientiflc investigations of cellular properties (related to ad- hesion, viability and proliferation) at a microscopic level. The temporal information present in the sensor responses can provide new insights with regard to individual cell behavior. The demonstrated cell sensing approach can also be employed in sev- eral industrial applications such as automated drug screening and biocompatibility characterization of materials. 128 Part II A CMOS POTENTIOSTAT FOR CONTROL OF INTEGRATED MEMS ACTUATORS 129 Chapter 7 Research Background 7.1 First generation cell clinics The flrst generation prototype of the cell clinics microsystem comprises an ar- ray of lidded microvials for conflning single cells or small cell groups at the sensing sites corresponding to an array of CMOS bioampliflers for amplifying weak extra- cellular potentials from electrogenic cells [5]. The purpose of the lidded microvials is to conflne the living cells and isolate them within controllable microenvironments. The bioampliflers provide a means of monitoring the electrical activity of cells within the controlled environment. Fig. 1.1 in Chapter 1 provides a conceptual illustration of the microsystem. The microvial lids are opened and closed by actuator hinges employing an electroactive polymer that changes volume due to electrochemical ox- idation and reduction. At the macro-scale, such reactions are controlled using an instrument known as a potentiostat. In the flrst generation of cell clinics these con- trol signals were supplied by an external potentiostat instrument [5]. This research enables system miniaturization of cell clinics by integrating the necessary driver circuitry for in situ control of the microactuators right on top of the CMOS chip. 130 7.1.1 Cell clinics microstructure: conflguration and operation The closing action of the microvial lids is accomplished by bending of the hinge, as shown in Fig. 7.1 (a). SU8 microvial lid gold hinge PPy inner SU8 layer outer gold layer electrical contact layer 0V -1V 50 ?m 50 ?m (a) (b) Figure 7.1: (a) Schematic illustration of a lidded microvial with bilayer hinge. Dark layer represents PPy [Illustration based on an original flgure courtesy of Y. Liu and Dr. E. Smela]. (b) Photomicrograph of the fabricated cell clinics microvials [Photomicrographs courtesy of Dr. M. Christophersen and Dr. E. Smela]. Theelectroactivepolymeremployedinthecellclinicsmicroactuatorsispolypyr- role doped with dodecylbenzenesulfonate, PPy(DBS), a well-studied material whose properties depend on the imposed potential and the resulting oxidation level [92,93]. The hinge?s upper layer is made of the conjugated polymer PPy(DBS). The lower layer is made of gold. The gold layer acts as both a structural layer and an electrical contact to the PPy. It serves as an inert electrode to electrochemically address the electroactive polymer. When immersed in an electrolyte (in our case 0.1 M NaDBS), PPy changes volume according to the applied potential, while the gold does not. Reducing the polymer draws hydrated Na+ cations into the polymer matrix, in- creasing the volume of the fllm, whereas oxidizing it expels the ions, decreasing the volume [94]. Also associated with the change in the electronic state of the polymer 131 (change in oxidation level) is a change in color [92]. The potentiostat controls the direction and extent of the electrochemical reaction, which in turn determines the degree of expansion or contraction of the polymer fllm. The out-of-plane expansion of thin fllms in aqueous Na+-containing electrolytes is substantial, approximately 30% between the fully oxidized and reduced states, as established with techniques such as AFM and mechanical profllometry [92,94{96]. The bilayered actuator struc- tures can be miniaturized using standard microfabrication techniques [5,94,97{99]. The volume changing property of electroactive polymers has also been exploited to realize micro uidic valves [100]. The closing and opening of the microvial lids in the cell clinics microsystem re- quires a control voltage operating between 0 V and ?1 V with respect to a Ag/AgCl reference potential [101]. The polymer is in the reduced state at ?1 V and becomes oxidized at 0 V vs. Ag/AgCl [94,97]. Fig. 7.1 (b) shows photomicrographs of two fabricated microvials with their lids in the opened and closed positions correspond- ing to the two electrochemical states of the polymer. The electrochemical reaction requires a maximum current density on the order of 10 pA/?m2 for actuation. 7.1.2 Prototype testing The flrst generation cell clinics prototype comprised a CMOS chip with an array of bioampliflers connected to on-chip cell sensing electrodes and an array of MEMS structures comprising lidded microvials. The ampliflers were tested by recording the extracellular electrical potentials from bovine aortic smooth mus- 132 cell sensing electrode SU8vial bioamplifier module lid lid Figure 7.2: Prototype microstructures fabricated on a custom CMOS bioamplifler chip [Photographs courtesy of Y. Liu and Dr. E. Smela]. cle cells on a packaged bioamplifler chip (without any MEMS structures) [5,19]. The MEMS structures were tested by fabricating prototype microstructures on the bioamplifler chip. The function of the bilayer actuators was demonstrated by placing the chip in an electrolyte solution, making electrical connection to the chip surface through a micromanipulator probe, and applying voltages between 0 and ?1 V vs. Ag/AgCl using an external potentiostat. Fig. 7.2 shows the resulting actuation of the microvial lid [fabrication and testing was performed by Y. Liu]. A vial is positioned around a gold-plated sensing electrode, visible as a small square. The PPy/Au bilayer hinge was successfully actuated, as shown by the difierent positions of the lid in these images. 7.2 Potentiostat basics 7.2.1 Electrochemical cell An electrochemical cell [64] comprises a set of electrodes immersed in an electrolyte. An electric current resulting from a net movement of charged species through the cell gives rise to an electrochemical reaction. Electrons are the charge 133 carriers in the electrodes and ions constitute the charge carriers in the electrolyte. An electrochemical cell typically comprises a set of three electrodes: ? Working electrode (WE) [64]: This provides the surface on which the elec- trochemical reaction occurs. It is made of an inert material such as gold or platinum. ? Reference electrode (RE) [64]: This is the electrode with reference to which a control potential is applied to the WE for the electrochemical reaction to occur. It is to be connected to a high impedance node allowing no current to ow through it. Saturated Calomel Electrode (SCE) and Silver/Silver Chloride (Ag/AgCl) electrodes [64] are the standard REs used in laboratory applica- tions. Field applications normally employ pseudo REs made of inert materials. ? Counter electrode (CE) [64]: The current that enters the electrolyte through the WE exits through the CE or vice versa. Laboratory applications employ inert conductors such as platinum or graphite as CEs. Field applications employ another piece of WE as the CE. In the cell clinics microsystem the on-chip PPy/Au microactuator behaves as the WE in the electrochemical cell. For the flrst generation prototype testing, the PPy/Au bilayer was actuated by employing an ofi-chip Ag/AgCl RE and an ofi- chip Ag CE, in 0.1 M NaDBS electrolyte. 134 WE CERE Potentiostat VWR electrolyte electrochemical cell control voltage measured current Figure 7.3: An illustration showing an electrochemical cell connected to a potentio- stat instrument. 7.2.2 Potentiostat instrument A potentiostat is an electronic instrument used to control the reaction in an electrochemical cell [102]. It controls the current between the WE and CE, so that the potential VWR of the WE relative to the RE follows a required control voltage. At any instant the potential applied to the WE is maintained at the control voltage, irrespective of the ongoing electrochemical reaction. Fig. 7.3 shows the connection between an electrochemical cell in a typical three electrode conflguration and a potentiostat. 135 Chapter 8 Integrated Potentiostat Design Previous reports on integrated potentiostats have demonstrated their utility in electrochemical sensors for detecting minute concentrations of biochemical an- alytes [103{108]. The potentiostats primarily served as current measurement in- struments for precise low-level current detection (nA to pA) with low noise. In recent years a new class of applications have emerged that employ electrochemi- cal actuators for capturing, manipulating, and positioning of objects in the micro- regime [109,110]. The control of such microactuators requires a modifled design for the potentiostat, giving it the ability to robustly drive relatively high currents (?A to mA) with accurate voltage control and low output distortion. This work demonstrates such a CMOS potentiostat and its use for in situ control of the elec- trochemical oxidation level, and thus the volume, of an electroactive polymer fllm. The integrated control technique can enable complete miniaturization of a variety of electrochemical microsystems for micromanipulation [98,110], cell clinics [5,6,99], drug delivery [111], and combinatorial electrodeposition of materials [112]. For the cell clinics application the potentiostat serves to drive the PPy/Au bilayer microac- tuators. Lid actuation requires the application of a control voltage, which was provided by an external potentiostat instrument in the flrst generation of cell clin- ics. In order to reduce system complexity, this research contributes a custom VLSI 136 potentiostat for control of, and integration with the MEMS structures. 8.1 Implemented potentiostat architecture All potentiostats follow a common control architecture, but with various con- straints or additional circuit elements depending on the application. A potentiostat mainly comprises two functional units: (i) a core control unit that maintains a set desired potential difierence between the working and reference electrodes by sourcing or sinking a current through the counter electrode, the value of which is regulated by a feedback mechanism, and (ii) a current-sensing unit that measures the current owing through the cell for electrochemical analysis or detection [102]. Microac- tuator control requires a control unit that exhibits good accuracy, robust driving, and stability, while current-measurement requirements are less demanding, since the currents are relatively large. One of the key constraints on the potentiostat for our target cell clinics is minimal footprint on the chip, since the chip must carry out many other functions as well. In order to minimize area and power requirements, we have elected to integrate a single, compact driver for controlling an array of ac- tuators, rather than a separate driver for each actuator. The control circuit follows the architecture of a single-ended amperometric potentiostat [29,30,102] Fig. 8.1(b) illustrates the working (WE), reference (RE) and counter (CE) electrodes, and the associated circuitry. The circuit architecture implemented is that of a traditional single-ended amperometric potentiostat [113]. Fig. 8.1(b) illustrates the connection between the electrodes and the associated control circuitry. 137 OP1 OP2 OP3 CE RE ZC ZW WE Vcontrol actuator array Rs Rs Rmeas Vmeas VWR Z Rsoln Re-cCe-c Inter-electrodeimpedance (a) (b) Figure 8.1: (a)A model for the interelectrode impedance. (b) Potentiostat circuit for integration with the microactuators. The control circuitry comprises three operational ampliflers: ? OP1 bufiers the electrochemical reference potential in the feedback control loop. It provides a high input impedance to the RE, keeping the reference chemical reaction at equilibrium and allowing no current to ow through it. ? OP2 sources/sinks the current specifled by the control voltage to/from the counter electrode to enable the reduction/oxidation reaction. ? OP3, along with the ofi-chip feedback resistance Rmeas, operates as a current- to-voltage converter for measuring the current owing through the electro- chemical cell, and also provides a virtual ground potential at the WE. Current measurement using Rmeas is required to determine the voltage range for actu- ation from oxidation and reduction peaks obtained using cyclic voltammetry. The value of Rmeas is determined by the range of currents to be measured. 138 ZC denotestheimpedancebetweenCEandRE,andZW denotestheimpedance between WE and RE. The electrical impedances ZC and ZW are formed by a series combination of the solution resistance Rsoln and the electrode impedance Ze?c that arises from charging of the double layer capacitance (modeled by Ce?c) and electron transfer resistance (modeled by Re?c) at the electrode-electrolyte interface. This is illustrated in Fig. 8.1 (a). The transfer function from the source control voltage Vcontrol to the electro- chemical cell potential VWR can be written as: VWR Vcontrol = A2ZW A2ZW +2(ZC +ZW) (8.1) whereA2 isthegainofop-ampOP2. Thecircuitensuresthattheelectrochemicalcell voltage VWR tracks the source control voltage Vcontrol, provided A2 is high enough. 8.2 Wide swing op-amp design for microactuator control The potentiostat implementation requires an op-amp that satisfles the follow- ing speciflcations for driving electrochemical actuators: ? High gain (>50 dB) to maintain the desired electrochemical cell potential. ? Phase margin > 60? for stable operation. ? Rail-to-rail inputs and outputs to maximize the range of the electrochemical potentials that can be applied. ? High current handling capability for parallel driving and control of actuator 139 arrays. For example, the PPy(DBS)-based electrochemical reaction requires peak current densities on the order of 10 pA/?m2 for actuation. In this case the op-amp could be required to source or sink currents up to 1 mA while driving an array of PPy(DBS)/Au actuators [94]. ? Low output distortion for accurate voltage tracking during electrochemical control. A custom wide-swing op-amp has been designed using the topology shown in Fig. 8.2. It consists of a rail-to-rail input stage, a summing circuit, and a rail-to-rail output stage with feedforward class-AB control [79]. The NMOS input pair M1-M2 and the PMOS input pair M3-M4 together constitute the rail-to-rail input stage. In the low common-mode input voltage range the PMOS input pair is active, in the intermediate common-mode input voltage range both NMOS and PMOS input pairs are active and in the high common-mode input voltage range the NMOS input pair is active. In order to preserve the rail-to-rail capability, the complementary input pairs are loaded with folded cascodes formed by transistors M14-M17 and M18-M21. The diode-connected transistors M5 and M6 in the input stage provide a constant voltage source across the complementary input transistor pairs in order to reduce transconductance variation across the input common mode voltage range. This is required for optimal frequency compensation and reduced signal distortion. The output stage is biased in the class-AB mode by maintaining a constant voltage difierence between the gates of the output transistors M29 and M33. The biasing is provided by a feedforward class-AB control circuit formed by transistors M28 140 and M32. The class-AB control is combined with the summing circuit formed by transistors M14-M17 and M18-M21. Transistors M24-M25 form a oating current source. The class-AB control sets up two translinear loops, M26-M29 and M30-M33 which flx the voltage between the gates of M29 and M33. The rail-to-rail output stage with feedforward class-AB control provides a good compromise between power e?ciency and output signal cross-over distortion for a given supply power [79]. The output transistors M29 and M33 are suitably sized for supporting high current drives of up to 1 mA. Vdd +- +- Vss VoutVin+Vin_ Vb1 Vb2 Ibias M1 M2M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 Figure 8.2: Rail-to-rail operational amplifler constituting the potentiostat. The op-amp circuit was designed and fabricated in a commercially available 0.5 ?m, 2-poly, 3-metal standard CMOS technology for a supply voltage of ?1:5 V. Table 8.1 summarizes the performance metrics [80] for the op-amp obtained from bench testing. 141 Table 8.1: Performance metrics of the operational amplifler Parameter Value Unit On-chip area 0.021 mm2 Open loop gain 66 dB 3 dB bandwidth 3.5 kHz Phase margin 85 ? Unity gain frequency 2 MHz CMRR 110 dB Slew rate (RL=1 M?, CL=95 pF) 7.5 V/?s 8.3 Potentiostat test chip The potentiostat chip implements the control circuit of Fig. 8.1(b) connected to on-chip microelectrodes: 6 WEs measuring 100?100 ?m2 each (for a total area of 6?104 ?m2, a CE measuring 400?800 ?m2, and a RE measuring 50?800 ?m2. Fig. 8.3(a) shows a photomicrograph of the fabricated chip. counter electrode reference electrode working electrodes potentiostat module 200 ?m potentiostat chip polymer patterned for bond wire insulation DIP40 package well for containing electrolyte (a) (b) Figure 8.3: (a) Photomicrograph of the fabricated chip comprising the potentiostat module integrated with the microelectrodes constituting the electrochemical cell. (b) Photograph of a fully packaged potentiostat test flxture after postprocessing. 142 The RE is placed close to the WEs in order to minimize the voltage drop across the RE/WE electrolyte resistances. The CE area has been maximized in order to allow su?cient current ow during actuation. The WEs mimic the actuator array that will be employed in the cell clinics; after post-processing of the chip they comprise the same materials and have the same areas as the cell clinic actuators. The chip, measuring 1.5?1.5 mm2, was fabricated in a commercially-available 0.5 ?m, 2- poly, 3-metalCMOSprocess. Theon-chipareaofthepotentiostatcircuitis7.07?104 ?m2 (6% of the active chip area). The electrodes were fabricated using the top metal layer in the CMOS process, with the aluminum exposed using glass cuts, or openings in the passivation layer which are commonly used to create bond pads for external connections via bonding wires. In addition to the internal connections shown in Fig. 8.3(a), the electrodes are connected to bond pads that permit external connections to be made during electrodeposition of polymer fllms. The driver circuit can be employed to control the actuators either in parallel for all actuators or sequentially for individual actuators. Sequential control requires the working electrodes to be addressed through a switching network that is controlled by a decoder circuit. Since the potentiostat can also be employed for electrodeposition, sequential control can enable on-chip combinatorial electrochemistry. 143 Chapter 9 CMOS/MEMS Integration & Testing 9.1 Validatingpotentiostatoperationbycyclinganofi-chipPPy(DBS) fllm in a standard electrochemical cell The potentiostat chip was tested for actuation of an ofi-chip PPy(DBS) fllm of area 2 cm2 with thickness 2000 ?A on a gold-covered silicon substrate in 0.1 M NaDBS solution [PPy(DBS) sample was prepared by M. Urdaneta. Electrochemical cell was set up by M. Urdaneta]. PPy(DBS) is electrochromic, so it changes color during oxidation and reduction [92]. The cycling test was performed by connecting the working electrode pin of the on-chip potentiostat to an exposed gold region of the PPy(DBS) sample, the reference electrode pin to an external Ag/AgCl electrode, and the counter electrode pin to an external graphite electrode [Chip testing was performed along with M. Urdaneta]. A signal generator was used to ramp the control potential linearly at 100 mV/sec between 0 and ?1 V. As shown by the photographs in Fig. 9.1, in every cycling period the fllm was observed to change from salmon color (oxidation at 0 V vs. Ag/AgCl), to transpar- ent (reduction at ?1 V vs. Ag/AgCl), conflrming the electrochemical reaction of the fllm [Color changes were observed along with M. Urdaneta]. The color observed at 0 V is due to optical interference, and is thus a function of the PPy fllm thickness. 144 applied potential: 0 V vs. Ag/AgCl applied potential: -1 V vs. Ag/AgCl exposed gold spot (a reference for color comparison) PPy(DBS) Figure 9.1: Color change observed during cycling of the PPy(DBS) fllm using the on-chip potentiostat [Photographs were captured along with M. Urdaneta]. PPy itself is brown in the oxidized state, appearing darker with increasing thick- ness. Fig. 9.2 shows the cyclic voltammogram (CV, a plot of current vs. voltage) obtained. The CV shows current peaks at ?0:6 V and ?0:4 V (vs. Ag/AgCl), which are typically observed during the reduction and oxidation of PPy(DBS). To validate the operation of the potentiostat chip, the cycling experiment was repeated using an external potentiostat (EcoChemie pgstat30) [Validation experiment was performed along with M. Urdaneta]. The CV obtained using the external potentio- stat has been superimposed upon the CV obtained using the on-chip potentiostat in Fig. 9.2. There is good agreement between the CVs obtained from the external and on-chip potentiostats. The reason for the 2 plots to be not exactly identical to each other could be the disturbance in the electrode positions when the connections were changed from the on-chip potentiostat to the external potentiostat instrument. 145 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0?1 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 Control Voltage (V vs. Ag/AgCl) Measured Current (mA) on?chip potentiostatEcoChemie pgstat30 reduction peak oxidation peak Figure 9.2: Cyclic voltammograms obtained during electrochemical cycling at 100 mV/sec of a PPy(DBS) fllm using the on-chip potentiostat and an external po- tentiostat (EcoChemie pgstat30) [Cyclic voltammograms were recorded along with M. Urdaneta]. 9.2 Potentiostattestingforcontrolofanofi-chiparrayofPPy(DBS)/Au lidded microactuators in a standard electrochemical cell The on-chip potentiostat was further tested for the actuation of PPy/Au bi- layer microactuators with lids comprising a top SU8 layer and a bottom gold layer [Microactuators were fabricated by Dr. M. Christophersen]. The fabrication and characterization of these microactuators is described in [5,94,97]. The actuation test was performed on an array of 416 microactuators with varying hinge lengths ranging from 20 ?m to 800 ?m. All microactuators had a PPy thickness of 3000 ?A and a gold thickness of 1000 ?A. The array samples were placed face-up and at in a custom-fabricated electrochemical cell. A graphite plate was used as the counter 146 inner SU8 layer of the lid outer gold layer of the lid PPy/Au hinge actuator Figure 9.3: Photomicrographs of a portion of the actuated array of actuators [Pho- tomicrographs and videos were captured by Dr. M. Christophersen]. Top, lids open (at ?1 V vs. Ag/AgCl) and bottom, lids closed (at 0 V vs. Ag/AgCl). electrode along with an external Ag/AgCl reference electrode [Electrochemical cell was set up by Dr. M. Christophersen]. Actuators were viewed from directly overhead using a Leica Z16 APO stereomicroscope. Actuation of the microactuator samples was performed using the on-chip po- tentiostat by applying a cyclic control potential between 0 and ?1 V (vs. Ag/AgCl) at 0.25 Hz (500 mV/sec) in 0.1 M NaDBS [Chip testing was performed along with Dr. M. Christophersen]. The actuators rotated the lids from 90? (open position) to 180? (closed position) during the cycling. Fig. 9.3 shows a photomicrograph of part of the array of actuators with a bilayer hinge length of 600 ?m. When the cycling was performed at a lower frequency of 0.01 Hz (20 mV/sec), the actuators rotated the lids from 0? (open position) to 180? (closed position). 147 9.3 Demonstrating in situ control of on-chip PPy(DBS)/Au lidless microactuators 9.3.1 Chip postprocessing To enable deposition of PPy(DBS) and to avoid corrosion, all the aluminum electrodes on the potentiostat chip (described in the previous chapter) were electro- lessly plated with gold [Electroless gold-plating of on-chip electrodes was performed by M. Urdaneta]. Another purpose for the gold-plating is to make the on-chip elec- trodes biocompatible for the cell clinics application. The chip was immersed in a series of solutions for surface treatment (TAS 3Z, Technic Inc., Cranston, RI, USA), nickel deposition (EN 2600 A and B, Technic Inc., Cranston, RI, USA), and gold deposition (Oromerse SO, Technic Inc., Cranston, RI, USA). Approximately 1.5 ?m of nickel was deposited to prepare the surface for the subsequent 1 ?m of gold. All solutions were prepared and used according to the manufacturer?s instructions. Since the electrochemical reaction occurs in an aqueous ionic environment, the chip bond wires needed to be insulated from each other and the conducting electrolyte. The wirebonds were encapsulated using a photopatternable polymer (Loctite 3340, Henkel, Rocky Hill, CT, USA) such that the active chip surface was exposed, as described by Delille et al. [70] [Chip encapsulation was performed by M. Urdaneta]. Using epoxy, a well was placed over the encapsulation for containing ? 500 ?L of electrolyte. Fig. 8.3(b) in the previous chapter shows a photograph of a fully packaged potentiostat chip. 148 PPy(DBS) fllms were deposited using an external potentiostat instrument (EcoChemie pgstat30, Autolab, Westbury, NY, USA). PPy(DBS) was electrode- posited in an aqueous 0.1 M NaDBS, 0.1 M pyrrole solution as described in [93,94] [PPy(DBS) fllms were deposited by M. Urdaneta]. When using the external po- tentiostat, deposition was performed at a voltage of 0.48 V (vs. Ag/AgCl), and PPy(DBS) was deposited on both the WEs and the CE. The WEs here mimic the actuator array that will be employed in cell clinics. They comprise the same mate- rials and have the same areas as the cell clinic actuators, the only difierence being that they are lidless. Indicators of actuation in this experiment were instead color change and out-of-plane thickness change in the polymer fllms. The purpose of de- positing PPy(DBS) on the CE was to provide a known electrochemical reaction with su?cient charge-delivery capability, rather than requiring pH-changing hydrolysis to supply the necessary current. PPy(DBS) on CE provides better charge transfer and also better control over the electrochemical reaction. Furthermore, PPy(DBS) has a large internal surface area due to its lamella structure [94,114]. This helps to prevent the electrochemical reaction to be limited by the size ratio of WE and CE. Thechipemployedagold quasi-reference electrode(Au quasi-RE) because thin fllm Ag/AgCl REs have been found to be unstable for long-term applications [105]. It is well known that using a quasi-RE in an electrochemical cell can result in shifting of the oxidation and reduction peaks, and scaling of the cyclic voltammogram (CV), when compared to CVs obtained employing an Ag/AgCl RE [98]. So the control potential range for the actuation of PPy(DBS) had to be determined experimentally. 149 9.3.2 Test setup The potentiostat chip was mounted on a test-board interfaced to a data acqui- sition system (National Instruments DAQCard-6036E interfaced to a laptop running Labview 7.1). An Agilent 33220A arbitrary waveform generator was used to gener- ate control potential signals. An ofi-chip resistance of 21.58 k? was used for current measurement. The chip was viewed from above using a Leica Z16 APO stereomicro- scope. The electrolyte well was fllled with 500 ?L of 0.1 M NaDBS solution. Images were recorded with a digital camera (Nikon Coolpix 995). 9.3.3 In situ PPy(DBS) actuation The CMOS potentiostat was tested for actuating PPy(DBS) fllms on the 6 WEs that had been deposited using the external potentiostat instrument [Testing was performed along with M. Urdaneta and Dr. M. Christophersen]. Chip operation was demonstrated by performing cyclic voltammetry at a scan rate of 40 mV/sec while monitoring the color of the fllms on the WEs and recording CVs. The applied voltage range was successively incremented until distinct electrochromic changes, as showninFig. 9.4, wereobserved[Instructionsforapplicationofcontrolvoltageswere provided by Dr. M. Christophersen, Color changes observed along with M. Urdaneta and Dr. M. Christophersen]. The flnal voltage range for complete electrochemical cycling was between +200 mV (oxidized, dark brown color) and ?200 mV (reduced, light orange color). Thus, the chip was able to actuate the polymer fllms in situ. Fig. 9.5 shows the CVs, which were recorded over 135 cycles at a sampling rate 150 oxidized state reduced state 200 ?m PPy(DBS)on gold-plated working electrodes gold plated reference electrode PPy(DBS)on gold-plated counterelectrode Figure 9.4: In situ cycling of PPy(DBS) fllms on gold-plated WEs using the on-chip potentiostat connected to an external waveform generator [Photomicrographs were captured along with M. Urdaneta and Dr. M. Christophersen]. Left, PPy(DBS) in the oxidized state. Right, PPy(DBS) in the reduced state. of 50 Hz. The data were time-averaged over every 5 points, and across every 3 cycles, to produce the 45 traces in the flgure. There are distinct oxidation and reduction current peaks at +40 mV and ?85 mV (vs. Au) respectively. However, as expected, due to the quasi-RE, the oxidation/reduction peaks were shifted; vs. Ag/AgCl they typically appear at ?0:4 V (oxidation) and ?0:6 V (reduction). Mean oxidation and reduction peak currents of 1.0 ?A and 2.5 ?A were recorded during the cycling. These currents correspond to current densities of 16.7 pA/?m2 and 41.7 pA/?m2, which are comparable to those observed in standard macroscale setups. Peak cur- rents on the order of 1 mA were recorded in the previous experiment when the potentiostat was used to drive an array of PPy(DBS)/Au microactuators fabricated on an ofi-chip substrate [29]. The shape of the CVs also resemble those obtained from measurements of PPy samples using external potentiostat instruments. 151 ?0.2 ?0.1 0 0.1 0.2 ?3 ?2 ?1 0 1 2 Control Voltage (V) Measured Current (?A) oxidation peak reduction peak 45 traces averaged over 135 cycles Figure 9.5: Cyclic voltammograms recorded during in situ oxidation and reduction of PPy(DBS) fllms [Cyclic voltammograms were recorded along with M. Urdaneta and Dr. M. Christophersen]. 9.3.4 In situ PPy(DBS) deposition Cycling was also performed on PPy(DBS) fllms deposited in situ using the potentiostat chip [Experiment was performed along with M. Urdaneta]. In this experiment, the CE was not covered with PPy(DBS) since it is unfeasible to do that using the on-chip circuitry. Electrodeposition was performed potentiostatically at +250 mV (vs. Au) for 20 minutes. Polymer deposition on the WEs was observed visually. The polymer fllms were then cycled, and the typical current peaks and electrochromic changes were observed. 152 9.4 Summary A CMOS potentiostat chip was designed for driving in situ electrochemistry, for applications such as the deposition and control of electroactive polymer fllms. This was the flrst demonstration of such an integrated system. The potentiostat module was tested and validated for ofi-chip actuation of PPy(DBS) fllms and PPy/Au bilayer microactuators. The control circuit was then tested for both the deposition and actuation of PPy(DBS) fllms in situ on the CMOS chip, as conflrmed by the distinct electrochromic changes observed during electrochemical cycling and the recorded CVs. The data conflrmed that the chip met its design goals for the required current drive together with accurate voltage control. 153 Chapter 10 Conclusions: Part II A CMOS potentiostat chip was designed for in situ driving of electrochemical actuation reactions. The operational amplifler constituting the potentiostat was custom-designed according to the speciflcations for the electrochemical control of PPy(DBS), an electroactive polymer. The employed circuit architecture enables rail-to-rail operation and robust current driving in addition to providing a good compromise between power e?ciency and output signal cross-over distortion. The potentiostat module was tested for control of both ofi-chip lidded and on-chip lidless PPy/Au bilayer microactuators. An estimate for the maximum microactuator array size that the potentiostat will be able to drive in parallel is approximately 1000. The operational amplifler currently consumes 660 ?W of power, with the output driving stage consuming 72% of the total power. The power consumption the operational amplifler output stage can be scaled according to the microactuator array size in future designs. Control of on-chip actuators was demonstrated by employing a Au-plated quasi-reference electrode. This simplifled post-processing, but required experimen- tal determination of the control voltage range for achieving optimal actuation. Since the control voltage range is expected to change over time in the presence of a quasi- reference electrode, this step needs to be automated. This can be accomplished 154 by incorporating peak detection circuitry [115] along with the potentiostat module. This way, the current peaks in the cyclic voltammograms can be detected and com- pared on-chip, and the appropriate control voltage range can be set automatically. The current target application for the integrated potentiostat demonstrated here is to drive and control PPy(DBS)/Au-based lidded actuators in the cell clinics microsystem. Another potential application of the integrated electrochemical reac- tor is drug delivery, wherein drug dosage can be regulated by electrochemical control of electroactive polymers within which the drug molecules are stored [111]. Because of their electrochromic behavior, conjugated polymers are used in display applica- tions [116,117]; therefore the potentiostat and electroactive polymer fllm system presented here can also be considered as a fully integrated demonstration of elec- troactive polymer display technology. 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