ABSTRACT Title of dissertation: CORRELATION OF SIGNALS, NOISE, AND HARMONICS IN PARALLEL ANALOG-TO- DIGITAL CONVERTER ARRAYS Keir Lauritzen, Doctor of Philosophy, 2009 Dissertation directed by: Professor Martin Peckerar Department of Electrical and Computer Engineering Combining M analog-to-digital converters (ADC) in parallel increases the maximum signal-to-noise ratio (SNR) by a factor of M, assuming the noise is un- correlated from one channel to the next. This allows for a significant increase in SNR over a single ADC; however, noise and harmonic correlation degrade this improvement. ADCs have three sources of noise: thermal (and other ran- dom physical processes), sampling, and quantization noise. There are two system components creating harmonics: the sampler and the quantizer. In this thesis, I determine, analytically and experimentally, the degree of correlation between signals, noise, and harmonics in a parallel ADC array. To test the analysis experimentally, I developed a 16-channel test-bed using 16-bit, state-of-the-art ADCs and 16 direct-digital synthesizers as low-noise sig- nal sources. The test bed provides excellent signal isolation between channels and minimal digital noise to enable the measurement of very low levels of correlation. I investigated the feasibility of measuring the very high levels of signal correla- tion in the presence of channel nonlinearities with different measurement signals. For a completely linear channel, the channel matching is limited by noise. With nonlinearities, the ability to measure the signal correlation depends on the mea- surement signal. I verified that the thermal noise is uncorrelated across 16 chan- nels as expected. I also demonstrated that sampling noise is fully correlated from channel-to-channel when a common clock drives the ADCs. Efforts to reduce the correlation using two previously developed de-correlation techniques-phase ran- domization and frequency offsets-successfully reduced the correlated noise by a factor of two. I then demonstrated analytically and experimentally that harmonics from quantizers are largely uncorrelated; however, harmonics from the sampler are largely correlated confirming the need for decorrelation techniques. I demon- strated the impact of the previously developed decorrelation techniques to reduce harmonic correlation and developed two new decorrelation techniques: phase can- cellation and clock offsets, which offer significant advantages over phase random- ization and frequency offsets. Each technique offers different levels of dynamic range improvement and complexity, allowing for a range of techniques to target the optimal level of decorrelation. Correlation of Signals, Noise, and Harmonics in Parallel Analog-to-Digital Converter Arrays by Keir Christian Lauritzen Dissertation submitted to the Faculty of the Graduate School of the University of Maryland, College Park in partial fulfillment of the requirements for the degree of Doctor of Philosophy 2009 Advisory Committee: Professor Martin Peckerar, Chair/Advisor Professor Pamela Abshire Professor P.S. Krishnaprasad Dr. Salvador Talisa Professor Aris Christou c Copyright by Keir Christian Lauritzen 2009 Unless previously transferred to IEEE. Portions of work submitted to IEEE but not accepted for publication at the time of the publication of this dissertation. Dedication I dedicate this dissertation to all my C(K)atherine?s for all their support. ii Foreword The student made substantial contributions to the relevant aspects of the jointly authored work included in the dissertation. iii Acknowledgments I want to acknowledge the following efforts: George Vetticad, Al Wu, and Joe Sluz for helping design, assemble, and troubleshoot the various test beds; Cesar Lugo and Laura Ruppalt for helping me with my writing; Salvador Talisa for reviewing all of my writing; Ken O?Haver, my business area, and JHU Applied Physics Laboratory for support; and my advisor Martin Peckerar for supporting this collaboration. iv Table of Contents List of Tables viii List of Figures ix List of Abbreviations xviii 1 Introduction 1 2 Background 10 2.1 Combining Multiple Channels . . . . . . . . . . . . . . . . . . . 10 2.1.1 Signal Correlation . . . . . . . . . . . . . . . . . . . . . 13 2.1.2 Signal-to-Noise Ratio . . . . . . . . . . . . . . . . . . . 16 2.1.3 Spur-Free Dynamic Range . . . . . . . . . . . . . . . . . 19 2.2 Prewhitening and Decorrelation Techniques . . . . . . . . . . . . 22 2.2.1 Phase Randomization . . . . . . . . . . . . . . . . . . . . 23 2.2.2 Frequency Offsets . . . . . . . . . . . . . . . . . . . . . 27 2.2.2.1 Frequency Offsets on ADC Harmonics . . . . . 28 2.2.3 Dithering on Quantization Noise . . . . . . . . . . . . . . 28 2.3 Summary of Chapter . . . . . . . . . . . . . . . . . . . . . . . . 35 3 Development of Experimental Test Bed 36 3.1 Test Bed Description . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2 Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.1 Large Number of Channels . . . . . . . . . . . . . . . . . 45 3.2.2 Low Noise and Spur Measurement System . . . . . . . . 48 3.2.3 Excellent Signal Correlation Between Channels . . . . . . 52 3.2.4 Excellent Isolation Between Channels . . . . . . . . . . . 53 3.3 Test Bed Characterization . . . . . . . . . . . . . . . . . . . . . . 57 3.3.1 Equivalent Input Referred Noise and DC Offset . . . . . . 57 3.3.2 Full-Scale Power and Frequency Response . . . . . . . . 58 3.3.3 Frequency Response . . . . . . . . . . . . . . . . . . . . 59 3.3.4 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.3.5 Spur-Free Dynamic Range . . . . . . . . . . . . . . . . . 62 3.3.6 Integral and Differential Nonlinearities . . . . . . . . . . 62 3.3.7 Characterization of DDSs . . . . . . . . . . . . . . . . . 66 3.3.8 Characterization of 120 MHz Clocks . . . . . . . . . . . 67 3.3.9 Characterization of 800 MHz Clock . . . . . . . . . . . . 68 3.4 Design and Characterization of S-Band Receiver for CPCR Mea- surements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.5 Summary of Chapter . . . . . . . . . . . . . . . . . . . . . . . . 73 v 4 Correlation of Signals 74 4.1 CPCR Measurement Technique and Receiver Model . . . . . . . 76 4.1.1 CPCR of Linear Channels . . . . . . . . . . . . . . . . . 79 4.2 CPCR Limitations Due to ADC Saturation . . . . . . . . . . . . . 80 4.2.1 Effect of ADC Saturation on CPCR with LFM Measure- ment Signal . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.2.2 Effect of ADC Saturation on CPCR with BLGN Measure- ment Signal . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.2.3 Discussion of Maximum Saturation-Limited CPCR . . . . 84 4.3 CPCR Limitations Due to Third-Order Nonlinearities . . . . . . . 89 4.3.1 Effect of Third-Order Nonlinearities on CPCR with LFM Measurement Signal . . . . . . . . . . . . . . . . . . . . 90 4.3.2 Effect of Third-Order Nonlinearities on CPCR with BLGN Measurement Signal . . . . . . . . . . . . . . . . . . . . 91 4.3.3 Discussion of Maximum Third-Order Nonlinearity-Limited CPCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.4 CPCR Limitations Due to Both ADC Saturation and Third-Order Nonlinearities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.4.1 CPCR with LFM measurement signal . . . . . . . . . . . 97 4.4.2 CPCR with BLGN measurement signal . . . . . . . . . . 98 4.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5 Correlation of Noise 104 5.1 Correlation of Thermal Noise . . . . . . . . . . . . . . . . . . . . 104 5.2 Correlation of Sampling Noise . . . . . . . . . . . . . . . . . . . 109 5.3 Sampling Noise Model . . . . . . . . . . . . . . . . . . . . . . . 112 5.4 Impact of Phase and Frequency Shifts on Sampling Noise . . . . . 112 5.4.1 Determining the Correlation Coefficient . . . . . . . . . . 114 5.4.2 Constant Phase Offsets . . . . . . . . . . . . . . . . . . . 115 5.4.3 Frequency Offsets . . . . . . . . . . . . . . . . . . . . . 116 5.5 Measurements of Sampling Noise Correlation . . . . . . . . . . . 116 5.5.1 Measurement Approach . . . . . . . . . . . . . . . . . . 119 5.5.2 Verifying Sampling Noise . . . . . . . . . . . . . . . . . 120 5.5.3 Constant Phase Offsets . . . . . . . . . . . . . . . . . . . 121 5.5.4 Frequency Offsets . . . . . . . . . . . . . . . . . . . . . 126 5.6 Summary and Conclusion of Chapter . . . . . . . . . . . . . . . . 128 6 Correlation of Harmonics 130 6.1 Origin of ADC Harmonics . . . . . . . . . . . . . . . . . . . . . 131 6.1.1 Harmonics from the Sampler . . . . . . . . . . . . . . . . 132 6.1.1.1 Amplitude and Phase of Sampler Harmonics . . 133 6.1.1.2 Measured Sampler Distortion . . . . . . . . . . 135 6.1.1.3 Predicted Sampler Harmonic Correlation . . . . 138 6.1.2 Harmonics from Quantizer . . . . . . . . . . . . . . . . . 138 vi 6.1.2.1 Simulated Amplitude and Phase of Quantiza- tion Harmonics . . . . . . . . . . . . . . . . . 139 6.1.2.2 Measured Amplitude and Phase of Quantizer Harmonics . . . . . . . . . . . . . . . . . . . . 141 6.1.2.3 Predicted Quantizer Harmonic Correlation . . . 143 6.1.2.4 Maximum Quantizer Harmonic Power . . . . . 143 6.2 Inherent Harmonic Correlation in Parallel ADC Arrays . . . . . . 145 6.2.1 Measured Inherent Harmonic Correlation . . . . . . . . . 145 6.2.2 Inherent Correlation Summary . . . . . . . . . . . . . . . 148 6.3 Phase Decorrelation Techniques . . . . . . . . . . . . . . . . . . 149 6.3.1 Phase Randomization Measurements . . . . . . . . . . . 150 6.3.2 Phase Cancellation . . . . . . . . . . . . . . . . . . . . . 156 6.3.2.1 Theory of Operation . . . . . . . . . . . . . . . 156 6.3.2.2 Phase Cancellation Measurements . . . . . . . 158 6.4 Frequency Decorrelation Techniques . . . . . . . . . . . . . . . . 164 6.4.1 Frequency Offset Measurements . . . . . . . . . . . . . . 164 6.4.2 Clock Offsets . . . . . . . . . . . . . . . . . . . . . . . . 166 6.4.2.1 Theory of Operation . . . . . . . . . . . . . . . 167 6.4.2.2 Clock Offset Measurements . . . . . . . . . . . 169 6.5 Summary and Conclusion . . . . . . . . . . . . . . . . . . . . . . 175 7 Summary and Discussion 179 7.1 Suggestions for Future Work . . . . . . . . . . . . . . . . . . . . 182 A Power of BLGN through Third-Order Nonlinearity 184 B Matlab Code to Determine bopt 185 Bibliography 190 vii List of Tables 2.1 Prior work on decorrelation techniques for different error sources. 23 2.2 PDF of common dither distributions. M is number of digital bits and K = 1;2;:::;M. . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3 Characteristic functions of common dither distributions. Only Uniform and Triangular distributions are the only distributions that can meet the conditions of (2.57). J0 is a Bessel function. M is number of digital bits. K = 1;2;:::;M. . . . . . . . . . . . . 33 3.1 Error power increase due to correlation PR=(MPr) for several val- ues of ?r and M. The larger the number of channels the greater the impact of partial correlation and the greater our ability to measure the partial correlation. Our test bed enables us to observe average correlation coefficients ?r approaching 0.01. . . . . . . . . . . . . 47 4.1 Measured Receiver Characteristics. The large difference in ITOI limits the CPCR for BLGN due to third-order nonlinearities. . . . 86 6.1 Measured SFDR for Each Technique . . . . . . . . . . . . . . . . 178 viii List of Figures 1.1 Combining multiple ADCs in parallel increases the SNR by a fac- tor M, if all noise is uncorrelated across ADC channels. . . . . . . 2 1.2 Measured spectrum of single tone with many harmonic spurs and SFDR of 90 dB. The first nine ADC harmonics are numbered. Many of the non-numbered spurs are generated by the DDS, in- cluding the largest spurs. While these spurious harmonics are larger than the ADC harmonics, they occur at different frequen- cies from the ADC harmonics, so they can be ignored. . . . . . . 5 1.3 For an M channel ADC array, correlated signals and harmonics increase in power by M2, while uncorrelated harmonics and noise increase by M. As a result, for completely correlated harmonics, the total SFDR does not increase, while for uncorrelated harmon- ics an increase in SFDR of M would be achieved. . . . . . . . . . 6 2.1 Simple block diagram of CPCR measurement. . . . . . . . . . . . 15 2.2 The CPCR is the reduction in power between a single channel and the difference between two signals. . . . . . . . . . . . . . . . . . 15 2.3 Schematic diagram of phase randomization and frequency offset decorrelation techniques. . . . . . . . . . . . . . . . . . . . . . . 25 2.4 Subtractive dither in a parallel ADC array. . . . . . . . . . . . . . 29 2.5 Additive dither in a parallel ADC array. . . . . . . . . . . . . . . 29 3.1 Block diagram of experimental test bed consisting of 16 ADCs, 16 DDS, eight 120 MHz oscillators, an 800 MHz oscillator, am- plifiers, and assorted buffers and distribution networks. . . . . . . 37 3.2 Photograph of the test bed composed of 16 ADCs, 16 DDSs, and supporting hardware. Test bed designed and assembled by myself. 38 3.3 Photograph of the ADC board. ADC board designed by Prologic Designs with guidance and troubleshoot by myself. . . . . . . . . 39 3.4 Photograph of the front and back of the ADC board. . . . . . . . . 39 ix 3.5 Simplified block diagram of custom DDS highlighting key en- hancements for this work: phase ?incrementor? and additive white Gaussian noise generator. . . . . . . . . . . . . . . . . . . . . . 40 3.6 Dual DDS board using Xilinx Virtex 4 FPGA and Analog Devices AD9736. DDS board designed by Matt Gerwell . . . . . . . . . . 41 3.7 Block diagram of 120 MHz clock array. . . . . . . . . . . . . . . 43 3.8 Front panel of 120 MHz clock array. . . . . . . . . . . . . . . . . 43 3.9 Top down view of 120 MHz clock array. Clock assembly designed by myself and assembled by George Vetticad. . . . . . . . . . . . 43 3.10 Block diagram of the 800 MHz clock. Clock assembly designed by myself and assembled by George Vetticad. . . . . . . . . . . . 44 3.11 Measured phase noise from DDS at 100 MHz output frequency using 800 MHz clock. The DDS phase noise from each channel is comparable to commercial signal generators. . . . . . . . . . . 48 3.12 Plot of first 100 ADC harmonics in the first, second, and third Nyquist zones and the first 100 DDS harmonics for a frequency of 97:59979248 MHz. Only the fiftieth harmonic of both the ADC and DDS occur at the same frequency within the passband of the anti-aliasing filter. The blue lines mark the passband of our band- pass anti-aliasing filter, and the green lines mark the boundaries of the first, second, and third Nyquist zones. . . . . . . . . . . . . 50 3.13 Y-factor noise figure measurement technique uses two calibrated noise sources to measure the noise figure of the ADC. The mea- surement required a preamplifier due to the high noise figure of the ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.14 Measured noise figure matches the specification when RF trans- former loss is included. . . . . . . . . . . . . . . . . . . . . . . . 52 3.15 ADC noise floor. . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.16 Output of 16 ADC channels demonstrating phase incrementation alignment technique. . . . . . . . . . . . . . . . . . . . . . . . . 54 3.17 (a) When the input signal phases were adjusted randomly across channels the power of the second harmonic varied significantly. (b) After hardware modifications to increase isolation, the varia- tion was dramatically reduced. . . . . . . . . . . . . . . . . . . . 55 x 3.18 ADCs meet EIRN specification. . . . . . . . . . . . . . . . . . . 58 3.19 The DC offset of some ADCs are out of specification, but this does not impact correlation measurements. . . . . . . . . . . . . . 58 3.20 Measured full scale power shows good matching between chan- nels and RF transformer loss of about 1 dB. . . . . . . . . . . . . 59 3.21 Measured frequency response shows increasing loss as frequency increases and excellent matching from channel to channel (small gain error). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.22 The 1 dB and 3 dB bandwidths are about 180 MHz and 280 MHz for all ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.23 Measured SNR matches the specification when RF transformer loss is included. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.24 Measured SFDR with gain off. . . . . . . . . . . . . . . . . . . . 62 3.25 Measured SFDR with gain on, which, in general, improves the third order harmonic performance. . . . . . . . . . . . . . . . . . 63 3.26 Block diagram of INL measurement setup. The signal frequency was chosen such that the number of cycles per record 16659 is relatively prime with the record length 65536. The filter improves the purity of the test signal, reduces spurs and noise. . . . . . . . . 64 3.27 Measured INL from all 16 ADCs show complexity of quantizer transfer function errors. The large scale structure exhibits similar- ities from channel to channel, implying some level of correlation. . 65 3.28 Three measurements of INL and DNL from the same ADC prove the excellent reproducibility of the measurements. . . . . . . . . . 66 3.29 DDS phase noise at 100 MHz output frequency with 800 MHz clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.30 Measure phase noise is below white floor specification of -165 dBc/Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.31 The SNR is reduced by 2 dB at the highest frequency of interest. . 69 3.32 The phase noise of the 800 MHz clock is very low. . . . . . . . . 70 3.33 Block diagram of S-band receiver. . . . . . . . . . . . . . . . . . 71 xi 3.34 Photo of S-band receiver. . . . . . . . . . . . . . . . . . . . . . . 72 4.1 Block diagram of the CPCR measurement. Each channel contains a single receiver, and one of the legs possesses a digital equalizer heq and a single-tap equalizer g. Our receiver model includes both third-order nonlinearities and noise contributions, and the ADC model specifies the ADC full-scale voltage, F. . . . . . . . . . . . 76 4.2 Demonstration of clipping on a sinusoidal input. The residue of saturated signals is increased relative to the unsaturated case. . . . 80 4.3 Comparison of LFM and BLGN probability density functions at the same power (LFM amplitude A = 1 and BLGN variance s2 = 12). 82 4.4 Analytical and simulated saturation-limited CPCR versus mea- surement signal power for the receiver parameters shown in Ta- ble 4.1. The maximum CPCR for BLGN measurement signal is 8 to 10 dB below that of the LFM measurement signal. For both measurement signals, the simulations closely match the analytical results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.5 Saturation-limited maximum CPCR versus channel gain differ- ence for both measurement signals. For both measurement sig- nals, the maximum CPCR decreases approximately linearly with increasing gain difference. . . . . . . . . . . . . . . . . . . . . . 88 4.6 Maximum CPCR versus channel ITOI difference. Maximum CPCR increases above the worst-case maximum CPCR as the difference between ITOI decreases (in other words, as ITOImax=ITOImin ap- proaches 0 dB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.7 Maximum CPCR in the presence of third-order nonlinearities ver- sus measurement signal power using the parameters in Table 4.1. With g, the maximum CPCR of the LFM measurement signal is not limited. For BLGN, the CPCR remains limited, but the inclu- sion of g increases the maximum CPCR by a few dB as predicted. 95 4.8 Experimentally measured CPCR versus measurement signal power for both LFM and BLGN measurement signals. The right hand plot is a close-up corresponding to the dotted region indicated on the left hand plot. For the BLGN case, the experimentally ob- tained data closely matches the expected CPCR; however, elec- tromagnetic interference limited the CPCR measurement for the LFM case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 xii 4.9 Output signal power of the equalized channel gz1, reference chan- nel z2, and residue r versus frequency. The left hand figure shows the total 15 MHz LFM waveform and the right hand figure shows a narrow region of 400 kHz. Uncorrelated spurs in the equalized and reference channels limit channel matching and CPCR. Signals are canceled by over 65 dB, but sideband spurs limit total CPCR compared to ideal CPCR of about 70 dB. . . . . . . . . . . . . . . 100 5.1 (a) Overlay of the spectrum of 16 channels with input signal of -60 dBFS. (b) Spectrum of 16 channels added in the voltage domain. The axis of (b) is offset by 10log10 16 = 12 dB, so that noise may be directly compared. At this input power, noise is uncorrelated and SNR is increased by 12 dB. . . . . . . . . . . . . . . . . . . 105 5.2 Plots of the noise and distortion power from the 16 channels as well as the combined channel. The noise and distortion power in- creases significantly near the full scale of the ADC. This is likely the result of increases in both distortion and sampling noise. The DDS signal source noise is < 75 dBc within the filter bandwidth. 107 5.3 Plot of D for many different input powers. Below -10 dBFS, the noise and distortion is uncorrelated and I 0 dB. Above - 10 dBFS, the noise and distortion is partially correlated with D decreasing to a minimum values of about -2.7 dBFS. . . . . . . . 108 5.4 Maximum SNR of parallel ADC arrays as a function of IF fre- quency. The SNR (excluding sampling noise) of a single ADC is 78 dB and the RMS clock jitter is 60 fs; both values are near the state of the art. The impact of sampling noise on a single channel is low for IFs below 100 MHz; however, as the number of chan- nels increases the SNR limitation due to correlated sampling noise becomes very significant. The 700 MHz 3 dB bandwidth of the LTC2208 is also marked. . . . . . . . . . . . . . . . . . . . . . . 110 5.5 Maximum SNR of parallel ADC arrays as a function of IF fre- quency. The SNR (excluding sampling noise) of a single ADC is 78 dB and the RMS clock jitter is 200 fs; the RMS clock jitter is common for PLL clock sources [1]. The impact of sampling noise on a single channel is significant for IFs above 50 MHz. . . . . . . 111 5.6 Downconversion block diagram with phase and frequency decor- relation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 xiii 5.7 Block diagram of sampling noise measurement using 8 ADCs and DDSs. The measured phase noise of the 120 MHz signal genera- tor and noise diode was -123 dBc/Hz at 1 MHz, Ill above the inter- nal noise of the ADC (-157 dBc/Hz) and the DDS (-150 dBc/Hz at 1 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.8 (a) Plot of the generated signal in the frequency domain. The rel- atively high noise floors are due to the imposed sampling noise. (b) Frequency domain plot of the noise of each channel over a 100 kHz bandwidth offset 15 MHz from the signal. There is strong correlation within each set of ADCs 1-4 and 5-8, and no correla- tion between sets with different diodes. DDS and ADC noise was much lower at about -101 dBFS per FFT bin from prior measure- ments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.9 The measured correlation coefficient for phase shifted signals matches the prediction from (5.13). . . . . . . . . . . . . . . . . . . . . . 123 5.10 Color map of the measured correlation coefficient matrix between channels with phase uniformly distributed among all 8 channels between 0 and 2p. . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.11 (a) The fully correlated and phase-decorrelated measured spec- tra for a uniform phase distribution from 0 to 2p over a 24 MHz bandwidth. Scale relative to the full scale of a single channel. (b) Close up of noise in 100 kHz bandwidth offset from the signal by 13 MHz. I calculated the correlated spectrum by summing the magnitude of each channel?s spectrum. The phase-decorrelated noise is 3 dB below the correlated output due to the phase shifts; the actual spectrum is always less than or equal to the correlated spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.12 Color map of the measured correlation coefficient matrix when channels 1-4 are set in phase with each other but in quadrature with channels 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.13 Input signals of 8 ADCs shifted 1.8 kHz before downconversion and recorrelation. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.14 Measured correlation coefficient matrix is about 0.5 for all chan- nels when input frequencies are offset by 1.8 kHz. . . . . . . . . . 128 6.1 Simple block diagram of an ADC composed of a sampler and quantizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 xiv 6.2 Measurement setup used to capture Fig. 6.3 composed of an Ag- ilent E8267D signal generator, Mini-Circuits HELA-10B ampli- fier, lowpass filters, and a single ADC. . . . . . . . . . . . . . . . 136 6.3 The second through fifth harmonic?s magnitude and phase mea- sured at different input frequencies near full scale of the ADCs. The second, third, and fourth harmonics all increase in power with frequency, although the second and fourth contain several troughs. The phase of the ADCs are largely consistent from chan- nel to channel, suggesting strong correlation. . . . . . . . . . . . 137 6.4 (a) Simulated jakmj. (b) Simulated fkm. (c) Measured jakmj. (d) Measured fkm. The simulated results used the measured INL with a noise signal as suggested in [2]. The measured results were mea- sured at 38.6 MHz using the experimental test bed. The measured magnitudes show similar trends; the magnitude is nearly constant over most input powers with the second and third harmonics in- creasing near full scale. At lower powers, the simulated is higher than the measured. The simulated and measured phase offsets are vastly different. . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 6.5 Maximum measured harmonics for k = 2;:::;100 for 100 input powers from -60 to -0.2 dBFS at 38.6 MHz. The maximum pow- ers for the tenth and higher ADC harmonics are below -100 dBFS. 144 6.6 Comparison of Pk;max and Pk for k = 2;3;4;5 shows that second and fourth harmonics are more correlated at high powers (above -8 dBFS) and the third and fifth harmonics are more correlated at lower powers. The second harmonic is the largest harmonic. At some input powers, the harmonics destructively interfere and cancel.147 6.7 Ik and Rk at -0.2, -5.2, -20.0, and -40.4 dBFS. Many higher or- der harmonics are well correlated at higher input powers and less correlated at lower input powers. . . . . . . . . . . . . . . . . . . 148 6.8 Distribution of phase randomization Sets 1 and 2 around the unit circle. Sets were generated using uniform pseudorandom number generator from 0 to 2p. Phase randomization used the red ?x? phase offsets and phase cancellation used the adjusted blue circle phase offsets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.9 Phase randomization Set 1 effectively decorrelates the harmonics. The SFDR improves to 101.5 dB from 91.2 dB. . . . . . . . . . . 152 xv 6.10 Phase randomization Set 2 is less effective than Set 1. Both the second and third harmonic are largely correlated at higher powers and the SFDR is only 95.5 dB compared to 101.5 dB for Set 1. . . 153 6.11 Measured Ik for phase randomization Sets 1 and 2 at -0.2, -5.2, -20.0, and -40.4 dBFS. Ik shows significant decorrelation for all harmonics unlike Fig. 6.7. The peak Ik is about -3 dB and the average is approximately M 1. . . . . . . . . . . . . . . . . . . . 154 6.12 12-point histograms of n2 across 120 input powers have a similar shape to the Rayleigh distribution fn(n). . . . . . . . . . . . . . . 155 6.13 The vector formed by the sum of bopt is rotated, so that it is p out of phase with the sum of the channels of ?bopt. . . . . . . . . . . . 157 6.14 Measured Pk and Pk;max for k = 2;3;4;5 using phase cancellation technique for Set 1. The second harmonic is well canceled at full scale and improves the SFDR to 103.9 dB from 101.5 dB. The correlation of the other harmonics does not increase. . . . . . . . 159 6.15 Measured Pk and Pk;max for k = 2;3;4;5 using phase cancellation technique for Set 2. The results are similar to Set 1 and the SFDR increases to 103.4 dB from 95.5 dB. . . . . . . . . . . . . . . . . 160 6.16 Measured Pk and Pk;max for k = 2;3 using phase cancellation Set 1 phases. At 86.64 MHz, the second harmonic is not canceled due to the Nyquist zone difference with the training data. At 91.64 MHz, the second harmonic is well canceled. . . . . . . . . . . . . 162 6.17 Measured Pk and Pk;max for k = 2;3 using phase cancellation Set 1 phases. At 86.64 MHz, the second harmonic is largely correlated and the SFDR is reduced. At 91.64 MHz, the second harmonic cancels as expected. . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.18 Before realignment, each channel is offset by 10 kHz from the previous channel. After downconversion and realignment, the sig- nals coincide in frequency and are correlated. . . . . . . . . . . . 165 6.19 Prior to realignment, the second harmonics are spaced by 20 kHz. After realignment, though the fundamental signals coincide, the second harmonics remain offset by 10 kHz, and as a result do not sum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.20 Before realignment, the third harmonics are spaced by 30 kHz. After realignment, they are spaced by 40 kHz (k+1). . . . . . . . 167 xvi 6.21 Schematic of the clock offset technique. Each channel is sampled by a different frequency and then digitally resampled to realign the signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.22 The sampled signal appears very similar when plotted in the sec- ond Nyquist zone as expected. Each clock is offset from the pre- vious channel by 200 kHz. There is insufficient isolation between clocks, so large spurs occur on the right hand side of the spectrum. 170 6.23 Captured signals after downconversion and resampling. The AWGN signals are well correlated in the frequency domain. . . . . . . . . 171 6.24 Real part of the eight captured signals after downconversion and resampling. The excellent overlap indicates that the signals are well correlated in the time domain. . . . . . . . . . . . . . . . . . 172 6.25 The captured sinusoidal input is correlated when plotted in the second Nyquist zone. Insufficient clock isolation cause the series of spurs around the signal. . . . . . . . . . . . . . . . . . . . . . 173 6.26 Plot of the second harmonics from each of the four channels fol- lowing downconversion and resampling. For the sampling fre- quencies chosen, the resulting second harmonics are offset by 100 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 A.1 ?Lowpass? and ?bandpass? Gaussian noise through a third-order nonlinearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 xvii List of Abbreviations ADC Analog-to-digital converter SNR Signal-to-noise ratio RSS Root-sum-square DDS Direct-digital synthesizer CPCR Channel-pair cancellation ratio IF Intermediate frequency RMS Root-mean-square SFDR Spur-free dynamic range PSD Power Spectral Density DFT Discrete Fourier transform IDFT Inverse discrete Fourier transform LO Local oscillator PDF Probability density function LSB Least significant bit AAF Anti-aliasing filters MSPS Millions of samples per second FPGA Field-programmable gate array DAC Digital-to-analog converter NF Noise figure EMI Electromagnetic interference EIRN Equivalent input referred noise INL Integral Nonlinearity DNL Differential Nonlinearity LFM Linear frequency modulation BLGN Band-limited Gaussian Noise ITOI Input third order intercept RF Radio frequency MOSFET Metal-oxide semiconductor field effect transistor AWGN Additive white Gaussian noise xviii Chapter 1 Introduction Analog-to-digital converters (ADC) limit the dynamic range of many sen- sor, test and measurement, and communication systems [3, 4, 5, 6, 7]. Despite increases in ADC dynamic range over time [8], many of these systems would benefit from greater dynamic range capabilities. Since ADC performance gains arise from advances in underlying circuit techniques and semiconductor process advances, improvements in ADC performance are likely to plateau as silicon?s limits are reached, much as microprocessor clock speed has stagnated [9]. Both of these concerns necessitate moving toward parallel ADC array architectures for performance gains, as microprocessors have. Parallel ADC arrays allow a substan- tial increase in the dynamic range relative to a single ADC; however, the impact of signal, harmonic, and noise correlation on a parallel systems has been little studied and may potentially limit the system dynamic range with many channels. It is an interesting and surprising result emerging from this study that the impact of noise and distortion correlation on multi-channel dynamic range is only fully manifest when the channel count is large (> 4). In this work, I determined analytically and experimentally the degree of correlation between signals, noise, and harmonics in a parallel ADC array. Fig. 1.1 shows a parallel ADC system composed of M ADCs (not to be confused with 1 Figure 1.1: Combining multiple ADCs in parallel increases the SNR by a factor M, if all noise is uncorrelated across ADC channels. a time-interleaved ADC array [10]). In this system, the same analog signal is applied to all M ADCs and the output is digitally summed. The dynamic range, as measured by the maximum signal-to-noise ratio (SNR), increases because the signal is correlated from channel to channel while the noise is not. When summed, the voltage of the M correlated (or coherent) signals increase over a single channel by a factor M (power increases by M2), while the uncorrelated (or independent) noise from each channel combines as root-sum-square (RSS), which increases the voltage by pM (power increases by M). The maximum power into the ADC array increases by M while the noise averages lower. In a parallel array, the SNR, therefore, increases by a factor of M assuming the noise is uncorrelated from channel-to-channel [11, 12, 13, 14]. In Chapter 2, I will develop a mathematical framework to discuss the cor- relation between channels. Additionally, I will discuss the limited literature in this area of multi-channel ADC arrays. I will discuss the decorrelation techniques previously discussed in the literature. To investigate the correlation of noise and distortion experimentally, I devel- 2 oped a 16-channel testbed using 16-bit state-of-the-art ADCs and 16 direct-digital synthesizers (DDS) as low-noise signal sources. I will describe the test bed and its characterization in Chapter 3. The goal of the test bed is the capability to measure low levels of correlation. To achieve this, the test bed is composed of a large num- ber of channels, provides excellent isolation from channel to channel, excellent source correlation, and has minimal source and digital noise. While the signal power increases by M2 when the channels are reasonably well matched, many communication and sensor applications of parallel ADC ar- rays, such as interference mitigation, require the extremely high matching be- tween channels [15, 16]. Though hardware variations between channels limit the intrinsic channel response match, digital equalization techniques improve channel- to-channel matching. Channel nonlinearities, however, limit the level of matching achievable, as measured by the channel-pair cancellation ratio (CPCR). I inves- tigated the challenge of measuring the very high levels of signal correlation in the presence of channel non-linearities with different measurement signals. For a completely linear channel, the channel matching is limited by noise. With non- linearities, the ability to measure the signal correlation depends on the measure- ment signal, with linear frequency modulated signals performing better than band- limited Gaussian noise on an experimental receiver. I will discuss this further in Chapter 4. In Chapters 5 and 6, I will address five sources of noise and distortion within ADCs? thermal noise (and other random physical processes), sampling noise, quantization noise, sampler distortion, and quantizer distortion. Thermal noise 3 is assumed to be always independent between ADCs and is the largest source of noise in modern ADCs. In Chapter 5, I will verify this experimentally. Ideally, quantization noise is correlated between channels, but previous investigations in the literature determined that it may be decorrelated using dithering [17]. Continuing in Chapter 5, I will demonstrate the sampling noise due to a common clock is fully correlated from channel-to-channel. Efforts to reduce the correlation using two previously developed decorrelation techniques?phase ran- domization [18, 19] and frequency offsets [20, 21]?successfully reduced the cor- related noise in half. In addition to noise, real ADCs generate spurious harmonics that may limit the dynamic range and degrade system performance. The undesired harmonics may alias into the passband of the signal. The extent of spurious harmonic gener- ation by an ADC is characterized by the spur-free dynamic range (SFDR), which is the ratio of the signal to the largest harmonic, while the SNR is the ratio of the signal to the integrated noise power. Generally, you would like a SFDR greater than your SNR within a given bandwidth. Fig. 1.2 shows the spectrum from of a single DDS input to single ADC. The largest ADC harmonic is about -90 dBFS, so by our definition the SFDR is 90 dB (the higher spurious tones are not ADC harmonics, and I assume they are generated by the DDS). These harmonics may be correlated across ADCs (I show later that they largely are), in which case their power increases by M2 like the signal, resulting in no net increase in SFDR from parallelization, as illustrated in Fig. 1.3. Various methods have been proposed to improve the SFDR of a single channel ADC [22, 23, 24]. 4 Figure 1.2: Measured spectrum of single tone with many harmonic spurs and SFDR of 90 dB. The first nine ADC harmonics are numbered. Many of the non-numbered spurs are generated by the DDS, including the largest spurs. While these spurious harmonics are larger than the ADC harmonics, they occur at different frequencies from the ADC harmonics, so they can be ignored. 5 Figure 1.3: For an M channel ADC array, correlated signals and harmonics increase in power by M2, while uncorrelated harmonics and noise increase by M. As a result, for completely correlated harmonics, the total SFDR does not in- crease, while for uncorrelated harmonics an increase in SFDR of M would be achieved. 6 In Chapter 6, I will demonstrate analytically and experimentally that har- monics from quantizers are largely uncorrelated (with some partial correlation); however, harmonics from the sampler are largely correlated. This large corre- lation necessitates the need for decorrelation techniques. I will demonstrate the impact of the previously developed decorrelation techniques to reduce harmonic correlation and discuss two new decorrelation techniques?phase cancellation and clock offsets?that offer significant advantages over the other two. Phase cancel- lation increases the system SFDR by adjusting the input phase in such a way as to cancel the largest harmonics. Clock offset decorrelation applies unique sampling frequencies to each channel causing aliased harmonics to alias to different fre- quencies, which increases the SFDR by about M2. Together the four techniques provide a complete ?toolbox? to improve the SFDR by up to M2. Each tech- nique offers different levels of dynamic range and complexity increases, allowing a system design a range of techniques to target the optimal level of decorrelation. Finally in Chapter 7, I summarize the results and make suggestions for future work. To conclude, a succinct statement of the problems addressed in this thesis is: 1. What are the major noise and distortion sources in large (> 4 channel) parallel ADC arrays? 2. To what extent are these noise and distortion sources correlated from chan- nel to channel? 7 3. To what extend can existing (and proposed) decorrelation techniques min- imize output noise and distortion? The unique contributions of this thesis to the field of multi-channel ADC array technology are: 1. I have built the largest channel-count multi-channel ADC array useful for studying noise averaging effects in such systems. 2. I have found that sampling noise and sampler distortion are the major cor- related noise and distortion sources. 3. I have found that thermal noise and quantization noise (with dithering) are the major uncorrelated noise sources. 4. I have found that distortion from quantizer nonlinearities are partially cor- related. 5. I have investigated the following techniques for decorrelation: a Phase randomization b Frequency offsets 6. Of these techniques, I have found frequency offsets to be most effective (as discussed in the body of this thesis). 7. I have developed the following two decorrelation techniques: a Phase cancellation b Clock offsets 8. I have shown that the advantages of phase cancellation relative to phase randomization are: 8 a Reduced peak harmonics levels, increasing SFDR by up to 8 dB b Reduced impact of a ?bad draw? in phase randomization 9. I have shown the advantages of clock offsets relative to frequency offsets are that clock offsets do not require mixers and are therefore appropriate in direct-sampling systems. 10. Of all the techniques, frequency offsets and clock offsets are most effec- tive, improving the SFDR by M2 11. Phase randomization, phase cancellation, and frequency offsets reduced the sampling noise by 50% - the maximum theoretical limit, while clock offsets use independent clocks and produce independent sampling noise. These findings are substantiated in theory and in experiment as described below. 9 Chapter 2 Background In this chapter, I will discuss the relevant background research from the literature. In the first section, I mathematically describe the correlation between channels and associated correlation metrics. Next, I will describe the analytical models for sampling noise, sampler distortion, and quantizer nonlinearities from the literature. I will then discuss prewhitening, which is the intellectual foundation of the decorrelation techniques used in this dissertation. Finally, I discuss the previous literature on harmonic correlation and decorrelation techniques. 2.1 Combining Multiple Channels In this section, I outline the mathematical foundation of correlation, de- scribe correlation across many channels, and discuss various metrics to charac- terize correlation across many channels. It is important to note that, while the mathematics are the same, the discussion here focuses on the correlation between two sequences or signals, not between random variables. Fig. 1.1 showed a parallel ADC array, where the output sequences xm of M channels are digitally summed, M m=1 xm: The power of the combined signal Px is the expectation of the magnitude squared 10 of sum of the sequences xm, Px = E 2 4 M m=1 xm 23 5; (2.1) where E[x] denotes the expectation of x. The expectation is defined as E[x], 1t 1 t0 t1Z t0 x(t)dx for continuous signals and E[x], 1N N n=1 x[n] for discrete signals, if the signals are wide-sense stationary. Expanding the mag- nitude squared operation of (2.1), Px becomes Px = E " M m=1 xm ! M l=1 xl ! # (2.2) where denotes complex conjugation. Summation and expectation are linear op- erations, so (2.2) may be rewritten as Px = M m=1 M l=1 E[xmx l ]: (2.3) E xmx l is the correlation, or first joint moment, between the sequences xm and xl [25]. The elements of (2.3) form the M M correlation matrix Cx, Cx = 2 66 66 66 66 66 4 E[x1x 1] E[x1x 2] E[x1x M] E[x2x 1] E[x2x 2] E[x2x M] E[xMx 1] E[xMx 2] E[xMx M] 3 77 77 77 77 77 5 (2.4) where m is the row number and l is the column number. The mth diagonal entry of the correlation matrix is the power, or second moment, of the mth channel. The 11 correlation matrix is Hermitian because Cx is the conjugate transpose of itself, E[xmx l ]= E[x mxl]. The total power Px of the sum of channels xm is the sum of all the entries of Cx, which in matrix notation is Px =1TCx1; (2.5) where 1 is a M-dimensional vector with a value of 1 for every entry, 1= 2 66 66 66 66 66 4 1 1 ... 1 3 77 77 77 77 77 5 M : (2.6) Px is always real (as it should be, since you can?t have imaginary power!) because Cx is Hermitian, therefore, Px =1TCx1=1T R(Cx)1: (2.7) The correlation coefficient, defined as rml , E[xmx l ]p E[jxmj2]E[jxlj2]; (2.8) characterizes the degree of correlation between two channels, irrespective of the sequence power. Correlation has units of power, while the correlation coefficient is unit less. The correlation coefficient may be measured for harmonics, signals, or noise in the frequency domain or the time domain. If rml = 1, then xm is fully correlated 12 with xl. If rml =0, then xm is uncorrelated with xl. If rml = 1, then the sequences are anti-correlated and xm = xl. The correlation coefficient rml varies from -1 to 1. The correlation coefficient matrix Rx is composed of pairwise correlation coefficients, in the same way as the correlation matrix Cx, Rx = 2 66 66 66 66 66 4 1 r1;2 r1;M r2;1 1 r2;M rM;1 rM;2 1 3 77 77 77 77 77 5 : (2.9) The total correlation coefficient Rx is the sum of the entires of the correlation coefficient matrix Rx, Rx =1TRx1: (2.10) The maximum value of Rx is M2 when all channels are correlated (rml = 1). The correlation coefficient matrix, like the correlation matrix, is Hermitian (rml = r lm). Therefore, like the Px, when calculating the total correlation coefficient Rx only the real parts of Rx are required, since the complex parts cancel. 2.1.1 Signal Correlation Throughout this dissertation, the focus is on the correlation difference be- tween the signal s and the error e. The error e may be thermal noise, sampling noise, spurious harmonics, or some other error source. The recorded sequence xm 13 is separated into a signal sm and a signal-dependent additive error em(sm), xm = sm +em(sm): (2.11) (The additive error may also be signal independent, such as thermal noise, but the formulation is the same.) The signals are typically about the same, that is sm sl s0. The correlation matrix Cs is then approximately Cs 2 66 66 66 66 66 4 E[s0s 0] E[s0s 0] E[s0s 0] E[s0s 0] E[s0s 0] E[s0s 0] E[s0s 0] E[s0s 0] E[s0s 0] 3 77 77 77 77 77 5 ; (2.12) and Ps M2 E[js0j2]. The total correlation coefficient Rs is about M2. While the above approximation is generally true, it does not provide suf- ficient information of exactly how well matched two channels are. Very high levels of matching are required for many interference mitigation techniques used in communications [15]. Consider two signals s1 and s2, where s2 the ampli- tude is different by a factor of 1.01 and the phase offset from s1 by 170 ?rad 1, s2 = 1:01s1e j0:00017. The correlation coefficient is, therefore, r1;2 = E[s1s 2] pE[js 1j2]E[js2j2] = 0:99999999 0:00017 j: (2.13) Clearly, the signals are very well correlated, although they are not identical as such a high correlation coefficient would suggest. Retaining eight significant digits is not only unwieldy, but it violates standard scientific notation. 1This is the measured RMS phase error and amplitude error of the IF testbed discussed later. 14 Figure 2.1: Simple block diagram of CPCR measurement. Figure 2.2: The CPCR is the reduction in power between a single channel and the differ- ence between two signals. CPCR provides a much better metric of matching between any two chan- nels. CPCR quantifies the matching of two signals xm and xl by comparing the signal power of one channel to power of the difference between the two signals, CPCR = E[jxmj 2] E[jxm xlj2] = E[jxmj2] E[jxmj2]+E[jxlj2] 2rmlpE[jxmj2]E[jxlj2]; (2.14) as shown in Fig. 2.1. Fig. 2.2 shows a qualitative description of CPCR. The sig- nal xm has a particular power spectral density (PSD) and after cancellation it is reduced by the CPCR. The CPCR from the example (2.13) is CPCR = E[js1j 2] E[js1 s2j2] = E[js1j2] E[js1 1:01s1e j0:00017j2] = 1 1:0 10 4 = 40:0 dB; (2.15) which demonstrates that the CPCR is far more readable than the correlation coef- 15 ficient when the signals are well matched. 2.1.2 Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is defined as SNR , PsP e = M 2 E[js0j2] 1TCe1 (2.16) where e is the noise. If I assume that the noise power is about the same in every channel, E[eme m] E[ele l ] E[je0j2]; then Ce ReE[je0j2]. In that case, (2.16) becomes SNR = M 2 E[js0j2] ReE[je0j2] : (2.17) The SNR improvement relative to a single channel from combining M channels is then SNRimprovement = SNR=E[js0j 2] E[je0j2] = M2 Re : (2.18) Since Re varies from 0 to M2, the SNR improvement varies from a factor ? to 1, although an improvement of ? is unlikely. In addition, I define the average non-diagonal correlation coefficient ?r, ?r, 1M2 M M m=1 M l6=m=1 rml = Re MM2 M: (2.19) It is often possible to calculate ?r between any two pairs of channels, such as sampling noise. In these cases, (2.17) is written as SNR = M 2 (M+(M2 M)?r) E[js0j2] E[je0j2]: (2.20) 16 and the SNR improvement from (2.18) is then SNRimprovement = PsP e =E[js0j 2] E[je0j2] = M2 (M+(M2 M)?r): (2.21) When ?r= 0 (as in the case of thermal noise), then the SNR improvement is M. I will now introduce the ratio of the actual SNDR increase to the ideal SNDR increase I. The actual SNDR increase is SNDRsum SNDRsingle channel = M2S PR = S Pr = M2Pr PR ; (2.22) while the ideal SNDR increase is M. Therefore, I is D = M 2Pr PR =M = MPr PR : (2.23) Some challenges exist in measuring the correlation of the noise. In some instances, it is beneficial to measure the correlation in frequency domain, such as when the input signal is a tone. The signal may be transformed into the frequency domain using the discrete Fourier transform (DFT) [26]. The DFT transforms the sequence xm[n] to the discrete frequency domain X[?n], X[?n], N 1 n=0 x[n]W n ?nN (2.24) where WN = e2pj=N. The inverse DFT (IDFT) is defined as x[n], 1N N 1 ?n=0 X[?n]W n ?nN : (2.25) The correlation between xm and xl in the discrete frequency domain is E[xm[n]x l [n]]= 1N N 1 n=0 1 N N 1 ?nm=0 Xm[?nm]W n ?nmN ! 1 N N 1 ?nl=0 Xl[?nl]W n ?nlN ! ; 17 which may be rewritten as E[xm[n]x l [n]]= 1N2 N 1 ?nm=0 N 1 ?nl=0 Xm[?nm]X l [?nl] 1 N N 1 n=0 W n(?nl ?nm)N ! : (2.26) As discussed earlier, I generally only require the real part of the correlation. Tak- ing the real part of the correlation, (2.26) becomes R(E[xm[n]x l [n]])= 1N2 N 1 ?n1=0 N 1 ?n2=0 R(Xm[?n1]X l [?n2]) 1 N N 1 n=0 cos(2pn(?n2 ?n1)=N) ! : (2.27) The summation of cosines equals 1 N N 1 n=0 cos(2pn(?n2 ?n1)=N)= 8 >>>< >>> : 1 if ?n1 = ?n2 0 if ?n16= ?n2 ; so (2.27) becomes R(E[xm[n]x l [n]])= 1N2 N 1 ?n=0 R(Xm[?n]X l [?n]): (2.28) The real part of the correlation may be found with a single summation. Alternately, the real part of the correlation may be found by adding the two signals and measuring the power. The real part of the correlation is R(E[xmx l ])=(1=2)E[xmx l ]+(1=2)E[xmx l ] : (2.29) Using (2.3) for two channels, E[xm +xl]= E[jxmj2]+E[jxlj2]+E[xmx l ]+E[xmx l ] ; (2.30) the real part of the correlation becomes R(E[xmx l ])= 12 E[xm +xl] E[jxmj2] E[jxlj2] : (2.31) 18 By measuring the power of each channel individually and then the sum, I can measure the correlation. This is especially powerful when the voltage signal is not directly available, such as when using a spectrum analyzer. I implemented this technique when I measured the correlation of the sampling noise. 2.1.3 Spur-Free Dynamic Range Throughout this dissertation, I only consider harmonics of sinusoidal input tones, although harmonics are generated for all input signals. The kth harmonic of an input tone at frequency f is also a tone, which is at frequency k fin. The tone may then be analyzed using the DFT. If I consider only the positive fre- quencies of the Fourier spectrum, since the harmonic is real, then the harmonic is fully described by the Fourier coefficient akm of the bin containing the harmonic frequency k fin, where m is the channel number. In the time domain (again, only considering the positive frequencies), the harmonics ekm(t) are ekm(t)= akme j2pk ft: (2.32) When the signal input frequencies are the same, then the correlation is E[ekme kl]= E h akme j2pk fta kle j2pk ft i = akma kl: (2.33) If the harmonics may be manipulated in such a way, that k f of channel m is different from channel l, then the correlation is zero. Applying (2.33) to (2.8), the correlation coefficient between the kth har- 19 monic of any two channels m and l is rml = akma kl jakmjjaklj= jakmje j\akmjaklje j\akl jakmjjaklj = e j\akm j\akl: (2.34) While the magnitude of rml is always 1, I are only concerned with the real part of R(rml)= cos(\akm \akl); which equals zero when the difference between the angles of the harmonics is p=2. The harmonics are fully correlated when the difference between the angles is 0, and they harmonics are anti-correlated when the angle are p out of phase. The total kth harmonic output power Pk of M combined channels is Pk = M m=1 akm 2 = M m=1 M l=1 akma kl = M m=1 M l=1 jakmjjakljrml: (2.35) The total harmonic power depends on both the magnitude and phase of each har- monic. If the phases are all equal (rml = 1), their amplitudes add coherently, and the maximum total harmonic power Pk;max is achieved, Pk;max = M m=1 jakmj !2 : (2.36) Ideally, a single metric is desired to describe the correlation of harmonics between a set of M channels; however, sincejakmjmay vary significantly between channels, I instead use a trio of metrics to describe the performance. The first 20 metric is the decorrelation value Ik, Ik , PkP k;max : (2.37) Ik measures the ratio of the actual harmonic power over the fully correlated har- monic power for a given harmonic k. For example, Ik = 1=4 indicates that the actual harmonic power is four times lower than the fully correlated case. When the average value of the real part of rml = 0 when m6= l, then the harmonics are ?fully decorrelated? and Ik M 1. The harmonics powers from each channel add instead of their voltages. The second metric is the total correlation coefficient defined in (2.10). Rk is closely related to Pk; Pk is Rk weighted by the amplitude of the harmonics. Ik provides a better understanding of the actual performance of a parallel array; how- ever, it is sensitive to harmonic power and a single large amplitude harmonic may significantly impact its value. Rk, on the other hand, is independent of harmonic amplitude and, therefore, provides a better measure of the harmonic correlation. Both metrics are useful for evaluating the correlation and performance of parallel ADC arrays. The third metric is the SFDR, which maintains the same definition whether for an individual ADC or ADC array: the ratio of the maximum signal over the maximum harmonic, SFDR , M 2PFS max(Pk): (2.38) where PFS is the full-scale power of the ADC, which is 0 dBFS. SFDR provides a single metric to underscore the correlation and the effectiveness of decorrelation 21 techniques, and enables a direct comparison to single ADC performance. 2.2 Prewhitening and Decorrelation Techniques Prewhitening is a common technique within the communications commu- nity. Prewhitening involves applying linear filtering to a signal, such that, after filtering, the power spectral density appears white (flat spectrum) [27]. The auto- correlation of the signal is made more like a delta function. Prewhitening allows for more efficient use of the available spectrum in a communications system. The noise added within the communications channel has a white spectrum. By reducing peaks and increasing the troughs in the spec- trum, the signal-to-noise ratio is maximized across all frequencies for the available signal power. When the signal is received, the opposite linear filter is applied to recover the original signal. The decorrelation techniques presented here are a variation on prewhiten- ing, where instead of attempting whiten the signal, the decorrelation technique attempts to whiten the errors introduced by the hardware. Then, when the chan- nels are combined the errors add as though they are independent. The challenge of combining many ADCs in parallel is relatively new and, as such, the literature record is very sparse. Table 2.1 shows the significant liter- ature for each ADC error source and decorrelation technique. Several papers and application notes discussed combining 2 to 4 ADC in parallel [11, 12, 13, 14]. An array of that size is unlikely to be limited by the correlated noise sources. 22 Table 2.1: Prior work on decorrelation techniques for different error sources. Decorrelation Technique Quantization Noise Sampling Noise Harmonics Dithering [20, 17] No effect - Phase Randomization - This Work [18, 19] Frequency Offsets - This Work [20, 21] Phase Cancellation - This Work This Work Clock Offsets - - This Work Rabideau, Howard and their colleagues at MIT Lincoln Laboratory published a series of conference papers beginning in 2001 on the decorrelation technique for very large arrays of both ADCs and other analog components [20, 21, 18, 19]. Their papers described the linear transform technique and outlined five methods to decorrelate the errors. In addition, a paper by Skartlien and Oyehaug discussed the decorrelation of quantization noise in large arrays using additive dithering [17]. In this section, I describe prior research on correlation of errors in parallel ADC arrays. The literature record is sparse. 2.2.1 Phase Randomization In a previous report, Howard et al. proposed and demonstrated a method to decorrelate mixer spurs and harmonics in parallel receiver arrays [18]. Further measurements of this technique were performed by Rabideau using four receivers 23 [19]. The technique involved applying a phase shift to the input signal of each channel by adjusting the local oscillator (LO) phase driving each mixer in the parallel array. The phase shift is then removed digitally at the output, resulting in a decrease in the harmonic correlation. The phase randomization technique seeks to reduce the correlation between harmonics by randomizing the harmonic phases, which should reduce the total correlation coefficient Rk. Fig. 2.3 schematically shows how the phase randomiza- tion technique is implemented. In this approach, the signal phase of each channel is offset by a random phase using a flexible LO Lm(t) and mixer. An ADC then digitizes the signal, which generates sampler and quantizer harmonics. A digital multiplier then removes the previously introduced phase shift and recorrelates the signal across channels. Since the harmonic phase is a multiple of the input sig- nal phase, even after signal recorrelation, the harmonic phases are still randomly distributed across channels. If the harmonics of each channel are of equal magni- tude (they are not) and randomly distributed in phase around the unit circle with a uniform distribution, then their sum approaches the Rayleigh distribution and the average total correlation coefficient Rk is M. Consider a phase and amplitude modulated signal w(t)= A(t)cos(wRFt p(t)) (2.39) where A(t) is the amplitude modulation, p(t) is the phase modulation, and wRF is the carrier frequency. The signal is mixed with an LO Lm(t)= 2cos(wLOt +qm(t)) (2.40) 24 Figure 2.3: Schematic diagram of phase randomization and frequency offset decorrelation techniques. where qm(t) is the introduced phase offset. The resulting output from each channel m is xm(t)= A(t)cos(wt + p(t)+qm(t)) (2.41) where wLO wRF = w. Next, the ADC digitizes the mixed signal xm and intro- duces harmonic distortion em. The digitized signal with distortion em(nT) is ym[n]= xm(nT)+em(nT): (2.42) where n is the sample index and T is sampling period. Finally, the Hilbert trans- formH(x) is applied to the digitized signal to extract only the positive frequencies [28] and the phase offset is removed, by multiplying by a complex exponential, e jqm(nT) zm[n]=H(ym[n])e jqm(nT) =A(nT)e j(wnT+p(nT))+H(em(nT))e jqm(nT): (2.43) When analyzing harmonics, I consider a sinusoidal input with A(t)= A and 25 p(t)= 0. In that case, the positive frequencies of the harmonic distortion em(nT) are H(em(nT))e jqm(nT) = akme jkwnT jqm(nT); (2.44) which using (6.1) becomes akme jkwnT jqm(nT) =jakmje j\akme jkwnT jqm(nT) =jakmje j(kwnT+(k 1)qm(nT)+fkm): (2.45) For the phase randomization technique, I set qm(t)=qm and (2.45) simpli- fies to jakmje j(kwnT+(k 1)qm+fkm): (2.46) The phase of the kth harmonic is, therefore, (k 1)qm +fkm. The goal of the phase randomization approach is to randomize the input signal phase qm and cause the harmonic phase to be randomly distributed around the unit circle with a uniform distribution. To begin, I define the harmonic voltage gain n, vu ut M m=1 M l=1 rml: (2.47) If the harmonics are successfully distributed around the unit circle, then n may be described by the Rayleigh distribution, assuming the harmonic amplitudes is equal across all channels. The exact probability distribution function of the voltage sum n of M tones uniformly distributed on the unit circle is fn(n)=n ?Z 0 gJ0(ng)[J0(g)]Mdg (2.48) 26 where J0 is the zeroth order Bessel function [29, 18]. For large M, and assuming that approximately M=2 phases are on each half of the unit circle [30, 31], the distribution approaches the Rayleigh distribution fn(n) 2nM e n2=M: (2.49) The expected value of Ik becomes Ik E[fn(n)n2dn]=M2 = 1=M; (2.50) which, in our 16-channel system is 10log10(16 1)= 12:0dB: 2.2.2 Frequency Offsets In addition to using phase offsets to decorrelate spurs, Howard et al. sug- gested an implementation using frequency offsets [20, 21]. Howard?s method causes the harmonics to be offset in frequency from channel to channel, so that when the channels are combined the harmonics do not add, resulting a SFDR im- provement of M2. I discuss Howard?s method as a way to introduce our extension of this technique. In our extension, I apply frequency offsets to each sampling clock, which causes aliased harmonics to occur at different frequencies. This ex- tension removes the need for a mixer, making it more appropriate for a wider range of systems. 27 2.2.2.1 Frequency Offsets on ADC Harmonics By applying different frequency offsets to the input signal of each channel using independent local oscillators, I can cause the harmonics to appear at dif- ferent frequencies for each channel. A frequency offset is simply a time-varying phase offset, and, as a result, the phase offset analysis from Section 2.2.1 may be applied using the appropriate qm(t)=wmt +qm for each channel. The phase error term qm accounts for the unknown starting phase of the signals at a particular time (for instance, t = 0). From (2.45), I find that the harmonic, after realignment, is akme jkwnT jqm(nT) =jakmje j(kwnT+(k 1)(wmnT+qm)+fkm): (2.51) After realignment of the signal frequency, each harmonic is offset in frequency from the original harmonics by (k 1)wm. The harmonics are not at the same frequency and, therefore, do not add. Ik is approximately M2, which is M times larger than expected from phase randomization. The harmonics are no longer at the same frequency and do not combine. Depending on the Nyquist zone of the harmonic and signal, (2.51) may need to be adjusted slightly, so that the final frequency offset is (k 1)wm. If both harmonic and signal are in either even or odd Nyquist zones, then the frequency offset is (k 1)wm; otherwise, the offset is (k+1)wm. 2.2.3 Dithering on Quantization Noise Dithering is the addition of an independent signal to the input of the ADC to randomize the ADC input. The dither signal randomizes the input to reduce spurs 28 Figure 2.4: Subtractive dither in a parallel ADC array. Figure 2.5: Additive dither in a parallel ADC array. and whiten the quantization noise. The dither signal is typically random noise or a tone. Common noise probability density functions (PDF) for the random noise are Gaussian or normal, uniform, triangular, digital, and sinusoidal [32]. Dithering is either subtractive, where the dither signal is subtracted from output, or additive, where the dither signal is not subtracted. Figures 2.4 and 2.5 show subtractive and additive dither systems in a parallel ADC system. The correlated input signal s(t) is added to a unique independent dither signal dm(t) for each channel m. The linear transform is gm(x) = x+dm. The 29 transformed input signal wm(t) = s(t)+dm(t) is quantized and sampled and the ADC output signal is xm[n]= s(nT)+dm(nT)+em(wm(nT)): (2.52) The inverse transform is g 1m (x)= x dm for subtractive dither and g 1m (x)= x for additive dither. The output for subtractive dither is ym[n]= s(nT)+em(wm(nT)) (2.53) and y[n]= s(nT)+dm(nT)+em(wm(nT)) (2.54) for additive dither. Quantization noise is a mapped error sequence; for every input voltage there is a single error voltage. If the ADCs are identical and if the input signals are cor- related, then the quantization noise is fully correlated between channels. Dithering reduces the correlation between the input signals and, therefore, reduces the cor- relation of quantization noise between channels. The correlation of quantization noise and the input signal is well-known [33]. In Bennett?s seminal paper on quantization noise [39], he observed that quantization noise is approximately uniform and white if four conditions hold. Bennett?s conditions (quoted from [40]) are: The quantizer does not overload The quantizer has a large number of levels The bin width or distance between levels is small 30 The PDF of the pairs of input samples is given by a smooth PDF Many common signals, including some sinusoids, do not meet Bennett?s condi- tions. The quantization noise of signals that meet Bennett?s conditions appears to be white, uniformly distributed with a variance D2=12, and independent of the input signal. D is the voltage of one least significant bit (LSB). Bennett?s results are only approximately true. Widrow?s Statistical The- ory of Quantization provides an exact condition for independence of quantization noise from the signal [41]. For an input signal s with a particular PDF fs(s) and characteristic function Fs(u)= Z ? ? fs(s)e jusds; (2.55) the quantization noise and signal are independent if the signal is band limited, such that Fs(u)= 0 for juj> pD: (2.56) Most signals do not meet the band limited condition; however, I could add an independent dither signal that meets the band limited condition and ensure inde- pendence, since the sum of two independent signals is the multiplication of their characteristic functions. Few dither signal of practical interest exists that meets the above band lim- ited condition [42]. The necessary and sufficient condition for independence and whiteness of a signal with added dither d is Fd i D = 0 for all i = 1; 2;:::; (2.57) 31 Table 2.2: PDF of common dither distributions. M is number of digital bits and K = 1;2;:::;M. Distribution Probability Density Function Uniform fd(d)= 1=D for f D2 d D2g Triangular fd(d)= dD2 + 1D f D d 0g fd(d)= dD2 + 1D f0 d Dg Gaussian fd(d)= 1p2ps d e d2=2s Sine fd(d)= 1 pD2 q 1 (2dD )2 D 2 d D 2 Digital fd (d)= 1M k2K d k M D which is a more relaxed condition than (2.56) [42, 43]. A uniformly distributed random variable with a width of i D meets the condition of 2.57. In addition, any arbitrary dither signal added to another dither signal that meets the condition for whiteness, such as triangular dither signal, also meets the conditions. Gaussian noise does not meet the condition for independence. Table 2.3 lists the char- acteristic function of five common dither distributions and when they meet the conditions of (2.57). As Table 2.3 shows, most common dither signals do not make the quanti- zation noise independent from the signal. In [42], the authors suggest using the 32 Table 2.3: Characteristic functions of common dither distributions. Only Uniform and Triangular distributions are the only distributions that can meet the conditions of (2.57). J0 is a Bessel function. M is number of digital bits. K = 1;2;:::;M. Distribution Characteristic Function Meet (2.57) Uniform Fd(u)= sinc(uD) D =D Triangular F(u)= sinc2(uD) D = 2D Gaussian Fd(u)= e 2p2u2s2d Never Sine Fd (u)= J0(puD) Never Digital Fd(u)= 1M k2K e j2pu(k=M)D Never 33 deviation factor, or ?D? factor, DF = Z [E(ejs)]2 fs(s)ds; (2.58) to calculate the dependence of the quantization noise on the input signal [44]. The ?D? factor is the expected value of the quantization noise conditional on the input signal. If the deviation factor is zero, then the quantization noise power remains approximately D2=12 but the quantization noise is completely independent of the signal. DF is zero only if E(ejs) = 0 or fs(s) = 0, but the latter is a trivial case. Given the characteristic function of the dither signal, the expectation in (2.58) is E(ejs)= ? i6=1 Fd i D e jp(i=D)sDi cos(pi) for i = 1; 2;::: [42]: (2.59) It is clear that if Fd(k=D)= 0 ? which are the necessary and sufficient conditions for independence ? then DF is zero. DF may be evaluated for other dither func- tions and the appropriate signal s. If Bennett?s conditions hold then a reasonable approximation of s is a uniform distribution from D=2. DF is signal-dependent noise power, so in a parallel ADC system, DF is the correlated quantization noise [32]. Without dither, DF is equal to D2=12 and goes to zero if conditions of (2.57) are met. Independent Gaussian dither has been discussed as a method to decorrelate quantization noise in simulation [20] and analytically [17]. Both results show that additive Gaussian noise reduces the correlation of quantization noise. Skartlien and Oyehaug analytically determined total correlated and uncorrelated noise in an additive dithered array [17]. They found the optimal dither power to minimize to 34 total noise power (including dither) is s2d;opt = D 2 (2p)2 ln(2(M 1)): (2.60) These results were not confirmed experimentally. 2.3 Summary of Chapter In summary, I have discussed the mathematical background of correlation and developed a set of metrics to evaluate parallel ADC array performance. I then discussed the previously developed decorrelation techniques, phase random- ization and frequency offsets. Finally, I discussed the previous results from the literature that demonstrated quantization noise is decorrelated from the signal us- ing dithering. 35 Chapter 3 Development of Experimental Test Bed 3.1 Test Bed Description The 16-channel test bed is composed of 16 ADCs, 16 DDSs as signal sources, amplifiers, anti-aliasing filters (AAF), clocks, and trigger sources, as shown in Fig. 3.1. Fig. 3.2 shows a photograph of the test bed, which required two 19 inch half height racks. The DDSs generate tones (as well as other modulated signals), which are amplified to full-scale of the ADC and filtered to remove out-of-band noise and harmonics. The ADC then samples the resulting signal at 120 MHz using by one of eight low-noise crystal oscillators. I designed the test bed to oper- ate at a nominal intermediate frequency of 90 MHz, which is in the center of the second Nyquist zone. This is a common frequency location in radio applications. The ADCs chosen were 16-bit Linear Technology LTC2208 capable of sam- pling at 130 MSPS. An RF transformer performs the single-to-differential conver- sion; I used the example input circuit from the datasheet [45]. Digital buffers can store up to 4 million samples before transferring them to a personal computer over 100 Mbit Ethernet. The large buffer length allows for long integration time to reduce the noise floor and expose many harmonics, while using a low data rate interface. The LTC2208 includes two gain settings (I use both depending on the experiment), a digital randomizer (which I generally used), and an internal sub- 36 Figure 3.1: Block diagram of experimental test bed consisting of 16 ADCs, 16 DDS, eight 120 MHz oscillators, an 800 MHz oscillator, amplifiers, and assorted buffers and distribution networks. 37 Figure 3.2: Photograph of the test bed composed of 16 ADCs, 16 DDSs, and supporting hardware. Test bed designed and assembled by myself. 38 Figure 3.3: Photograph of the ADC board. ADC board designed by Prologic Designs with guidance and troubleshoot by myself. tractive dither circuit (which I generally did not use). The buffer circuit accepted either an external LVTTL trigger or an internal trigger. The DDSs are composed of a Xilinx Virtex 4 field-programmable gate array (FPGA) that controls two Analog Devices AD9736 digital-to-analog converters (DAC) (each FPGA controls two channels). The DACs are 14-bit and capable Figure 3.4: Photograph of the front and back of the ADC board. 39 Figure 3.5: Simplified block diagram of custom DDS highlighting key enhancements for this work: phase ?incrementor? and additive white Gaussian noise generator. of operating at 1.2 GHz; however, our FPGA code was only able to run at 400 MHz with a double-data rate output resulting in a DDS clock frequency of 800 MHz. I implemented a standard DDS architecture [46]: the phase accumulator length is 32 bits and the phase-to-amplitude conversion look-up table is 17 bits, as shown in Fig. 3.5. The DDSs are capable of generating tones, pulsed tones, and pulsed linear frequency modulated waveforms. A seventh-order 360-MHz output reconstruction filter followed the DAC output. The maximum output power of each DDS is -3 dBm. I used a RS-232 serial connection to interface with the DDSs, which was chosen due to its low cost. I implemented two key features in DDSs for this work. First, I developed a simplified additive white Gaussian noise generator using a Ziggurat method simi- lar to [47, 48]. This allowed us to raise the noise floor of the DDSs as high as -100 dBc/Hz to act as a dither source. Second, I added a phase ?incrementor? to phase align the channels, as described in Section 3.2.3. The Mini-Circuits ZFL-500HLN+ amplifiers increase the -3 dBm signal to greater than the ADC full-scale power of +12 dBm. The amplifiers are a sig- nificant source of harmonic distortion (-45 dBFS maximum); however, the anti- 40 Figure 3.6: Dual DDS board using Xilinx Virtex 4 FPGA and Analog Devices AD9736. DDS board designed by Matt Gerwell 41 aliasing provide greater than -75 dB of attenuation to the second and higher har- monics, resulting in harmonics powers of -120 dBFS at most. The anti-aliasing filters have a nominal bandwidth of 24 MHz centered at 90 MHz. The 800 MHz clock is generated by multiplying 100 MHz ultra-low noise oscillator from Wenzel Associates by eight. The 800 MHz is phase locked to a master 10 MHz oscilla- tor. The final 800 MHz signal is divided eight ways and connected to each DDS board. Each of the eight 120 MHz oscillators from Wenzel Associates clocked two ADCs resulting in independent sampling noise in each pair of channels. Each independent oscillator was phase locked to the master 10 MHz signal. Finally, the LVTTL trigger was generated by an Agilent 81104A pulse generator. The trig- ger was divided 24 ways and buffered with two Texas Instruments CDC318ADL clock drivers resulting in a trigger rise time of approximately 3 ns. The test bed includes a low noise 120 MHz clock array and an 800 MHz clock. Fig. 3.7 shows the configuration of the 120 MHz clock array. A 10 MHz reference is multiplied to 120 MHz using 4 and 3 multipliers. Eight individual oscillators are then phase locked to the common 120 MHz reference. Figs. 3.8 and 3.9 show the top and front of the clock array. George Vetticad assembled the clocks. Fig. 3.10 shows the 800 MHz clock configuration. A 10 MHz reference clock is multiplied by 10 to 100 MHz and phase locked to a low noise 100 MHz oscillator. The output of the 100 MHz oscillator is then multiplied by 8 in two steps, split 8 ways and filtered. One clock signal is fed to each DDS board, which has two output channels. 42 Figure 3.7: Block diagram of 120 MHz clock array. Figure 3.8: Front panel of 120 MHz clock array. Figure 3.9: Top down view of 120 MHz clock array. Clock assembly designed by myself and assembled by George Vetticad. 43 Figure 3.10: Block diagram of the 800 MHz clock. Clock assembly designed by myself and assembled by George Vetticad. 3.2 Design Goals The goal of the 16-channel ADC test bed is to determine the performance capability of large parallel arrays that may be limited by noise and distortion cor- relation. To achieve this goal, I identified four design goals of the test bed: (1) the test bed must be able to measure low levels of partial correlation and provide significant statistical variation; (2) the measurement system?the signal sources and digital buffers?must be clean with low noise and spurs; (3) the signal sources must be well correlated from channel to channel; (4) the ADC channels must have excellent isolation between them. The section outlines the reason for each, steps I took to implement these goals, and any challenges I encountered. 44 3.2.1 Large Number of Channels When the number of channels is small the impact of correlation is small compared to a large number of channels. This impacts both the total parallel array performance and our ability to measure the correlation. Consider the error sequence rm generated in each channel m =1;:::;M, with M being the total number of channels. In our parallel array, I directly sum the error sequence digitally to form the total output error sequence R R = M m=1 rm: I find the total output error power PR by taking the expectation of R2 PR = E[R2]= E " M m=1 rm ! M n=1 rn !# ; which, since expectation and summation are both linear operations, can be ex- panded as PR = M m=1 M n=1 E[rmrn]: (3.1) The total power is the sum of M2 pair-wise correlations E[rmrn]. The correlation coefficient is defined as rmn = E[rmrn]pE[r2 m]E[r2n] : The correlation coefficient is one when the sequences are fully correlated, zero with no correlation, and minus one when the sequences are anti-correlated. If I assume that the single channel power, which I will denote as Pr = E[r2m], is the same for all channels then the total power (3.1) becomes PR = M m=1 M n=1 rmnPr: (3.2) 45 I further simplify (3.2) by recognizing that r= 1 when m = n, and by defining the average correlation coefficient ?r as ?r= 1M2 M M m=1 M n=1 rmn; in which case, (3.2) becomes PR = Pr M+(M2 M)?r (3.3) Table 3.1 shows the error power increase due to correlation PR=(MPr) PR MPr =(1+(M 1)?r) (3.4) for several values of ?r and M. The larger the number of channels, the greater the impact of partial correlation on limiting the performance of the parallel array. For example, a large average correlation coefficient of 0.5 increases the total error power by 1.76 dB for a two-channel ADC array, while it increase the total error power of a 16-channel ADC array by 9.29 dB. This impacts both performance of the ADC array and our ability to measure partial correlation; therefore, I designed the test bed with a large number of channels. In addition to improving our ability to measure low levels of partial cor- relation, the 16 channels provides a large sample set to draw statistical behavior on harmonics and noise. This is particularly important for quantizer nonlinear- ities, which can vary significantly from ADC to ADC. Having a large number of channels prevents statistical outliers from impacting the overall performance measurements 46 Table 3.1: Error power increase due to correlation PR=(MPr) for several values of ?rand M. The larger the number of channels the greater the impact of partial correlation and the greater our ability to measure the partial correlation. Our test bed enables us to observe average correlation coefficients ?r approaching 0.01. M ?r= 0 ?r= 0:01 ?r= 0:10 ?r= 0:50 ?r= 1:00 2 0.00 dB 0.04 dB 0.41 dB 1.76 dB 3.01 dB 4 0.00 dB 0.13 dB 1.14 dB 3.98 dB 6.02 dB 8 0.00 dB 0.29 dB 2.30 dB 6.53 dB 9.03 dB 16 0.00 dB 0.61 dB 3.98 dB 9.29 dB 12.04 dB 32 0.00 dB 1.17 dB 6.13 dB 12.17 dB 15.05 dB 64 0.00 dB 2.12 dB 8.63 dB 15.12 dB 18.06 dB 47 Figure 3.11: Measured phase noise from DDS at 100 MHz output frequency using 800 MHz clock. The DDS phase noise from each channel is comparable to com- mercial signal generators. 3.2.2 Low Noise and Spur Measurement System As with most measurements, it is desirable that the measurement system?s? signal sources and digital buffers, in this case?noise and spurious signals (spurs) be below that of the device under test (parallel ADCs). In particular, I am con- cerned about the signal source phase noise [49]. I chose to use DDSs because their phase noise is comparable to commercial signal generators and independent from channel to channel, so the resulting total noise is much lower than most com- mercial signal generators [50, 51]. Fig. 3.11 shows the measured phase noise of a single channel, measured with a DDS output frequency of 100 MHz. The phase noise was measured using a cross-correlation phase noise measurement system similar to [52]. The DDSs generate harmonics that alias into the anti-aliasing filter passband that are large relative to the ADC harmonics ( 75 dBFS or less for the DDSs com- 48 pared to 85 dBc for the ADCs). The normal AAFs limit the signal bandwidth to 24 MHz centered at 90 MHz. The filters have greater than 60 dB of rejection at 138 MHz, which is the lowest frequency in the third Nyquist zone that aliases into the passband of the filter, (120 102)+120 = 138 MHz: Fig. 3.12 shows the first 100 ADC and DDS harmonics for an input frequency of 97:59979248 MHz. The ADC harmonics are plotted in the first, second, and third Nyquist zones. While the in-band DDS harmonics from 78 to 102 MHz may be large, only the fiftieth harmonic coincides between the ADC and DDS, demonstrating that I can separate the ADC and DDS harmonics in the frequency domain. The anti-aliasing filter removes the other coincident harmonics. The number of coincident harmonics is a small fraction of the first 100 harmonics, since the ADC and DDS clocks (120 and 800 MHz, respectively) are not closely related. The second significant source of noise and spurs is the digital buffer that collects the digital data from the analog-to-digital converter. I sought to minimize the noise contribution of the digital circuitry isolating the components as much as possible. I electrically isolated the two analog and digital boards using a 3/8? piece of aluminum. In addition, I isolated the input, clock, and Ethernet connections from the chassis. To verify that the digital buffer added minimal noise, I measured the noise figure (NF) of the ADC using the Y-factor method [53]. Fig. 3.13 shows the block 49 Figure 3.12: Plot of first 100 ADC harmonics in the first, second, and third Nyquist zones and the first 100 DDS harmonics for a frequency of 97:59979248 MHz. Only the fiftieth harmonic of both the ADC and DDS occur at the same frequency within the passband of the anti-aliasing filter. The blue lines mark the passband of our bandpass anti-aliasing filter, and the green lines mark the boundaries of the first, second, and third Nyquist zones. 50 Figure 3.13: Y-factor noise figure measurement technique uses two calibrated noise sources to measure the noise figure of the ADC. The measurement required a preamplifier due to the high noise figure of the ADC. diagram of the Y-factor method. In the Y-factor method, the ADC noise figure is measured applying two calibrated noise sources with known noise temperatures Tec and Teh to the ADC input and measuring the two output noise powers Ph and Pc. The noise temperature of the ADC Te is then calculated using Te =(Teh Y Tec)=(Y 1) (3.5) where Y = Ph=Pc. The noise figure is NF = 10log10(1+Te=290): (3.6) I used a calibrated noise diode and 50 W termination as the noise sources. I measured the preamplifier and filter gain and noise figure using a noise figure capability of an Agilent E4440A. Fig. 3.14 shows the measured noise figure for 16 ADCs, which match the specification of 30.6 dB with gain ?off? and 29.6 with gain ?on? when the RF transformer loss is included. From this match, I conclude that the digital buffer adds minimal noise to the ADC. In addition to white noise, the digital buffers could generate spurs. I mea- sured the ADC noise floor spectrum shown in Fig. 3.15 by connecting a 50 W 51 Figure 3.14: Measured noise figure matches the specification when RF transformer loss is included. termination to an ADC, collecting 100 records with 221 samples in each, and av- eraging the power of each spectrum. The ADC noise floor is composed of many spurs; however, all are below -105 dBFS, which is well below most of our har- monic measurements. 3.2.3 Excellent Signal Correlation Between Channels Signal-dependent noise and distortion is potentially correlated; however, to see this correlation the signals must be highly correlated. The DDSs allow us to achieve very high levels of correlation between channels with the addition of the phase ?incrementor? shown in Fig. 3.5 and mentioned earlier. Each DDS receives a common 800 MHz clock and trigger. Unfortunately, the rise time of the trigger was too long (3 ns rise time versus 1.25 ns clock pe- riod), such that the trigger did not reliably occur on same clock period for all 52 Figure 3.15: ADC noise floor. DDSs. This was a flaw in our DDS design. To synchronize the channels, I started all the DDSs running with the arbitrary starting phase. Then I would measure the phase using the ADCs and increment the phase accumulator using the phase ?incrementor? until the channels were phase aligned. Fig. 3.16 shows excellent phase (standard deviation of 170 rad) and amplitude matching from the 16 DDSs using this closed-loop calibration technique. 3.2.4 Excellent Isolation Between Channels I designed the test bed to provide excellent isolation between channels by housing each ADC in a separate enclosure, as shown in Fig. 3.2. Even in separate enclosures, however, I found that there was insufficient isolation between channels for some harmonic measurements. I observed the insufficient isolation when measuring the amplitude stability of the second harmonic over a set of different captures. For the first set of 10 cap- 53 Figure 3.16: Output of 16 ADC channels demonstrating phase incrementation alignment technique. tures, the input signal phase of each channel was kept constant and the measured second harmonic power was constant as expected. For the second set of 10 cap- tures, the input signals phase were all adjusted by the same amount between each capture and the second harmonic remained constant as expected. On the third set of 10 captures, the input signal phase of each channel was adjusted by a random amount and the amount was different for each channel. Fig. 3.17a shows the sec- ond harmonic power for this third set of 10 captures for each ADC channel. Each line is one of 10 captures. The variation was as large as 20 dB from capture to capture for any given ADC. This second harmonic power variation was unexpected. Our hypothesis is that there was insufficient isolation from channel to channel, and that the signal from the adjacent channels was leaking into the clock line. This unwanted clock 54 Figure 3.17: (a) When the input signal phases were adjusted randomly across channels the power of the second harmonic varied significantly. (b) After hardware modifications to increase isolation, the variation was dramatically reduced. signal at the signal frequency also sampled the input signal, resulting in a spur at the same frequency as the second harmonic. The spurious clock signal was the sum of multiple channels, so that when all the phases were changed randomly the spurious clock signal phase also changed randomly. When all the input phases were changed by the same amount then the combined spurious clock phase did not change from channel to channel. The resulting spurious ?second harmonic? then either destructively or constructively combined with the ADC generated second harmonic. A reasonable estimate for power of the spurious ?second harmonic? was about -92 dBFS for most channels, since the measured second harmonics below this level showed greater variation from more complete destructive inter- ference. Comparing high-power Channel 10 to low-power Channels 3 and 16, the 55 lower power harmonics vary more. I made several modifications to the test bed to reduce the crosstalk. To re- duce RF leakage on the power lines, I added additional bypass capacitors to the ADCs and amplifiers. I implemented a star ground to reduce signal leakage via the ground [54]. I also added additional grounds to the chassis holding the ADCs. Finally, I replaced all the single-shielded signal and clock cables with double- shielded cables to reduce radiated electromagnetic interference (EMI). Single- shielded cables only provide about -55 dB of attenuation, while double-shielded cable provides -110 dB of attenuation [55]. This reduced the ambient electric fields near the cables when measured with a small monopole antenna connected to a spectrum analyzer. I then repeated the earlier experiments, where I changed the input signal phase randomly from channel to channel and record to record. Fig. 3.17b shows that the resulting power of the second harmonic was far more stable. The changes to the test bed significantly improved the isolation between channels and elimi- nated the variation between captures. 56 3.3 Test Bed Characterization Each ADC was fully characterized to ensure it meets specifications in the following areas: Equivalent Input Referred Noise (EIRN) DC Offset Full-Scale Power Frequency Response Noise Figure Signal-to-Noise Ratio Spur-Free Dynamic Range Integral and Differential Nonlinearities (INL and DNL) 3.3.1 Equivalent Input Referred Noise and DC Offset The EIRN is a measure of the internal noise of the ADC without an input signal, which adds sampling noise. EIRN was measured by terminating the input of the ADC and measuring the standard deviation of the resulting noise [1]. Sev- eral captures were taken to reduce any fluctuations in the measurement. The DC offset is found by calculating the mean output for the same data. The data sheet specifies a 78 dBFS noise power, which is about 10D2 with gain off and 17D2 with gain on [45]. The DC offset is specified as 2 mV, which is 60D with gain off and 90D with gain on. Fig. 3.18 shows that the measured EIRN for all 16 ADCs meet specification. 57 Figure 3.18: ADCs meet EIRN specification. Figure 3.19: The DC offset of some ADCs are out of specification, but this does not im- pact correlation measurements. Fig. 3.19 shows that the DC of some of the ADCs is out of specification; however, this does not impact the performance on these experiments. 3.3.2 Full-Scale Power and Frequency Response The full-scale voltage of the LTC2208 is 2.25 V with the gain off and 1.5 with the gain on. The full-scale power in a 50W system is 11.0 and 7.5 dBm with gain off and on. The measured full-scale power differs from the expected power due to gain errors in the ADC and loss from the input RF transformer. 58 Figure 3.20: Measured full scale power shows good matching between channels and RF transformer loss of about 1 dB. I measured the full-scale power by connecting a sinusoidal signal (from a signal generator) to the input of the ADC and capturing the output. I increased the input power in 0.01 dB increments in an automated loop until a sample on the ADC output was at full-scale. The input frequency must be chosen to excited many different output bits [1]. I then measured the signal that caused saturation on the spectrum analyzer. Fig. 3.20 shows the measured results. The RF transformer loss is about 1 dB. 3.3.3 Frequency Response I measured the magnitude frequency response by applying a 75 MHz sinu- soidal signal to the ADC and measuring the input power at the ADC. Then, using an automated loop, I changed the frequency in small increments and measured the power of the ADC data. Fig. 3.21 shows the frequency response is basically flat over the frequency bands of the anti-aliasing filters. Fig. 3.22 shows that the 1 dB 59 Figure 3.21: Measured frequency response shows increasing loss as frequency increases and excellent matching from channel to channel (small gain error). and 3 dB (relative to a 75 MHz input) bandwidths are about 180 MHz and 280 MHz for each ADC. 3.3.4 SNR I did not directly measure the maximum SNR, since the noise of the signal generators is well above the noise of the ADC. The SNR is inferred through SNR(dB)= PFS ( 174+NF+10log10(fs=2): (3.7) Fig. 3.23 the SNR matches the data sheet specification when RF transformer loss is included. 60 Figure 3.22: The 1 dB and 3 dB bandwidths are about 180 MHz and 280 MHz for all ADCs. Figure 3.23: Measured SNR matches the specification when RF transformer loss is in- cluded. 61 Figure 3.24: Measured SFDR with gain off. 3.3.5 Spur-Free Dynamic Range SFDR is the ratio of the full-scale signal over the highest spur. The highest spur is usually the second or third harmonic of the input signal. I measured the SFDR by applying a nearly full-scale signal at 98.5 MHz from a signal generator to the ADC through an anti-aliasing filter. I measured the power of the ten largest spurs after filtering known signal generator spurs. Figures 3.24 and 3.25 show the measured SFDR with gain off and on. The data sheet specification is 90 dBc and the second and third harmonics do not always meet this, but all higher order harmonics do. With gain on, the third order harmonic power seems to decrease. 3.3.6 Integral and Differential Nonlinearities To characterize our ADCs, I measured the performance metrics differential and integral nonlinearities (DNL and INL) of each channel [1]. DNL is the dif- ference in the measured step size between each ADC output bit from the ideal step size D. INL is the deviation of the transfer function from the ideal transfer 62 Figure 3.25: Measured SFDR with gain on, which, in general, improves the third order harmonic performance. function, and is also the cumulative sum of the DNL. I measured the DNL and INL of the 16 ADCs using a sine histogram test described in IEEE Standard 1241-2000 [56]. In the sine histogram test, I collect many samples of a high purity signal to form a large histogram. I then deter- mine the DNL and INL from the deviation of the histogram from the ideal case. The test requires a large number of samples for each ADC output bit to reduce the measurement error. For each ADC, I recorded 91000 different captures each with a length of 65536 samples. Fig. 3.26 shows a block diagram of the sine histogram measurement setup. I overdrove the input about 0.5 dB, which is more than enough according to the standard. The frequency 30503540:04 Hz was se- lected, such that the number of cycles per record 16659 is relatively prime with the record length 65536. The 1 MHz narrowband filter is included to suppress signal generator spurs and reduce source noise, both of which are necessary to achieve the required spectral purity. 63 Figure 3.26: Block diagram of INL measurement setup. The signal frequency was chosen such that the number of cycles per record 16659 is relatively prime with the record length 65536. The filter improves the purity of the test signal, reduces spurs and noise. Fig. 3.27 shows the measured INL for all 16 channels. Each subplot shows four ADC channels. Ideally, the INL would be 0 for all output bits of the ADC, but this is clearly not the case. For most ADCs, the INL is within 2D. The INL measurements show a large scale ?sinusoidal? or ?polynomial? structure and a small scale ?jagged? structure. The large scale structure of the INL measurements is similar among some channels, but not others. I, therefore, expect the errors due to these transfer functions to be at least partially correlated. The measured INL meets the manufacturer?s specifications of a typical error of 1:2D and a maximum INL error of 4:0D [45]. Furthermore, to verify the fidelity and repeatability of our measurements over multiple runs, I took 3 INL measurements of the same ADC. Fig. 3.28 shows excellent matching between measurements of the same ADC, which provides confidence that our measurement technique is accurate and consistent. The count by count RMS difference of the INL between Run 1 and Run 2 is 0:0198D, between Run 1 and Run 3 is 0:0237D, and between Run 1 and Run 3 is 0:0183D showing excellent reproducibility. 64 Figure 3.27: Measured INL from all 16 ADCs show complexity of quantizer transfer function errors. The large scale structure exhibits similarities from channel to channel, implying some level of correlation. 65 Figure 3.28: Three measurements of INL and DNL from the same ADC prove the excel- lent reproducibility of the measurements. 3.3.7 Characterization of DDSs The DDS noise is dominated by phase noise. Fig. 3.29 shows a plot of the phase noise profile. For these experiments the white noise region > 1 MHz is more important than lower offset frequencies. The phase noise in the white region is -150 dBc/Hz. The phase noise was measured using a in-house phase noise measurement test set. The inherent phase noise of the measurement system is well below the phase noise of the DDS. The DDS includes a low pass reconstruction filter, which cause a non- uniform frequency response. The cutoff frequency of the 7-pole Chebyshev filter is 360 MHz. 66 Figure 3.29: DDS phase noise at 100 MHz output frequency with 800 MHz clock. 3.3.8 Characterization of 120 MHz Clocks The power output of each channel is 11.5 dBm. Each channel connects to two ADCs through a RF splitter and the power at the ADC is about 8 dBm. The recommended power is 12 dBm, but this should have negligible performance impact and it is impractical to increase the gain by only 3 dB. The oscillators in clock array are very low noise. All of the oscillator com- ponents are from Wenzel Associates, Inc. The measured phase noise is about -170 dBc/Hz for frequencies greater than 10 kHz. This exceeds the specification of -165 dB/Hz. The clock phase noise is low enough that it does not increase the ADC noise floor significantly. The phase noise PN is converted to timing jitter through ? = p 2 10(PN+10log10(B))=10 2p 120 106 ; (3.8) 67 Figure 3.30: Measure phase noise is below white floor specification of -165 dBc/Hz. where B is the clock input bandwidth of the ADC [1]. I estimated the clock input bandwidth as about 150 MHz based on the equivalent circuit in the data sheet [45]. The timing jitter ?, based on estimated bandwidth and the measured phase noise, is 73 fs. Fig. 3.31 shows the SNR reduction at the maximum frequency of interest is about 2 dB. This is insignificant relative to the phase noise of the DDSs. 3.3.9 Characterization of 800 MHz Clock The 800 MHz clock is also very low noise. The 100 MHz oscillator has lower noise than the 120 MHz oscillators; it is -174 dBc/Hz. I was not able to measure the phase noise, but Fig. 3.32 shows the specified phase noise from com- ponents. The clock phase noise at the output of the DDS is reduced by the ratio of the output frequency over the clock frequency. The clock phase noise contribution 68 Figure 3.31: The SNR is reduced by 2 dB at the highest frequency of interest. to the DDS phase noise at 90 MHz is 20log10 f out fclock = 20log10 90 800 = 19 dB (3.9) lower than the specified clock noise. 69 Figure 3.32: The phase noise of the 800 MHz clock is very low. 70 Figure 3.33: Block diagram of S-band receiver. 3.4 Design and Characterization of S-Band Receiver for CPCR Measurements The S-Band receiver used to make CPCR measurements was designed by Joe Sluz, Matt Gerwell, and Al Wu [6]. The receiver has an RF bandwidth from 2.7-3.7 GHz and an instantaneous bandwidth of 15 MHz. The receiver uses two downconversion stages with the first LO variable from 3.35 to 4.35 GHz, and the second LO fixed at 725 MHz. The ADC is an Analog Devices AD6645, which is 14 bits and sampled at 100 MHz. The receiver parameters are listed in Table 4.1. 71 Figure 3.34: Photo of S-band receiver. 72 3.5 Summary of Chapter In summary, I have developed a unique test bed using 16 state-of-the-art ADCs to investigate noise and distortion correlation. The test bed was designed around four design goals: Large number of channels Low noise and spur measurement system Excellent signal correlation Excellent isolation between channels Each design goal was met. In addition, the test bed was throughly characterized. 73 Chapter 4 Correlation of Signals Interference cancellation techniques in multi-channel radar and communi- cations system, such as adaptive beamforming, are only effective if the response of each channel used is well matched [15, 16]. Though hardware variations be- tween channels limit the intrinsic channel response match, digital equalization techniques improve channel-to-channel matching. Receiver channel nonlineari- ties, however, limit the level of channel matching achievable. CPCR is a measure of the matching between two channels, which I define as the ratio of the output power of a reference channel Pout to the output power of the difference of the output signals (residue) Pr, CPCR , PoutP r : (4.1) CPCR may be defined either as (4.1) or its reciprocal; I use (4.1) so that the CPCR is greater than 1 and a maximum CPCR describes the highest degree of channel matching instead of a minimum. CPCR measures the digital equalizer perfor- mance. In addition, CPCR may be used to infer higher level system parameters, such as null depth in an interference cancellation system, although, CPCR is not a direct measure of these characteristics [57, 58]. Experimentally, CPCR is measured by applying the same input signal to the two channels under test, either with or without digital equalization, and subtract- 74 ing the two outputs to find Pr. In order to reveal any mismatch within the channel bandwidth, the CPCR measurement signal should excite all frequencies within the bandwidth. The most desirable input signals will equally excite all frequencies within the channel bandwidth. Among the choices of excitation signals, linear frequency modulation (LFM) and band-limited Gaussian noise (BLGN) wave- forms satisfy this requirement, as they both exhibit uniform power spectral den- sities within the channel bandwidth [57]. They differ, however, in their temporal characteristics: LFM sequentially excites each frequency, while BLGN excites all frequencies simultaneously. In this paper, I compare the effect of the use of LFM and BLGN measure- ment signals on CPCR, and seek to determine the effect of hardware nonlineari- ties, including ADC saturation and analog-component third-order nonlinearities, on the measurement of CPCR. I do not directly evaluate the advantages or dis- advantages of either signal for training purposes to generate equalization coef- ficients. In Section 4.1, I describe the hardware model used and determine the impact of noise on the CPCR. In Section 4.2, I determine the impact of ADC saturation on LFM and BLGN, and, in Section 4.3, I determine the impact of third-order nonlinearities. Finally, in Section 4.4, I experimentally confirm the re- sults using a pair of S-band receivers. I show that the maximum achievable CPCR is lower for BLGN than LFM measurement signals due to ADC saturation and third-order nonlinearities. 75 Figure 4.1: Block diagram of the CPCR measurement. Each channel contains a single receiver, and one of the legs possesses a digital equalizer heq and a single-tap equalizer g. Our receiver model includes both third-order nonlinearities and noise contributions, and the ADC model specifies the ADC full-scale voltage, F. 4.1 CPCR Measurement Technique and Receiver Model Fig. 4.1 shows a detailed block diagram of our CPCR measurement setup. In this approach, CPCR is measured by applying a common input signal, denoted ?measurement signal,? to both channels under test. The equalizer is trained to match Channel 1 to Channel 2. The outputs are digitally captured and the differ- ence is taken. The residual power Pr and CPCR are then measured. Channel 1 consists of a receiver, modeled to include third-order nonlineari- ties and thermal noise, an ADC, a digital equalizer heq, and a single-tap adaptive equalizer g. Channel 2 consists of a similar receiver, again modeled with third- order nonlinearities and noise, and an ADC. As Channel 2 is considered the ?ref- erence? channel, no equalizer is included in that leg. The noise of the ADC is assumed to be included in the receiver noise and the ADC clips signal voltages with magnitudes greater than the full-scale voltage F. Throughout the analysis, 76 I assume a uniform magnitude frequency response and no phase error, such that the channel gain completely accounts for all differences between channels. I also assume the equalizer is perfectly calibrated and completely cancels the measure- ment signal when the receiver is operating linearly; the adaptive equalizer g only corrects for nonlinearities. I make these assumptions for mathematical simplicity and to address more effectively the effects of nonlinearities. A complete listing of parameters from Fig. 4.1 follows: x is the common measurement signal. yi is the output voltage of receiver i, yi = p Gix aix3 +ni: (4.2) zi is the output voltage of channel i. For Channel 1, z1 is the output after the single-tap equalizer g, and ?z1 is the output before g. Gi is power gain of receiver i, G1 > G2. ai is third-order voltage gain of receiver i and is related to the input third- order intercept (ITOI) by [59] ai = 23 pG i ITOIiR: (4.3) Note that ITOI is in Watts, ai has units V 2, and R is the impedance of the system. I use R = 1W for simplicity. ni is output noise voltage of receiver i, including ADC noise. F is the full-scale voltage of the ADC and is the same for both receivers. heq is the equalizer gain, which, if I assume a uniform frequency response 77 in both channels, is heq = rG 2 G1: Pin is the measurement signal power, E[x2]. r is the residue voltage. Pr is the residue power, E[r2]. Pout is the output power of the reference channel, E[z22] g is an adaptive single-tap equalizer that minimizes the residue, and g = 1 if the equalizer is ideal. The single-tap equalizer g is often included in digital equalization to correct for less than optimal equalizer weights heq. The adaptive equalizer is recalculated on shorter time intervals than the standard equalizer heq. For this work, I wish to understand the impact of the single-tap equalizer, if any, on the maximum CPCR. The single-tap equalizer g minimizes the residue power over a collection of samples, ? ?gPr = ? ?g E[(gopt ?z1 z2)]= 0: I solve the previous equation and find that the optimal g is gopt = E[z2 ?z 1] E ?z21 : If the signals are well matched, such that z2 ?z1, as is the case for linear ADC operation, then g 1 and the single-tap equalizer has no effect on the CPCR. When the signals differ, g adjusts the gain and phase to minimize the residue. 78 4.1.1 CPCR of Linear Channels In this section, I determine the CPCR of two channels in the case of ADC linearity (no saturation, infinite F) and no third-order nonlinearities (a1=a2=0). Assuming the equalizer perfectly matches the channels, such that g = 1, the input signal is fully canceled and the residue is simply the difference between the noise of each channel r = rG 2 G1 n1 n2: The noise in each channel is independent and, as a result, the power of the residue is the sum of the two noise powers Pr = E r2 = E 2 4 r G2 G1 n1 !23 5+Eh(n2)2i = G2G 1 Pn;1 +Pn;2 = Nt: (4.4) Nt is about twice the noise power of a single channel, in other words, Nt 2Pn;2 assuming that G2 G1. I apply the residue power to (4.1) and find that the CPCR is CPCR = G2PinN t = Pout2P n;2 : (4.5) Therefore, the CPCR without nonlinearities is approximately half the output signal-to-noise ratio (SNR) of one receiver regardless of the type of measurement signal used. In practice, the CPCR increases linearly with increasing input power, until nonlinearities increase the residue and limit the maximum CPCR. 79 Figure 4.2: Demonstration of clipping on a sinusoidal input. The residue of saturated signals is increased relative to the unsaturated case. 4.2 CPCR Limitations Due to ADC Saturation In the following analysis, I assume there are no third-order nonlinearities (a1 =a2 = 0). I also assume g = 1 for the analysis, although I allowed g6= 1 in the simulations performed. ADC saturation results in the ?hard? clipping of the receiver output signal yi. Any signal voltage greater than F is limited to F, and any voltage less than F is limited to F. After equalization, the output voltage zi at saturation is different between channels due to the gain difference; therefore, when one (or both) signals saturate the ADC, the output voltages differ and the residue increases above zero (excluding noise), as depicted in Fig. 4.2. Fig. 4.2a shows the output of two channels with slightly different gains prior to equalization when both signals are saturated. Before equalization, the maximum voltage of each signal is F = 1 V. After equalization, shown in Fig. 4.2b, the maximum voltage of Channel 2 remains at F, but the maximum voltage of Channel 1 is FpG2=G1 and therefore the residue increases above zero (excluding noise). 80 The saturated transfer function of each channel is zi(x)= 8> >>> >>< >>> >>>: F q G2 Gi ; Fp Gi x pG 2x; FpGi < x < FpGi F q G2 Gi ; x Fp Gi assuming a1 =a2 = 0 and g = 1. As a result, the residue r(x)= z1(x) z2(x) is r(x)= 8> >>>> >>> >>>> >>< >>> >>>> >>> >>>> : F q G2 G1 F; Fp G2 x F q G2 G1 pG 2x; FpG1 < x FpG2 0; FpG 1 x FpG 1 F q G2 G1 + pG 2x; FpG2 x < FpG1 F q G2 G1 +F; x Fp G2 (4.6) As can be seen from (4.6), the residue power due to saturation depends intimately upon the likelihood that the input signal voltage saturates the ADC, and, as a result, the CPCR will vary depending on the specific input measurement signal used. By evaluating the variance of r for a given measurement input signal, the residue power due to saturation (including the noise) is Pr = ?Z ? r2(x) f(x)dx+Nt where f(x) is the PDF of the measurement signal voltage x. The PDFs of both the LFM and BLGN measurement signals are symmetric about zero, so, from (4.6), 81 Figure 4.3: Comparison of LFM and BLGN probability density functions at the same power (LFM amplitude A = 1 and BLGN variance s2 = 12 ). the residue power simplifies to Pr =2 ?Z F=pG2 F rG 2 G1 F !2 f(x)dx +2 F=pG2Z F=pG1 F rG 2 G1 p G2x !2 f(x)dx+Nt: (4.7) With this relation, I can calculate the effect of saturation on residue power for an LFM and BLGN input signal. Note that (4.7) reduces to (4.4) when x does not saturate the ADC, in other words, whenjxj< F=pG1. Fig. 4.3 shows the PDF of the LFM (black) and BLGN (blue) measurement signals with the same power. Though both measurement signals have the same total power, the PDF varies sig- nificantly, with the peak-to-peak voltage variation much greater for BLGN than LFM. As a result, the saturated CPCR is expected to differ depending upon which measurement signal is used. 82 4.2.1 Effect of ADC Saturation on CPCR with LFM Measurement Signal The PDF of an LFM measurement signal x = Asin(q(t)) with amplitude A is [60] f(x)= 8 >>< >>: (ppA2 x2) 1; x >>> >>> >>>> >>>> >>< >>> >>>> >>> >>>> >>>: Nt; A< FpG 1 Nt +2G2 AR Fp G1 (F=pG1 x)2 ppA2 x2 dx; Fp G1 F=pG1. Referring to (4.9), the closed form 83 solution of the second interval is Pr(A)=Nt + 2pG2 A 2 2Fp G1 s A2 F 2 G1 +G2 A2 2 + F2 G1 1 2p sin 1 FApG 1 : (4.11) From (4.11), I see that Pr increases quickly when A is greater than but near F=pG1 since the derivatives the arcsine and square root functions are very large. A sample case that shows how the maximum CPCR is reached as a function of measurement signal power is in Section 4.2.3 below. 4.2.2 Effect of ADC Saturation on CPCR with BLGN Measure- ment Signal I determine the CPCR with a BLGN measurement signal in the same man- ner, but substituting the PDF of BLGN, f(x)= 1p2ps2 e x 2 s2 (4.12) into (4.7). The integrals may be solved analytically using error functions; how- ever, I chose to evaluate them numerically, as shown below. The resulting CPCR is CPCR(s)= G2s 2 Pr(s): (4.13) 4.2.3 Discussion of Maximum Saturation-Limited CPCR Fig. 4.4 shows the CPCR as a function of the input measurement power for both LFM (black) and BLGN (blue) signals calculated by substituting (4.11) into 84 Figure 4.4: Analytical and simulated saturation-limited CPCR versus measurement signal power for the receiver parameters shown in Table 4.1. The maximum CPCR for BLGN measurement signal is 8 to 10 dB below that of the LFM measure- ment signal. For both measurement signals, the simulations closely match the analytical results. (4.10) for LFM and (4.12) into (4.7) and (4.7) into (4.13) for BLGN using the receiver parameters in Table 4.1. The measurement signal power is in units of dBFS, which is dB relative to the full scale of the Channel 2 ADC (Fig. 4.1). In addition, Fig. 4.4 shows a numerically simulated CPCR (dotted) for each case. In the LFM simulation, I swept an ideal LFM measurement signal with 215 sam- ples through the system in Fig. 1 with a1 = a2 = 0 and receiver characteristics described in Table 4.1. I then calculated the residue and CPCR. The BLGN case was simulated similarly, using a 215-sample pseudorandom BLGN waveform as the measurement signal. In addition, the simulation included the adaptive equal- izer g, although the analysis assumed g = 1. 85 Table 4.1: Measured Receiver Characteristics. The large difference in ITOI limits the CPCR for BLGN due to third-order nonlinearities. Output Thermal ADC Channel Gain Noise in ITOI Saturation 15 MHz at ADC Input 1 7.8 dB -70.7 dBm 22.0 dBm 5.5 dBm 2 7.6 dB -67.4 dBm 18.6 dBm 5.5 dBm As shown in Fig. 4.4, the CPCR increases linearly (it is noise limited) until about -10 dBFS for BLGN and about 0 dBFS for LFM, at which point the CPCR peaks. The maximum CPCR is lower for a BLGN measurement signal because the BLGN signal has a much larger peak-to-peak voltage for the same input power and, therefore, begins to saturate at much lower input powers. Fig. 4.3 clearly shows this large difference between the two types of signals. For the LFM signal, the CPCR decreases rapidly once either channel sat- urates. The CPCR of the BLGN degrades at a much lower rate with increasing power, dropping off at about 5 dB per dB from -8 to -4 dBFS. Qualitatively the reason is that, though the BLGN signal has a large peak-to-peak voltage variation, at any given time the voltage is most likely to be closer to zero (Fig. 4.3). In con- trast, the voltage of the LFM signal is most likely to occur at the peak voltage. Because of this characteristic, there is a sharp reduction of CPCR at saturation for the LFM waveform. 86 From Fig. 4.4, I note that for both the LFM and BLGN cases, the numeri- cally simulated curves are in good agreement with the analytically calculated val- ues. For LFM waveforms, the analytical and simulated maximum CPCRs match, while for the BLGN case, the simulated data possesses a maximum CPCR ap- proximately 1.5 dB higher than the analytical calculation. This increase in CPCR is likely due to the limited number of samples in the simulation and the use of the adaptive g in the simulation. Recall the g was set to 1 in the analysis. The analyt- ical solution includes the residue from the long tail of the BLGN PDF, while the simulation only includes a finite number of samples that tends to ignore the long tail contribution. The inclusion of the long tail causes a gentle peaking compared to the simulation, but the discrepancy is not large and the curves match at higher input powers. It is not clear whether the adaptive g increases the CPCR by better matching the saturated signals. The maximum CPCR for both LFM and BLGN depends on the gain differ- ence between channels. In theory, if both channels were perfectly matched before equalization, the maximum CPCR would be infinite since the saturation residues would exactly match. Recall from Fig. 4.2 that after equalization the saturation voltages are different. The maximum saturation-limited CPCR for the LFM sig- nal occurs when the input signal A is just greater than F=pG1, in other words, when Channel 1 saturates. Applying A = F=pG1 to (4.5), the resulting maximum CPCR is CPCRmax;LFM = F 2 2Nt G2 G1 SNR2 2 G2 G1 (4.14) 87 Figure 4.5: Saturation-limited maximum CPCR versus channel gain difference for both measurement signals. For both measurement signals, the maximum CPCR decreases approximately linearly with increasing gain difference. where SNR2 is the output signal-to-noise ratio of Channel 2. Fig. 4.5 shows the dependence of the saturation-limited maximum CPCR on the gain difference between channels for both LFM and BLGN. The simulated LFM line clearly matches (4.14). The analytical solution (calculated numerically from (4.13)), shown in Fig. 4.5, is lower than the the simulation results. Since I earlier decided that the simulation is more accurate, I empirically determined that the maximum saturation-limited CPCR for a BLGN measurement signal from the simulation. I approximated the dotted blue line as CPCRmax;BLGN 16 F 2 2Nt G2 G1 SNR2 12 G2 G1: (4.15) The maximum CPCR decreases linearly with increasing gain difference, with a slope of approximately 0.9 (due to the change in Nt with changing gain). 88 Fig. 4.5 also shows that if the gain is very well matched (< 0:1 dB) then the BLGN CPCR increases by several dB, although this behavior is not captured in (4.15). The maximum CPCR for channels with a 1 dB gain difference, which in our experience is representative of a typical system, is about SNR2;dB 4 dB for LFM and SNR2;dB 12 dB for BLGN, so the maximum CPCR is about 8 dB higher for LFM measurement signals, which is consistent with Fig. 4.4. I can achieve the highest maximum CPCR through excellent analog gain matching before equalization. The maximum CPCR between different pairs of a larger set of receivers may vary substantially due to analog gain differences. Variations due to gain differences may be a significant source of CPCR variation in an otherwise identical set of receivers. 4.3 CPCR Limitations Due to Third-Order Nonlinearities The analog components of any receiver are slightly nonlinear. Third-order nonlinearities generate intermodulation products of the measurement signals, which can increase the residue and limit CPCR. In this section, I will determine the im- pact of third-order nonlinearities on the maximum CPCR for LFM and BLGN measurement signals. Throughout this section I assume the channel is not satu- rated, such that F pGix, and the g6= 1. 89 4.3.1 Effect of Third-Order Nonlinearities on CPCR with LFM Measurement Signal The LFM measurement signal is x = Asin(q(t)), where q(t) is the quadratic phase term of an LFM. The output voltage through Channel 1 of Fig. 4.1 is z1 = g p G2Asinq g rG 2 G1a1A 3 sin3q+g rG 2 G1 n1: I apply a trigonometric identity for sin3q and the output voltage becomes z1 = g p G2Asinq g rG 2 G1a1A 3 14 sin3q+ 34 sinq +g rG 2 G1 n1: The third harmonic term sin3q is filtered out prior to analog-to-digital conversion. The filtered output voltage of Channel 1 is z1 = g p G2A 1 34 a1A 2 pG 1 sinq+g rG 2 G1 n1 and the similarly filtered output voltage of Channel 2 is z2 = p G2A 1 34 a2pG 2 A2 sinq+n2: The residue using an LFM measurement signal is r = p G2A g 1 34 a1A 2 pG 1 1 34 a2pG 2 A2 sinq +g rG 2 G1 n1 n2: (4.16) The single-tap equalizer g completely cancels the sinq term and minimizes the residue when gmin = 1 34 a2pG 2 A2 = 1 34 a1A 2 pG 1 : (4.17) 90 Because the sinq term, which includes the effects of the third-order nonlinearity, can be fully removed with proper choice of g, third-order effects do not limit the maximum CPCR for LFM measurement signals. With g = gmin, the CPCR is the same as the linear case (4.5). 4.3.2 Effect of Third-Order Nonlinearities on CPCR with BLGN Measurement Signal The residue using a BLGN measurement signal is r = g p G2 p G2 x+ g rG 2 G1a1 a2 ! x3 + g rG 2 G1 n1 n2 ! : (4.18) I consider first the case g = 1 for which the linear term is fully canceled. To simplify the notation, let d be the residual third-order voltage gain d, rG 2 G1a1 a2: (4.19) The residue is r =dx3 + r G2 G1 n1 n2 ! (4.20) and the power of the residue (after bandpass filtering) is Pr =d2 E h x3 2 i +Nt = 12d2P3in +Nt (4.21) where the power of the third-order term is derived in the Appendix. The CPCR is then calculated to be CPCR = PoutP r = G2Pin12d2P3 in +Nt : (4.22) 91 The optimal input power to maximize the CPCR is Pin,opt = 3pNt=24d2. If the measurement signal power is greater than Pin,opt, the third-order nonlinearities dominate the residue and the CPCR decreases with increasing measurement power. As a result, the maximum CPCR limited by third-order nonlinearities with a BLGN signal is found by setting Pin = Pin,opt and is CPCRmax = G2(9Ntd) 2=3: (4.23) As seen above, unlike the LFM measurement signal case, third-order nonlineari- ties may limit the CPCR for BLGN measurement signals. When I allow g6= 1, I expect g to increase the CPCR slightly due to bet- ter matching of the third-order nonlinearity. This, however, decreases the linear matching, so the increase is expected to be small. This is explored further using simulations below. In the same way gain differences between channels impact saturation-limited CPCR, ITOI differences impact nonlinearity-limited CPCR. High ITOI matching results in lower residue from third-order nonlinearities and a higher CPCR. From (4.3) and (4.19), I find the relationship between d and the ITOI of each channel, d= rG 2 G1 2 3 pG 1 ITOI1 2 3 pG 2 ITOI2 = 23 pG 2 ITOI2 ITOI 2 ITOI1 1 (4.24) Substituting (4.24) into (4.23) CPCRmax = G 2 6Nt ITOI1 ITOI2 ITOI2 ITOI1 2=3 (4.25) 92 Figure 4.6: Maximum CPCR versus channel ITOI difference. Maximum CPCR increases above the worst-case maximum CPCR as the difference between ITOI de- creases (in other words, as ITOImax=ITOImin approaches 0 dB). Because of the 2=3 exponent, the sign of the denominator may be ignored and (4.25) may be written as CPCRmax = CPCR0 ITOI max=ITOImin ITOImax ITOImin 1 2=3 (4.26) with CPCR0 = G 2 6Nt ITOImin 2=3 (4.27) where ITOImin and ITOImax are the minimum and maximum ITOI of Channels 1 and 2. Fig. 4.6 shows a plot of (4.26) over (4.27). Note that CPCRmax > CPCR0 and that when ITOImax ITOImin, then CPCRmax CPCR0. That is, CPCR0 is the worst-case CPCRmax. Since the CPCR varies for different channel pairs, when measuring the max- imum CPCR using a BLGN measurement signal, it is best to measure many dif- ferent channel pairs and analyze the CPCR statistically. The maximum CPCR 93 variation is larger due to third-order nonlinearities than ADC saturation. 4.3.3 Discussion of Maximum Third-Order Nonlinearity-Limited CPCR In Section 4.3.1 I showed that, as long as a single-tap equalizer is available, the CPCR, when measured with an LFM measurement signal, is not limited by third-order linearities. On the other hand, in Section 4.3.2, I showed that nonlin- earities do limit the CPCR measured using a BLGN signal, and argued that even with the single-tap equalizer in place the increase would be small. The maximum CPCR in the BLGN case was shown to be dependent on the residual third-order voltage gain d. Fig. 4.7 plots analytical and simulated CPCR for both LFM and BLGN as a function of the measurement power assuming F yi. The simulation was executed in a manner similar to that presented in Section 4.2.3, with the receiver model modified to include third-order nonlinearities and exclude saturation for the parameters in Table 4.1 Both the analytical and simulated results for LFM show no dependence on the third-order nonlinearities if I include g. When I exclude g, the CPCR is limited by third order nonlinearities. Third-order nonlinearities clearly limit the maximum CPCR for BLGN mea- surement signals as expected from (4.23). The simulated results without g match the analytical results. With g included, the maximum CPCR increases by about 94 Figure 4.7: Maximum CPCR in the presence of third-order nonlinearities versus measure- ment signal power using the parameters in Table 4.1. With g, the maximum CPCR of the LFM measurement signal is not limited. For BLGN, the CPCR remains limited, but the inclusion of g increases the maximum CPCR by a few dB as predicted. 95 4 dB due to better matching between channels. The single tap equalizer g is not able to completely cancel the impact of third order nonlinearities like it does for LFM. 4.4 CPCR Limitations Due to Both ADC Saturation and Third- Order Nonlinearities In Sections 4.2 and 4.3, I studied the effects of ADC saturation and analog third-order nonlinearities on CPCR, with each effect in the absence of the other. I now consider both effects together, analytically, experimentally and through sim- ulation. For our experiments, I used two S-band receivers with 15 MHz of instan- taneous bandwidth and an RF bandwidth from 2.7 to 3.7 GHz [6]. The receivers have two down conversion stages and include analog-to-digital conversion. Ta- ble 4.1 lists the measured characteristics of the receivers. I reduced the LO drive power of the receivers from the previously published levels to increase the dif- ference in ITOI and reduce the absolute ITOI level. This increases the residual third-order voltage gain and reduces the maximum CPCR due to third-order non- linearities. The equalizer is a finite-impulse response, deterministic least squares im- plementation [61]. I examined filter length, causal versus non-causal filters, and training length, and it was determined that 65 taps and 3000 training samples pro- vide excellent performance over 15 MHz of bandwidth. 96 To assess the input power levels required to reach saturation, I measured the full scale power of Channel 2 by applying a sinusoid to the input and measuring the ADC output, increasing the input power until full scale was reached. 4.4.1 CPCR with LFM measurement signal The CPCR when measured with an LFM measurement signal is only limited by saturation, not third-order nonlinearities, so long as the single-tap equalizer g is allowed to vary. The maximum CPCR is, therefore, (4.14). To verify our analysis and simulations, I applied the same 15 MHz LFM waveform with a pulse duration of 100 ?s to the input of the two receivers through a microwave power divider. I increased the power from -45 dBFS to +3 dBFS in 0.2 dB increments, which sweeps through the linear regime into Channel 1 saturation first and then Channel 1 and 2 saturation. New equalizer coefficients were calculated for each measurement and trained on the first 3000 samples. The equalizer was then applied to the captured data and the CPCR was measured using all 65536 (216) samples taken. I included g to minimize the total residue. All measurements were made at 3.2 GHz. The experimentally measured LFM CPCR is plotted as the black line in Fig. 4.8, along with the expected CPCR performance according to (4.14) in solid black. The measured CPCR does not go as high as analysis predicts, although the CPCR matches far from saturation and after saturation has been reached, demon- strating that ADC saturation provides an absolute limit on the measure CPCR. 97 The lower-than-expected CPCR in the near-saturation region appears to stem from uncorrelated spurs in the receivers, which originate from EMI, not third-order nonlinearities, and limit the total channel matching. Fig. 4.9 shows the LFM spectra recorded from both channels, as well as the residue between the channels. The sideband spurs are clearly evident (at 10 and 33 kHz offsets from the signal) in the Channel 1; however, the sideband spurs are either not present or are lower in the Channel 2 spectrum. These uncorrelated spurs do not cancel to the noise floor, and as a result, limit the degree to which the channels are matched (maximum achievable CPCR) and raise the noise floor. The uncorrelated spurs are not due to nonlinearities, but are caused by some unknown EMI arising from isolation and grounding issues within the receiver rack, resulting in low frequency oscillations modulating the signal. The spur power is partially signal dependent, and I observe the same behavior when in- putting a single tone. Without these spurs, the LFM CPCR would continue to increase until saturation is reached, verifying that, with the inclusion of the single- tap filter, the LFM CPCR is not limited by third-order nonlinearities. 4.4.2 CPCR with BLGN measurement signal The CPCR, when measured with a BLGN measurement signal, is limited by both ADC saturation and third-order nonlinearities, although, normally only one determine limit the maximum CPCR. The total CPCR is found by substituting (4.12) into (4.7) to find Pr(s), and including Pr(s) in (4.22) (although including 98 Figure 4.8: Experimentally measured CPCR versus measurement signal power for both LFM and BLGN measurement signals. The right hand plot is a close-up cor- responding to the dotted region indicated on the left hand plot. For the BLGN case, the experimentally obtained data closely matches the expected CPCR; however, electromagnetic interference limited the CPCR measurement for the LFM case. 99 Figure 4.9: Output signal power of the equalized channel gz1, reference channel z2, and residue r versus frequency. The left hand figure shows the total 15 MHz LFM waveform and the right hand figure shows a narrow region of 400 kHz. Uncor- related spurs in the equalized and reference channels limit channel matching and CPCR. Signals are canceled by over 65 dB, but sideband spurs limit total CPCR compared to ideal CPCR of about 70 dB. 100 only one Nt) to find the total CPCR CPCR = G2Pin12d2P3 in +Nt +Pr(s) : (4.28) The maximum CPCR depends on d: if d is small, the maximum CPCR is ADC saturation limited; if d is large, then the maximum CPCR is third-order nonlinear- ity limited and lower than the saturation-limited CPCR (4.15). In order to experimentally measure the CPCR using a BLGN measurement signal, I applied a 15 MHz pseudorandom BLGN to the same two receivers and swept the power from 40 to 4 dBFS in 0.2 dB steps using the same equaliza- tion procedure described above. The pseudorandom noise sequence was longer than the capture time of the ADC, so the sequence did not repeat within a single capture. The experimentally measured BLGN CPCR is plotted in blue in Fig. 4.8, with the analytically expected results in solid blue. There is excellent agreement between the expected and observed CPCR behavior. The measured curve shows the CPCR roll-off due to third-order intermodulation and the sharp drop-off near -9 dBFS as saturation begins. The measured CPCR is somewhat lower than the ADC saturation-limited predicted value in (4.15) when the channels enter satura- tion. This may be due, in part, to the same spurs that reduce the maximum CPCR of the LFM measurement, but may also be because the predicted value considers saturation of only one channel, not both channels, as is the case in our measure- ment. 101 4.5 Discussion Our work has shown that the maximum CPCR of a pair of receivers is dra- matically impacted by the measurement signal chosen. Particularly in the pres- ence of saturation and third-order nonlinearities, the CPCR response can vary greatly depending upon whether an LFM or BLGN measurement signal is used. Even if the TOI of the receiver is very large such that the third-order nonlinearities are negligible, the maximum CPCR achievable with a BLGN measurement sig- nal is approximately 8 dB below that obtained with an LFM measurement signal. The maximum CPCR in both cases is dependent upon the gain difference between channels, with the CPCR decreasing for increasing gain disparity. If third-order nonlinearity effects are significant, the BLGN CPCR may be further reduced, al- though the actual degradation depends on the ITOI difference between channels. If an adaptive single-tap equalizer is included in one of the channels, the CPCR of the LFM measurement signal is not affected by third-order nonlinearities. I verified the analytically-derived results with both simulated and experimentally obtained data. Given the sensitivity of CPCR measurements to the properties of the mea- surement signal and the characteristics of the receiver pair used, any discussion of CPCR must include a specification of the measurement signal type and a dis- cussion of the receiver gain and ITOI difference. In particular, for CPCR mea- surements made with BLGN, precise matching between a pairs of receivers may inflate the maximum CPCR relative to the average of many other receivers pairs. 102 In most cases, LFM is likely preferable to BLGN to measure the effec- tiveness of the equalization, since the maximum CPCR is higher by at least 8 dB. This gives a larger measurement dynamic range to see imperfections in the equalization (or, as in our case, EMI). CPCR also allows indirect inference of the performance of interference mitigation techniques. When CPCR is measured for these purposes, it may be more useful to use a waveform representing the typical interference, so that the effect of nonlinearities would be included. 103 Chapter 5 Correlation of Noise There are three sources of noise in an ADC: thermal (and other random noise processes, such as shot noise), quantization, and sampling noise. Thermal noise is always independent between ADCs and is the largest source of noise in many modern ADCs. Quantization noise may be correlated between channels, but is typically below the thermal noise in modern ADCs and may be decorrelated using dithering [17]. Sampling noise (from clock or aperture jitter) is correlated when a common clock is used on all the ADC channels, and its magnitude depends on the input signal frequency and amplitude and the clock jitter. 5.1 Correlation of Thermal Noise I designed the test bed to determine the dynamic range improvement due to combining many ADC channels in parallel. When the noise and distortion is uncorrelated then the SNR increase by a factor M. The signal power, which is correlated, increases by M2, while the uncorrelated noise and distortion increases by M. Of the sources of noise in the test bed, I assumed that the white noise, usu- ally dominated by the thermal noise, was uncorrelated from channel to channel. Fig. 5.1a shows the spectrum of the 16 channels with an input power of -28 dBFS and input signal near 97.6 MHz. I chose an input power well below full scale, so 104 Figure 5.1: (a) Overlay of the spectrum of 16 channels with input signal of -60 dBFS. (b) Spectrum of 16 channels added in the voltage domain. The axis of (b) is offset by 10log10 16 = 12 dB, so that noise may be directly compared. At this input power, noise is uncorrelated and SNR is increased by 12 dB. that the potentially correlated sampling was minimal. Fig. 5.1b shows the spec- trum of the same signals added in the time domain. The y-axis of Fig. 5.1b is offset by 12 dB, such that uncorrelated noise is at the same level. The noise appears uncorrelated in the plots. I measured the SNDR using the power spectra. I calculated the noise and distortion power by summing all the bins in the power spectrum and subtracting the power in the signal bin. The SNDR is the ratio of the power in the signal bin over the noise and distortion power. I calculated the SNDR for each channel and the combined signal and found that the SNDR increased by an average of 11.98 dB, which demonstrates the expected 105 SNDR improvement. I conducted the same measurement using a single correlated tone across all channels for input powers from -52 dBFS to -0.1 dBFS. A signal offset from 98.1 MHz was applied to each channel and the phase and amplitude differences were removed using the calibration described earlier. I then captured 217 samples for each input power and converted the signal to the frequency domain using an FFT. I then measured the SNDR using by summing all bins except those containing the signal. I then measured the signal power bins. Fig. 5.2 shows the measured noise and distortion power from the 16 chan- nels and the combined channel. Below -15 dBFS, the noise and distortion remains constant around -74 dBFS. Above -15 dBFS, the noise and distortion power grad- ually increases to about -70 dBFS. The increase in noise and distortion power is likely due to increases in both distortion and sampling noise. The DDS noise power is < 75 within the 24 MHz filter bandwidth, so it is not likely to be the cause of the noise power increase. Using the same data, I calculated D using (2.23) as across the same input powers, as shown in Fig. 5.3. Above -10 dBFS, I begins to degrade from 0 reach- ing a low value of -2.5 dB near full scale. This value of I indicates would result from a ?r 0:05. For signals well below full scale, thermal noise is the dominate noise and distortion source and remains white and uncorrelated between channels regardless of the input signal. Near the full scale of the ADC the noise and distortion power increases significantly due to sampling noise and distortion from the ADC. These 106 Figure 5.2: Plots of the noise and distortion power from the 16 channels as well as the combined channel. The noise and distortion power increases significantly near the full scale of the ADC. This is likely the result of increases in both distortion and sampling noise. The DDS signal source noise is < 75 dBc within the filter bandwidth. 107 Figure 5.3: Plot of D for many different input powers. Below -10 dBFS, the noise and distortion is uncorrelated and I 0 dB. Above -10 dBFS, the noise and dis- tortion is partially correlated with D decreasing to a minimum values of about -2.7 dBFS. 108 noise and distortion sources are a partially correlated. In the rest of this chapter, I will further discuss the correlation of sampling noise and attempts to decorrelate it. Further, in the next chapter, I will discuss the correlation of harmonics. 5.2 Correlation of Sampling Noise For many single channel systems, sampling noise (from clock or aperture jitter) does not the limit the SNR [65, 66, 67, 68]; however, improvements in ADCs and the drive towards higher intermediate frequencies (IF) in RF applica- tions increases the impact of sampling noise [69]. Many modern ADCs have 3 dB bandwidths much greater than their sampling rate enabling higher IF frequen- cies; for instance, the Linear Technology LTC2208 used in these experiments has a 3 dB bandwidth of 700 MHz and a maximum sampling rate of 130 MHz [45]. Fig. 5.4 shows the maximum SNR of parallel ADC arrays with 1, 4, 8, and 16 channels as a function of IF frequency. In this calculation, the uncorrelated ther- mal noise-limited SNR of each individual ADC is taken as 78 dB, the correlated root-mean-square (RMS) clock jitter s? is 60 fs, and the uncorrelated RMS aper- ture jitter sm is 85 fs [45]; all three values are near the state of the art for their frequencies. The SNR contribution as a function of frequency is [70] SNR = M SNRthermal + M(ws m)2 + 1(ws ?)2 : (5.1) For a single channel, the SNR is thermal limited below about 100 MHz, while at higher frequencies the correlated sampling severely limits the maximum SNR. The onset frequency of clock-induced SNR degradation decreases for lower per- 109 Figure 5.4: Maximum SNR of parallel ADC arrays as a function of IF frequency. The SNR (excluding sampling noise) of a single ADC is 78 dB and the RMS clock jitter is 60 fs; both values are near the state of the art. The impact of sampling noise on a single channel is low for IFs below 100 MHz; however, as the num- ber of channels increases the SNR limitation due to correlated sampling noise becomes very significant. The 700 MHz 3 dB bandwidth of the LTC2208 is also marked. formance clocks and high numbers of ADC channels. Dedicated state-of-the-art crystal oscillators, which can cost over a thousand dollars are required to achieve the 60 fs jitter assumed here [1], hence any techniques which would enable im- proved system SNR with lower performance clocks are desirable. Fig. 5.5 shows the impact of a 200 fs RMS jitter source. For a single channel, the impact is small; however any multi-channel system is severely limited for IFs > 30 MHz. 110 Figure 5.5: Maximum SNR of parallel ADC arrays as a function of IF frequency. The SNR (excluding sampling noise) of a single ADC is 78 dB and the RMS clock jitter is 200 fs; the RMS clock jitter is common for PLL clock sources [1]. The impact of sampling noise on a single channel is significant for IFs above 50 MHz. 111 Figure 5.6: Downconversion block diagram with phase and frequency decorrelation. 5.3 Sampling Noise Model The clock jitter noise model I present here is based on several previous derivations [70, 71, 72]. The sampling clock period is T and the clock jitter is ?(nT) on the nth sample. The input signal to the ADC x(t) is sampled at time nT +?(nT) yielding an output y[n]= x(nT +?(nT)). I approximate this output as y[n]= x(nT +?(nT)) x(nT)+?(nT)x0(nT) (5.2) where x0(nT) is the sampled time derivative of the input signal x(t). 5.4 Impact of Phase and Frequency Shifts on Sampling Noise As Fig. 5.6 shows, consider an initial modulated radio frequency (RF) input signal to an array of M ADCs s(t)= A(t)cos(wRFt q(t)) (5.3) 112 where A(t) and q(t) are the amplitude and phase modulation. The RF input sig- nal mixes with a phase or frequency shifted local oscillator, cos(wLOt +fm(t)), and the output is lowpass filtered. Ignoring conversion loss, the downconverted intermediate frequency (IF) signal in each channel is xm(t)= A(t)cos wt +q(t)+fm(t) (5.4) where wLO wRF =w. The ADC then samples the intermediate frequency signal with a jittery clock and the digital output is ym[n]=A(nT)cos wnT +q(nT)+fm(nT) ?(nT)wA(nT)sin wnT +q(nT)+fm(nT) (5.5) where it was assumed that A0(t), q0(t), and f0m(t) are small compared to wA(t). The second term in (5.5) is the sampling noise of the IF signal. Finally, I digitally multiply the sampled output ym[n] by e jwnT jfm(nT) to frequency shift the signal to baseband and remove the excess phase. The final baseband signal zm[n] is composed of the desired baseband signal and the base- band sampling noise zm[n] = zsig[n]+em[n]. The desired baseband signal, after lowpass filtering, is zsig[n]= A(nT)e jq(nT) (5.6) where I again ignore conversion loss. I can downconvert simply using Euler?s identity because A(t) and q(t) are narrowband relative to the Nyquist bandwidth. Conversely, the clock jitter bandwidth considered here is wider than the Nyquist bandwidth, so Euler?s Identity cannot be used without accounting for 113 both the positive and negative frequencies and their aliases. The sampling noise after downconversion, but before filtering, is em[n]= ?(nT)A(nT)we jwnT jfm(nT) sin(wnT +q(nT)+fm(nT)): (5.7) I will ignore the filter when calculating the correlation between channels since there is no frequency dependence in the correlation coefficient assuming ?(nT) is white and wideband and taking into account both positive and negative frequen- cies and aliasing. 5.4.1 Determining the Correlation Coefficient The total sampling noise is the sum of the correlation coefficient matrix times the sampling noise in a single channel E 2 4 M m=1 em !23 5= M k=1 M l=1 E[eke l ] =s2e M k=1 M l=1 rk;l (5.8) where E[x] is the expectation of x, s2e = E[eme m] for all m, and the correlation coefficient is rk;l = E[eke l ]p E[eke k]E[ele l ] =r l;k: (5.9) The correlation coefficient matrix is Hermitian and, therefore, the imaginary parts cancel in the summation, so I only need to consider the real part of the correlation coefficient matrix ?rk;l =?(rk;l)= ?(E[eke l ])p E[eke k]E[ele l ]: (5.10) 114 Therefore, only the real part of the correlation coefficient ?rk;l is considered through- out the rest of this paper. For any channels k and l, the expected value of the sampling noise product is E[ek[n]el[n] ]= (1=2) E ?(nT)2A(nT)2w2 E h cos(Dfkl(nT))e jDfkl(nT) i : (5.11) where Dfkl(nT)=fk(nT) fl(nT) and, therefore, the real correlation coefficient is ?rk;l=E " e jDfkl(nT)+e jDfkl(nT) 2 cos(Dfkl(nT)) # =E cos2(Dfkl(nT)) (5.12) 5.4.2 Constant Phase Offsets For a constant phase offset, fm(nT) = fm, the real part of the correlation coefficient is ?rk;l = cos2(Dfkl): (5.13) The sampling noise between two channels is fully correlated (rkl = 1) when Dfkl = 0;p;::: and uncorrelated (rkl = 0) when Dfkl =p=2;3p=2;:::. It is pos- sible to reduce the sampling noise correlation between any two channels to zero by placing them in quadrature, which reduces the total sampling noise by 3 dB compared to the fully correlated case. However, if a third ADC is added with its phase p=2 offset from ADC 1 (or 2), then the newly added ADC is fully correlated with ADC 2 (or 1) and the total sampling noise reduction is less than 3 dB. 115 To achieve a maximum reduction in total sampling noise of 3 dB, the phase should be either randomly or deterministically distributed around the unit circle, or half the channels should be placed in quadrature with the other half of the channels. 5.4.3 Frequency Offsets For a linearly time varying phase offset, fm(nT)=wmt, the real part of the correlation coefficient is always ?rk;l = E[cos2(wkt wlt)]= 8 >>> < >>>: 1=2 if k6= l 1 if k = l (5.14) regardless of the frequency chosen. The sampling noise is always partially cor- related and cannot be fully decorrelated; however, no particular care needs to be taken to ensure partial correlation using frequency offsets. Frequency offsets re- duce the total sampling by 3 dB for a large array. 5.5 Measurements of Sampling Noise Correlation I verified the theoretical correlation coefficient by measuring the sampling noise correlation across a set of eight of the 16 ADCs described in Chapter 3, as shown in the block diagram of Fig. 5.7. An Agilent E8267D signal generator produced the 120 MHz ADC clock signal, which was subsequently divided by a microwave power splitter yielding a clock power at the ADC of about 12 dBm. The pulse generator, 800 MHz DDS 116 Figure 5.7: Block diagram of sampling noise measurement using 8 ADCs and DDSs. The measured phase noise of the 120 MHz signal generator and noise diode was -123 dBc/Hz at 1 MHz, Ill above the internal noise of the ADC (-157 dBc/Hz) and the DDS (-150 dBc/Hz at 1 MHz). 117 clock, and signal generator Ire all phase-locked to a common 10 MHz source. The phase noise of the signal generator was about -150 dBc/Hz ) at the 1 MHz corner frequency (about 1 ps jitter in 200 MHz bandwidth [1]), as measured using the phase noise measurement setting of an Agilent spectrum analyzer. This phase noise level was comparable to the white ADC noise of -157 dBc/Hz at ADC full scale and to the DDS phase noise of about -150 dBc/Hz at 1 MHz offset. The common signal generator clock jitter was large enough to yield a noise correlation coefficient of about 0.7 between all channels; the total measured noise?sampling, ADC thermal, and DDS source noise?was largely correlated across channels due to the influence of the common sampling noise. To better illustrate the impact of decorrelation techniques on sampling noise, I ensured that the clock jitter dominated our noise measurements by applying an amplified noise diode through a directional coupler to the clock signal before split- ting. This raised the ADC clock?s measured phase noise to about -123 dBc/Hz, ensuring that all measured noise was from sampling noise, as verified in Section 5.5.2. I eliminated phase and amplitude differences between channels by using a closed loop calibration procedure to equalize each DDS source signal. The DDSs Ire set to generate the same IF ( 90 MHz) with an initial unknown phase and an arbitrary amplitude below full scale. The ADCs measured the absolute amplitude using a fast Fourier transform (FFT) with a flat-top window. The DDS amplitudes Ire then adjusted until all signals measured about -0.1 dBFS, resulting in an amplitude variation across all channels of less than 0.1 dB. The ADCs then 118 measured the phase using an FFT and each DDS phase was adjusted to match the reference channel, resulting in a phase match of about 1 mrad. This calibration procedure yielded phase and amplitude alignment tighter than achievable with a typical microwave power splitter. 5.5.1 Measurement Approach To measure the real part of the correlation coefficient, I applied E[j(ek +el)j2]= E[jekj2]+E[jelj2]+2?(E[eke l ]) (5.15) to (5.10), so the the real part of the correlation coefficient becomes ?rk;l = E[j(ek +el)j 2] E[jekj2] E[jelj2] 2pE[eke k]E[ele l ] (5.16) Therefore, I can calculate the correlation coefficient by measuring three noise powers, that of channel k, channel l, and the sum of channels k and l. This tech- nique measures only the real part of the correlation coefficient. The sampling noise power is proportional to the input power, so all mea- surements Ire made with input powers of about -1 dBFS to maximize the noise. To measure the noise correlation coefficient, I applied a single tone with a fre- quency near 98 MHz to the ADCs and captured a sequence of 32768 samples. I then measured the noise power over a particular bandwidth away from the signal, for instance 85 to 95 MHz, by applying an FFT to the sequence and summing the magnitude squared of the FFT bins. In this way, I measured E[jekj2] and E[jelj2] from (5.16). To find the remaining term, E[j(ek +el)j2], I added the two voltage 119 sequences, applied an FFT, and summed the magnitude squared over the same set of FFT bins. Since the correlation coefficient is a ratio, the actual bandwidths over which the measurements are made are irrelevant, so long as there are a sufficient number of samples and the bandwidths are equal. 5.5.2 Verifying Sampling Noise To confirm that the measured noise was actually sampling noise and not ADC or DDS noise, I first modified the configuration shown in Fig. 5.7 to include two independent noise diodes (one on ADCs 1-4 and one on ADCs 5-8) coupled to the same signal generator. Fig. 5.8a shows the -0.8 dBFS signal with the sam- pling noise in the frequency domain, and Fig. 5.8b shows the noise over a 100 kHz bandwidth offset from the signal by 15 MHz. As described earlier, channel to channel phase and amplitude differences Ire calibrated out in the analog do- main prior to measurement. Clearly from Fig. 5.8b, the noise of channels 1-4 and 5-8 match each other within a set and appear independent between sets, indicat- ing correlation due to clock noise. The sampling noise power on ADCs 5-8 is about 3 dB lower than on ADCs 1-4 due to the different diode noise powers, and helping to distinguish between the two sets. All of the correlation coefficients be- tween channels with a common clock (ADCs 1-4 and 5-8) Ire greater than 0.999 and the magnitude of all of the correlation coefficients between channels with different noises Ire less than 0.03. From our experience, signals with correlation coefficients less than 0.03 are within our measurement error bounds and can be 120 Figure 5.8: (a) Plot of the generated signal in the frequency domain. The relatively high noise floors are due to the imposed sampling noise. (b) Frequency domain plot of the noise of each channel over a 100 kHz bandwidth offset 15 MHz from the signal. There is strong correlation within each set of ADCs 1-4 and 5-8, and no correlation between sets with different diodes. DDS and ADC noise was much lower at about -101 dBFS per FFT bin from prior measurements. considered independent, leading us to conclude that the noise present in our ex- perimental configuration arise primarily from clock-induced sampling noise, not independent thermal noise. 5.5.3 Constant Phase Offsets To experimentally assess the impact of our decorrelation techniques on sam- pling noise, I reverted to the single amplified noise diode configuration shown in Fig. 5.7, where a single noisy clock is common to all 8 ADCs. I phase and am- plitude aligned the signals using the close-loop calibration procedure described 121 earlier. I then purposely adjusted the phase of DDSs 5-8 by Dfkl (the phase shift was the same on all four channels) and measured the correlation coefficient of the sampling noise between all pairs of channels (64 total) using (5.16). Fig. 5.9 plots the average measured correlation coefficient ?r between all phase offset channels for many phase offsets from 0 to 2p. Here, ?r is calculated by ?r= 4 m=1 8 l=5 ?rml 42 : (5.17) The average measured two-channel correlation coefficient clearly follows the squared- cosine relationship predicted by (5.13), and complete decorrelation (?rk;l 0) was achieved for channels with a p=2 phase offset. The maximum decorrelation between two channels occurs when the phase difference is p=2 between channels. When a third channel is added with a p=2 phase offset to channel 2, it is then offset from channel 1 by p and the sampling noise is again fully correlated r = 1. It is not possible to reduce the the average correlation coefficient ?r when k6= l below 1=2. For systems with more than two channels, a distributed channel-dependent phase variation must be applied in or- der to achieve the maximum decorrelation. If the phase of M channels is either randomly or deterministically distributed from 0 to 2p, the average correlation coefficient ?r when k6= l may be reduced from 1 to 1=2. This reduces the total sampling noise by 3 dB for large arrays. I confirmed this result experimentally by uniformly distributing the phase of the signals from 0 to 2p (the phases Ire 0, p=4, p=2, 3p=4, p, 5p=4, 3p=2, and 7p=4) and measuring the correlation coefficient between all pairs of chan- 122 Figure 5.9: The measured correlation coefficient for phase shifted signals matches the prediction from (5.13). 123 Figure 5.10: Color map of the measured correlation coefficient matrix between channels with phase uniformly distributed among all 8 channels between 0 and 2p. nels. Fig. 5.10 shows the resulting phase correlation coefficient matrix as a color map. The sum of the sampling noise from all 8 channels is 3.14 dB below fully correlated noise, which matches the expected reduction of 3 dB. Fig. 5.11a shows the fully correlated spectrum and the phase-decorrelated measured spectrum with the uniform phase distribution from 0 to 2p (both spec- tra were calculated from the same measurement). The fully correlated spectrum was calculated by adding the magnitude of the spectrum of each channel together. The phase-decorrelated combined spectrum was calculated by adding the 8 chan- nels in the time domain then transforming to the frequency domain. The phase- decorrelated spectrum is always less than or equal to the fully correlated spectrum in every frequency bin. Measurements with random phases produced similar results. In addition, I 124 Figure 5.11: (a) The fully correlated and phase-decorrelated measured spectra for a uni- form phase distribution from 0 to 2p over a 24 MHz bandwidth. Scale rel- ative to the full scale of a single channel. (b) Close up of noise in 100 kHz bandwidth offset from the signal by 13 MHz. I calculated the correlated spectrum by summing the magnitude of each channel?s spectrum. The phase- decorrelated noise is 3 dB below the correlated output due to the phase shifts; the actual spectrum is always less than or equal to the correlated spectrum. 125 Figure 5.12: Color map of the measured correlation coefficient matrix when channels 1-4 are set in phase with each other but in quadrature with channels 5-8. achieved the same result when the signals were in quadrature (the phases were 0, 0, 0, 0, p=2, p=2, p=2, and p=2), as shown in Fig. 5.12 The correlation coefficient between channels in quadrature is about zero and the total sampling noise is 2.43 dB below fully correlated noise. 5.5.4 Frequency Offsets I measured the correlation coefficient of 8 ADCs where the input signal frequencies were separated by 1.8 kHz. Fig. 5.13 shows the 8 frequency shifted signals before downconversion and recorrelation. The spacing was chosen to be one bin width apart in the FFT to make the signals as similar as possible. Fig. 5.14 shows that the correlation coefficient between channels ranges from 0.42 to 0.50, confirming the coefficient of 0.5 predicted by (5.14). The total sampling noise is 126 Figure 5.13: Input signals of 8 ADCs shifted 1.8 kHz before downconversion and recor- relation. 2.76 dB below full correlation, matching the expected 3 dB decrease. The same decrease is expected for any set of frequency separations, as the correlation co- efficient of (5.14) is frequency-independent; this was verified with a second set of measurements with a frequency separation of 18 kHz (data not shown). Fur- thermore, the frequency separation need not be uniform, and randomly distributed frequency offsets are expected to have the same effect. 127 Figure 5.14: Measured correlation coefficient matrix is about 0.5 for all channels when input frequencies are offset by 1.8 kHz. 5.6 Summary and Conclusion of Chapter I have experimentally demonstrated that thermal noise is uncorrelated from channel to channel, as expected. I have shown theoretically and experimentally that applying phase and fre- quency offsets prior to digitization can reduce the correlation of sampling noise in a parallel ADC array with a common clock source. Specifically, by adjust- ing the frequency of each channel, by randomly or deterministically distributing the phase offset from 0 to 2p, or by placing half the channels in quadrature, I decrease the total sampling noise by about 3 dB. The 3 dB decrease in total sam- pling noise achieved in our work represents the maximum decrease possible using phase and frequency offsets as neither approach allows for negative correlation 128 coefficients, which would be required to cancel the noise further. I are not aware of any technique that enables negative correlation coefficients between sampling noise, I believe the phase and frequency offset approaches to be among the most effective methods of reducing the correlated sampling noise in fixed ADC arrays. As these techniques require mixers, they are most useful in RF applications. The phase offsets may even occur naturally in phased-array antenna. Previously, frequency and phase offsets have been shown to effectively decorrelate mixer spurs and harmonic distortion, and our results show an addi- tional benefit of these techniques. Fig. 5.4 showed that maximum SNR becomes severely limited by sampling noise for large arrays and high IFs, even with very low jitter clocks. Due to the cost of low jitter sources and the drive to higher IFs, a reduction of 3 dB is significant and welcome in many applications. Further performance improvement would require improved clock sources [50, 78, 79] or the use of independent clocks on each ADC or adequately small group of ADCs raising costs. 129 Chapter 6 Correlation of Harmonics Unfortunately, real ADCs generate not only noise, but also spurious har- monics which may limit the dynamic range and degrade system performance. The undesired harmonics may alias into the passband of the signal. The extent of spurious harmonic generation by an ADC is characterized by the SFDR, which is the ratio of the maximum signal to the largest harmonic, while the SNR is the ratio of the signal to the integrated noise power. Generally, a SFDR greater than the SNR within a given bandwidth is desirable. In this chapter, I use modeling and measurement to determine the potential inherent channel-to-channel correlation of harmonics in parallel ADC systems. All measurements were made on a specially designed 16-channel experimental test bed described in Chapter 3. In Section 6.1, I discuss the origins of ADC harmonics and present measurements of the inherent harmonic correlation of the ADC array. These measurements clearly establish the need for decorrelation tech- niques, if any significant increase in system SFDR is desired from parallelization. I also develop a set of metrics to evaluate the effectiveness of the decorrelation techniques. Finally, in Sections 6.3 and 6.4, I describe and experimentally demon- strate four phase and frequency decorrelation approaches, two of which are pro- posed here for the first time, and I add significant experimental results for the 130 other two. The phase decorrelation techniques of Section 6.3 yield an increase in system SFDR of a factor M or more, while the frequency decorrelation techniques of Section 6.4 increase system SFDR by a factor of M2 over the correlated system. Though certain approaches may yield greater gains in SFDR, due to the varying complexity of implementations, the best choice of decorrelation technique for a given application will depend upon the required SFDR and system complexity. 6.1 Origin of ADC Harmonics While some research has been performed on techniques to decorrelate ADC harmonics [20, 21, 18, 19], as far as I know no one has shown to what level harmonics in ADC arrays are inherently correlated. This is important, since any decorrelation technique deemed necessary increase the complexity of a parallel ADC array and should only be implemented if truly needed. The primary mechanisms of ADC harmonic generation are related to sam- pling and quantization. Fig. 6.1 shows a simple block diagram of an ADC com- posed of a sampler (or sample and hold) and a quantizer. The sampler generates harmonics due to the finite time constant of the sampling capacitor and the finite fall time of the sampling clock. The quantizer generates harmonics due to errors in its transfer function, and, even for an ideal transfer function, the quantization noise is harmonically related to the signal [80]. Depending on the ADC architecture, sampler distortion may be more or less significant than quantizer distortion. At the signal frequencies I measured, 131 Figure 6.1: Simple block diagram of an ADC composed of a sampler and quantizer. quantizer nonlinearities tend to dominate with our ADCs, but that should not be regarded as a general result. In this section, I describe both sources of harmonic generation in isolation and determine the amplitude and phase relationship between the input signal and its harmonics. Using mathematical models and methods from the literature, I consider distortions arising from sampling and quantization mechanisms, verify these models, and predict the inherent harmonic correlation across ADCs in any array. I then evaluate these predictions and the inherent correlation of both sources of harmonics simultaneously at a particular input signal frequency, through mea- surements in our test bed. 6.1.1 Harmonics from the Sampler To describe sampling-generated harmonics, I utilize a model from the lit- erature to understand the characteristics of sampler distortion and then compare those characteristics with measurements to determine their applicability to our ADC [86]. This understanding of the distortion characteristics can then be used to predict the correlation of sampler harmonics. Yu et al. analyzed the distortion of a simple metal-oxide-semiconductor field-effect transistor (MOSFET) sampler composed of only a single MOSFET 132 and sampling capacitor [86]. Similar analysis was also performed on a classic diode bridge sampler [74]. Yu et al. identified three sources of distortion de- pending on the clock fall time relative to the signal rise time or its frequency. Continuous-time distortion occurs due to the voltage dependent ?on? resistance of the MOSFET switch. Continuous-time distortion dominates when the clock fall time is short enough that the clock is practically ideal. Time-varying distor- tion occurs when the clock fall time is longer, such that the changing voltage of the clock Vg also modulates the voltage-dependent ?on? resistance of the switch. Sampling distortion occurs when the fall time is greater still, such that the ac- tual time that the switch closes (when the signal is sampled) depends on the input signal. Yu et al. highlight that their model ignores high-order transistor effects such as the body effect and bias-dependent junction capacitance; however, their analytical model compares very well with SPICE simulations. 6.1.1.1 Amplitude and Phase of Sampler Harmonics The Yu model overestimates the harmonic amplitudes because it does not take into account differential sampling and other linearization techniques [1, 89, 90]. For continuous-time distortion, the Yu model-predicted second and third harmonic coefficients are a2(A)= A2 jwCK(V g Vt)2 and a3(A)= A 2 2 jwCK(V g Vt)3 133 where K and Vt are MOSFET parameters, Vg is the clock voltage, C is sampling capacitor?s capacitance, and A and w are the input amplitude and frequency. For sampling distortion, the predicted harmonic coefficients are a2(A)= A4 jwT f Vg and a3(A)= 3A 2 32 wT f Vg 2 where Tf is the fall time of the clock. No closed form solutions of the harmonic coefficients due to time-varying distortion are available; however, this is accept- able because continuous-time distortion and sampling distortion cover both limits of clock fall time and input signal frequency. Yu et al. did not calculate higher order harmonic coefficients as these will increasingly be impacted by considerations like the body effect and the exact cir- cuit models. Despite this, assuming the pattern established by the second and third harmonics holds generally true, several basic trends emerge: 1) both continuous- time and sampling distortion harmonic powersjakmj2 are proportional to (A2)k 1; 2) continuous-time distortion harmonic power is proportional to w2 while sampler distortion harmonic power is proportional to w2(k 1); 3) the harmonic phase is proportional to the input phase fm plus an offset fkm that depends on the source of distortion: \akm = kfm +fkm (6.1) The phase offset fkm =p=2 for continuous-time distortion and fkm = (k 1)p=2 for sampling distortion harmonics. It should be noted, though, that this is only a 134 simple analysis and higher-order effects may impact the harmonic phase. 6.1.1.2 Measured Sampler Distortion Fig. 6.2 shows our measurement setup to investigate the sampler distortion. The measurement setup was composed of an Agilent E8267D signal generator, Mini-Circuits HELA-10B amplifier, filters to reduce source harmonics, and a sin- gle ADC. I chose this combination of signal source and amplifier to minimize the source harmonics. The second and third harmonic power from the signal genera- tor and amplifier measured at the ADC full scale was 54 and 70 dBFS, respectively, for input signal frequencies from 80 to 250 MHz. Above 250 MHz, the second harmonic power increased to -35 dBFS and the third harmonic power to -65 dBFS. The harmonics were reduced using four filters, a bandpass filter from 78-102 MHz and three lowpass elliptical filters with cutoff frequencies of 150, 225, and 300 MHz. For all input frequency, I had a filter with at least 75 dB of attenuation at the second and higher harmonics, which I measured on a Hewlett Packard 8720C network analyzer. Therefore, the second harmonic was 120 from 80-250 MHz and 100 from 80-250 MHz, which was well below the measured harmonic power. The third harmonic power was at least 30 dB below these. To measure the second through fifth harmonic power and phase, I applied the amplified and filtered tone to the input of each ADC?each ADC was mea- sured separately?and adjusted the input power to -0.5 dBFS. I measured with 135 Figure 6.2: Measurement setup used to capture Fig. 6.3 composed of an Agilent E8267D signal generator, Mini-Circuits HELA-10B amplifier, lowpass filters, and a single ADC. input signal frequencies from 80 to 300 MHz in 5 MHz intervals. The input signal was offset by 100 kHz and then adjusted so that the frequency was near the center of a frequency bin. I then captured the data, transformed the data to the frequency domain, and measured the phase offset fkm and magnitudejakmj. Fig. 6.3 shows the measured values of fkm andjakmjfor k = 2;3;4;5. The power of the second, third, and fourth harmonics clearly increases with frequency as predicted from the analysis, indicating that they are sampler distortion limited. The fifth harmonic power does not increase with frequency, indicating that it is quantizer limited. The harmonic powers and trends are well matched across all channels. The phase offset of the second and third harmonics trends toward p=2 with increasing frequency from p for the second harmonic and p for the third. The fourth harmonic phase offset varies significantly with frequency, while the fifth harmonic varies from p toward 0. The harmonic phase offsets do not match the theory; however, the phase offsets match very closely from channel to channel. 136 Figure 6.3: The second through fifth harmonic?s magnitude and phase measured at dif- ferent input frequencies near full scale of the ADCs. The second, third, and fourth harmonics all increase in power with frequency, although the second and fourth contain several troughs. The phase of the ADCs are largely consis- tent from channel to channel, suggesting strong correlation. 137 6.1.1.3 Predicted Sampler Harmonic Correlation As discussed in Section 2.1.3, the phase matching between channels de- termines the correlation. Therefore, from the previous observation I expect the sampler distortion to be nearly fully correlated. The measured phase offset and power are well matched across channels, so that with common input signals, the harmonics should be correlated. 6.1.2 Harmonics from Quantizer Quantization, even ideal quantization, generates harmonics of the input sig- nal. The characteristics of harmonics arising from ideal quantization (more com- monly called quantization noise) are well understood [40, 80]. The maximum harmonic from ideal quantization is -9.03n dBFS (dB relative to ADC full scale) for an n-bit ADC [2]. The ADCs characterized in this paper have 16 bits, so the maximum harmonic due to ideal quantization is at most -144 dBFS. As I shall show, this is well below the measured harmonics and thermal noise by tens of dB. In addition, dithering effectively decorrelates ideal quantization noise [17], so I may disregard quantization noise as a significant source of harmonics. Errors in the quantizer transfer function are a far more significant source of harmonics in ADCs than ideal quantization noise. To model the quantizer har- monics, I utilized a modeling method developed by Pan and Abidi [2]. In that method, they generated a digital signal and quantizer transfer function with er- rors. They applied the signal to the transfer function and measured the resulting 138 error sequence. Several quantizer transfer function models exist in the literature [91, 2, 92, 93, 94]; however, I chose to use measured transfer functions, since all models exhibit some deficiencies and to better validate the modeling method against measurements. 6.1.2.1 Simulated Amplitude and Phase of Quantization Harmon- ics I simulated the effect of quantizer nonlinearities by digitally generating a sinusoidal input with a particular amplitude. To the signal, I added thermal and phase noise and a DC offset, and initialized the tone to a different starting phase. I based the simulations on the technique employed in [2]. I then quantized the signal with noise to 16-bit integers. Then, using the measured error sequence as a 16-bit error look-up table (LUT), I mapped the ideally quantized sinusoid to the error LUT yielding a quantizer error sequence. Finally, I transformed the simulated error sequence into the frequency domain and measured the complex Fourier coefficient akm for the kth harmonic and mth channel. Fig. 6.4a shows the simulated complex Fourier coefficientsjakmjof the 16 channels for k = 2;3;4;5 using the measured transfer functions for input powers from -60 to -0.2 dBFS. The frequency of the test signal was exactly in the center of the fifth bin of a 524288-bin DFT; this ensured no spectral leakage or scalloping loss [95]. Fig. 6.4b shows the phase offset fkm of the same data. From Fig. 6.4a,jakmjremains nearly constant over all input powers, except 139 Figure 6.4: (a) Simulated jakmj. (b) Simulated fkm. (c) Measured jakmj. (d) Measured fkm. The simulated results used the measured INL with a noise signal as suggested in [2]. The measured results were measured at 38.6 MHz using the experimental test bed. The measured magnitudes show similar trends; the magnitude is nearly constant over most input powers with the second and third harmonics increasing near full scale. At lower powers, the simulated is higher than the measured. The simulated and measured phase offsets are vastly different. 140 for k = 2;3 at high input powers, which increase significantly. I believe the in- crease in second and third harmonic powers at higher input powers is due to the large-scale structure of the INL shown in Fig. 3.27. At large powers, the large- scale structure causes significant second and third harmonics, while higher-order harmonics are generated from the more random INL structure. In addition, at all input powers, the second and third harmonics are higher power than the fourth and higher harmonics. The phase offset of the simulated data is generally around 0 or p, with some deviation due to the noise, as shown in From Fig. 6.4b. In a second sim- ulation, I subtracted the original noisy signal and found that the phase is either exactly 0 or exactly p. There are no transient effects in the simulation to cause a phase offset other than 0 or p. The phase offsets appear randomly and evenly distributed between 0 or p. 6.1.2.2 Measured Amplitude and Phase of Quantizer Harmonics I then measured the harmonic coefficients of each channel by applying a tone from each of the 16 DDSs to each of the ADCs through a lowpass AAF, us- ing the test bed described in Section 3. The input signal frequency was slightly off of 38.6 MHz, so that the signal was near the center of a DFT bin. When the signal is near the center of the frequency bin, spectral leakage and scalloping loss are reduced; however, I still applied a Hann window to further reduce spec- tral leakage. I chose a signal in the first Nyquist zone to ensure that I measured 141 harmonics caused by the quantizer instead of the sampler, since the sampler har- monics are proportional to frequency; however, the measurements indicate that above -10 dBFS the sampler distortion is significant and impacts our ability to measure the quantizer nonlinearities. I chose an input signal frequency near 38.6 MHz to match our 48 MHz lowpass AAFs, which have a filter rejection of greater than 80 dB at the second harmonic frequency of 77.2 MHz; the second harmonic from the DDS and amplifier after filtering at the input of the ADC was approxi- mately -140 dBc. I measured 100 input signal powers from -60 to -0.2 dBFS at the ADC. The differences in ADC input power between channels were calibrated out using a closed-loop calibration step. At each input power, the ADC captured 524288 samples (the same as the simulation). I then transformed the signals to the frequency domain using a DFT and measured the harmonic coefficients akm. Fig. 6.4c and d show the measuredjakmjand fkm for k = 2;3;4;5 for input powers from -60 to -0.2 dBFS. The magnitude of the measured harmonics below -10 dBFS are below the simulated harmonics, but by a small amount. I think im- pact of dithering is underestimated in the simulated harmonics magnitudes, which results in a higher harmonic magnitude. The measured phase offsets below -10 dBFS appear largely random with some grouping around 0 and p like the sim- ulation. Again, the increase in random phase can be attributed to the impact of dithering on low magnitude harmonics. Above -10 dBFS, I think the sampler distortion began to impact the mea- sured quantizer harmonics. The measured second and third harmonics increase like the simulation; however, all measured harmonic magnitudes increased above 142 zero, which was not predicted by the simulation. In addition, near full scale, the phase offsets begin to cluster towards the phase offset of the sampler distortion p=2. At full scale, third harmonic from the sampler distortion is larger than the quantizer distortion, while the second harmonic sampler distortion remains be- low the quantizer harmonics. The sampler distortion theory and quantizer model predicted the measured behavior very well. 6.1.2.3 Predicted Quantizer Harmonic Correlation The simulations predict that the quantizer harmonic phases group around 0 and p. Above -10 dBFS, the measured results indirectly match these results. Below -10 dBFS, the phase offsets are largely random with some grouping. From this, I predict the correlation that the quantizer harmonics will be largely uncorre- lated; however, the tendency to group around 0 and p will result in significant correlation at times, as well as significant cancellation. Because of the possibility of strong correlation, it is important to attempt to decorrelate the harmonics even at low input frequencies. 6.1.2.4 Maximum Quantizer Harmonic Power The previous analysis, simulation, and measurements led us to conclude that any decorrelation technique should focus on the lowest-order harmonics and ignore the higher-order harmonics. Unlike the sampler distortion harmonics, the quantizer harmonics show random amplitude characteristics. I want to ensure 143 Figure 6.5: Maximum measured harmonics for k = 2;:::;100 for 100 input powers from -60 to -0.2 dBFS at 38.6 MHz. The maximum powers for the tenth and higher ADC harmonics are below -100 dBFS. that the higher-order harmonics at some arbitrary input power are not as larger as the lowest-order harmonics. Fig. 6.5 shows the maximum power for the first 100 harmonics for input powers from -60 to -0.2 dBFS collected at the same time as the previous quantizer harmonic measurements. The green dots are the even harmonics and the blue circles are the odd harmonics. Neglecting the peaks at k = 61;62;63, which are due to the DDS, the second and third harmonics are the highest. The maximum power for the tenth and higher harmonics is -100 dBFS, more than 15 dB below the maximum second harmonic, which confirms that higher-order harmonics remain much lower than the lowest-order harmonics. The noise per bin with the Hann window is about -123 dBFS/bin, which is about 12 dB below the lowest harmonic, ensuring that the results are not noise limited. 144 6.2 Inherent Harmonic Correlation in Parallel ADC Arrays The previous sections evaluated the origins of harmonics in ADCs and pro- vided qualitative predictions of the expected harmonic correlation in an ADC ar- ray. In this section, I investigate the inherent harmonic correlation without inten- tional decorrelation techniques. 6.2.1 Measured Inherent Harmonic Correlation Using our 16 channel test bed, I measured the first 100 harmonic coefficients akm for each channel for 120 input powers from -60 to -0.2 dBFS. I chose a signal frequency near 97.6 MHz so it would be near the center of a frequency bin in the DFT, although I still applied a Hann window. I performed a closed-loop phase calibration at each input power to ensure the input signals to each channel were coherent and recorded 262144 samples per data set. The AAF reduced the second harmonic from the DDS and amplifier to approximately -135 dBc at full scale and the third harmonic to less than -150 dBc, which are well below the measured harmonics. Fig. 6.6 shows Pk and Pk;max for k = 2;3;4;5. Pk and Pk;max were calculated from the measured harmonic coefficients according to (2.35) and (2.36). Above -8 dBFS input power, P2;max and P3;max are much larger than at lower input powers and increase linearly with input power. Both sampler and quantizer show this behavior at high input powers, so it is not possible to definitively determine the origin of those harmonics. Below -8 dBFS, Pk;max is nearly constant, with a slight 145 decrease with decreasing amplitude, for k = 2;3;4;5. This behavior matches the simulations and measurements of quantizer nonlinearities shown in the previous section. For signal powers greater than -8 dBFS, the Pk of the second and fourth harmonics is closer to Pk;max than for the third and fifth harmonics. Above -8 dBFS, the second harmonic is both the most correlated and has the highest power. However, below -20 dBFS, the third and fifth harmonics are more correlated than the second and fourth harmonics. The SFDR of the complete system is 91.2 dB and is determined by the second harmonic magnitude.s is closer to Pk;max than for the third and fifth harmonics. Above -8 dBFS, the second harmonic is both the most correlated and has the highest power. However, below -20 dBFS, the third and fifth harmonics are more correlated than the second and fourth harmonics. The SFDR of the complete system is 91.2 dB and is determined by the second harmonic magnitude. For any system full correlation yields Ik = 1 = 0 dB. Fig. 6.7 shows Ik for input signal powers -0.2, -5.2, -20.0, and -40.4 dBFS. At the highest input signal powers -0.2 and -5.2 dBFS, many harmonics approach full correlation with the same input signals. On the other hand, while many harmonics appear to be almost completely correlated, there are others that are significantly less correlated. For instance, at -0.2 dBFS, I93 is about -2 dB while I56 is < 20 dB. This is expected for higher order quantizer nonlinearities; some of the harmonic phases add coher- ently and others do not. For lower input signal powers, -20.0 and -40.4 dBFS, correlation decreases substantially across all harmonics. At these input powers, 146 Figure 6.6: Comparison of Pk;max and Pk for k =2;3;4;5 shows that second and fourth har- monics are more correlated at high powers (above -8 dBFS) and the third and fifth harmonics are more correlated at lower powers. The second harmonic is the largest harmonic. At some input powers, the harmonics destructively interfere and cancel. 147 Figure 6.7: Ik and Rk at -0.2, -5.2, -20.0, and -40.4 dBFS. Many higher order harmonics are well correlated at higher input powers and less correlated at lower input powers. the harmonics may be near the level of the noise, which is uncorrelated. 6.2.2 Inherent Correlation Summary In the previous section, I discussed the two primary sources of harmonics in ADCs ? sampler distortion and quantizer nonlinearities. I showed through modeling and measurements that the second and third harmonics exhibit the high- est powers regardless of whether they arise from sampler distortion or quantizer nonlinearities. I then demonstrated that many of the harmonics are strongly correlated. In particular, I showed (Fig. 6.6) that the second harmonic is well correlated from channel to channel, suggesting that it could significantly degrade dynamic range 148 improvements expected from parallelization. The focus of any decorrelation tech- niques should be decorrelation of the second and, to lesser extent, third harmonics. The higher order harmonics were often correlated; however, since I showed that their maximum power is significantly below that of the lower order harmon- ics, these are far less of a concern. Recall that the maximum second harmonic power was about -85 dBFS, while the maximum harmonic power for the eleventh or higher harmonic was less than -100 dBFS. 6.3 Phase Decorrelation Techniques In a previous report, Howard et al. proposed and demonstrated a method to decorrelate mixer spurs and harmonics in parallel receiver arrays [18]. Further measurements of this technique were performed by Rabideau using four receivers [19]. The technique involved applying a phase shift to the input signal of each channel by adjusting the LO phase driving each mixer in the parallel array. The phase shift is then removed digitally at the output, resulting in a decrease in the harmonic correlation, as described in Section 2.2.1 In this section, I apply their phase randomization approach to ADC arrays and evaluate its effectiveness at decorrelating ADC harmonics. In particular, I ex- pand upon their investigation by confirming that harmonic correlation follows the Rayleigh distribution and demonstrate that the effectiveness of phase randomiza- tion of SFDR may be limited by the random phase offsets drawn. I then implement an improved phase cancellation approach which adjusts the input phase to cancel 149 the highest power harmonic. I will show that this improved technique significantly increases the resulting SFDR as compared to the phase randomization technique. 6.3.1 Phase Randomization Measurements In order to evaluate the efficacy of the phase randomization approach, I collected two sets of data ? Sets 1 and 2 ? with different phase offsets in a very similar manner to that described in Section 6.2.1. I aligned the phase and amplitude of the signal into each channel at 97.6 MHz. I then adjusted the phase of the DDSs by qm; qm was different for each of the two sets, but was kept constant over all signal amplitudes. I recorded 262144 samples per channel in the ADCs. Finally, I applied qm to each channel to recorrelate the signals and measured the harmonic coefficients akm. I repeated this procedure for 120 different amplitudes from -60 to 0.2 dBFS. Fig. 6.8 shows the phase qm for Sets 1 and 2, plotted on the unit circle as red ?x?s? (the blue circles are the phases for phase cancellation discussed later). The phase sets were generated using a uniform pseudorandom number generator from 0 to 2p. Figs. 6.9 and 6.10 show Pk and Pk;max for k = 2;3;4;5 for the phase ran- domization Sets 1 and 2. As expected, Pk;max for each case is similar to Pk;max from Fig. 6.6, since only the phase has changed and Pk;max ignores the phase of the harmonics. Looking first at Set 1, Pk is well below Pk;max for all harmonics plotted, indicating substantial decorrelation. The average values of I2 and I3 over 150 Figure 6.8: Distribution of phase randomization Sets 1 and 2 around the unit circle. Sets were generated using uniform pseudorandom number generator from 0 to 2p. Phase randomization used the red ?x? phase offsets and phase cancellation used the adjusted blue circle phase offsets. all amplitudes are 13:2 and 14:4 dB, slightly below (in other words, better than) the Rayleigh approximation. The SFDR is 101.5 dB. Clearly, comparing Figs. 6.9 and 6.10, phase randomization was less effec- tive for Set 2 than for Set 1. In particular, P2 and P3 are much higher (indicating more correlation) at high powers. The mean values of I2 and I3 over all input powers are only 7:7 and 9:6 dB, but are greater (worse) at higher input pow- ers where Pk is largest, so that the SFDR is only 95:5 dB. Set 2 is less effective due to the particular phase offsets drawn. In Set 2, despite the input phases being random, the second and third harmonics, at higher input powers, tend to be on the same half of the unit circle, which invalidates the Rayleigh approximation and results in a high Ik. This demonstrates a weakness of this technique: while most of the harmonics may approach the Rayleigh distribution and be decorrelated, if the 151 Figure 6.9: Phase randomization Set 1 effectively decorrelates the harmonics. The SFDR improves to 101.5 dB from 91.2 dB. 152 Figure 6.10: Phase randomization Set 2 is less effective than Set 1. Both the second and third harmonic are largely correlated at higher powers and the SFDR is only 95.5 dB compared to 101.5 dB for Set 1. largest harmonics are well correlated (by chance) then the SFDR improvement is minimal. Fig. 6.11 shows Ik for Sets 1 and 2 for k = 2 to 100. The difference between the two sets is small for k 6, and both are more effective than no decorrelation technique. Howard et al. predicted that phase randomization results in a Rayleigh dis- tribution for the harmonic voltage gain n. Fig. 6.12 shows twelve-point histograms 153 Figure 6.11: Measured Ik for phase randomization Sets 1 and 2 at -0.2, -5.2, -20.0, and -40.4 dBFS. Ik shows significant decorrelation for all harmonics unlike Fig. 6.7. The peak Ik is about -3 dB and the average is approximately M 1. 154 Figure 6.12: 12-point histograms of n2 across 120 input powers have a similar shape to the Rayleigh distribution fn(n). of n2 for Sets 1 and 2 along with plots of the Rayleigh distribution (fn(n))2 for M = 16. The histograms show the first 100 harmonics across 120 input powers. Both histograms appear similar to Rayleigh distribution confirming this predic- tion. The expected value of n2 for Sets 1 and 2 are 16.1 and 16.5, which is very close to the predicted value of M = 16. Set 2 appears to be skewed higher than Set 1 resulting in a slightly higher expected value. Phase randomization reduces the correlation of harmonics as predicted. I tested two sets and they showed different levels of decorrelation on the low or- der harmonics; the SFDR improved from 91.2 dB with no phase shifts to 101.5 155 and 95.5 dB. While the average Ik was about M 1, the peak values of Ik were as high as -4 dB, which will impact SFDR. I confirmed that the harmonics follow the Rayleigh distribution. Parallel system designers must include this statistical behavior of the harmonics in their designs. 6.3.2 Phase Cancellation As an extension to Howard et al.?s phase randomization technique, I pro- pose an enhanced technique, in which I attempt to align the harmonic phases in such a way that the largest harmonic is canceled. Our approach arises from two observations: first, the phase of a harmonic at a particular input power level is predictable for both sampler distortion and quantizer nonlinearities; second, the low order harmonics dominate the total SFDR. For all the data sets observed so far, the second harmonic is always the highest, and it is always largest at the max- imum input power. Therefore, by arranging the second harmonic phases in such a way that they cancel at the maximum input power the total system SFDR may be increased. Other harmonics could be chosen for optimization instead of the second harmonic, such as the third harmonic, depending of the specifics of the system, such as bandwidth and harmonic sources. 6.3.2.1 Theory of Operation I randomly distribute the input phases, using the same distribution as the phase randomization technique. I then measure the complex Fourier coefficients 156 Figure 6.13: The vector formed by the sum of bopt is rotated, so that it is p out of phase with the sum of the channels of ?bopt. of the second harmonic a2;m for an input signal at full scale. I group the harmonics into two sets bopt and ?bopt, such that the magnitude of sum of the second harmonics from the bopt channels approximately equal the sum of the second harmonics of the ?bopt channel harmonics, i=bopt a2;i i=?bopt a2;i : (6.2) Once I find bopt and ?bopt, I adjust the phase of the sum of the channels in the set bopt to be p out of phase with the channels in ?bopt, \ i=bopt a2;i ! \ 0 @ i=?bopt a2;i 1 A=p (6.3) I adjust the phase of the harmonics by changing the input phases qm for m = bopt. I find bopt by searching over all possible sets of channels b, where the size of b may vary from 1 to M=2. The number of possible combinations increases with the total number of channels Then, for all the possible sets of b, I attempt to 157 find the sets that meet the condition in (6.2) by calculating the following ratio: max j i=b a2;ij;j i=?b a2;ij ! min j i=b a2;ij;j i=?b a2;ij !: (6.4) The set of b that minimizes the ratio is bopt. Appendix B includes the Matlab code to determine bopt. 6.3.2.2 Phase Cancellation Measurements Starting with the two sets of phase randomization data presented previously, I determined the optimal second harmonic phase cancellation sets bopt and ?bopt using the method described above. To expedite the search, I limited the size of b to four or less (the size of ?b was 13 to 16). The adjusted phases qm that satisfy (6.3) are marked with blue circles in Fig. 6.8. Using the adjusted phase offsets, I remeasured the harmonic coefficients akm at 97.6 MHz for input powers -60 to -0.2 dBFS. Figures 6.14 and 6.15 show Pk and Pk;max for the second through fifth harmonics. Figures 6.14 and 6.15 clearly show that the second harmonics cancel at full scale, with 42 dB of cancellation for Set 1. The third, fourth, and fifth harmonics of both sets are not canceled; however, these show the same level of decorrelation as the previous phase randomization data. The cancellation does not continue over the full input power range, but does reduce the maximum second harmonic power significantly. The SFDR increases from 101.5 to 103.9 dB for Set 1 and from 95.5 to 103.4 dB for Set 2. This is an improvement of 2.4 and 7.9 dB, respectively, 158 Figure 6.14: Measured Pk and Pk;max for k = 2;3;4;5 using phase cancellation technique for Set 1. The second harmonic is well canceled at full scale and improves the SFDR to 103.9 dB from 101.5 dB. The correlation of the other harmonics does not increase. compared to phase randomization alone. Ik for k 6 for both sets is similar to the results from phase randomization. The increase in SFDR is significant and is achieved with little additional complexity. Since the harmonic phase offsetsfkm vary over frequency and amplitude, the cancellation degrades as I change the frequency and amplitude from 97.6 MHz and -0.5 dBFS. To determine the reduced effectiveness, I measured phase cancellation 159 Figure 6.15: Measured Pk and Pk;max for k = 2;3;4;5 using phase cancellation technique for Set 2. The results are similar to Set 1 and the SFDR increases to 103.4 dB from 95.5 dB. 160 data sets using the same phase offsets trained at 97.6 MHz for input signal fre- quencies of 86.64 and 91.64 MHz. The second harmonic is in the fourth Nyquist zone at 91.64 and 97.6 MHz, while it is in the third Nyquist zone at 86.64 MHz. Because the Nyquist zone changes, the second harmonic phase changes sign, so I expect that phase cancellation will be less effective for a signal frequency of 86.64 than 91.64 MHz. The third harmonic does not undergo a phase change for these frequencies. Fig. 6.16 shows the measured Pk for Set 1 at 91.64 and 86.64 MHz, and Fig. 6.17 shows the measured Pk for Set 2 at 91.64 and 86.64 MHz. At 91.64 MHz, the second harmonic is canceled in both sets, although the null is not quite as deep as at the training frequency 97.6 MHz. The SFDR is 104.0 and 99.3 dB for Set 1 and Set 2, respectively. On the other hand, at 86.64 MHz, the second har- monic does not cancel significantly for either set, with the second harmonic of Set 2 significantly more correlated. Although substantial improvements from phase cancellation were not achieved for 86.64 MHz, when using offsets calculated for 97.6 MHz, the SFDR is still 99.5 and 96.2 dB for Sets 1 and 2, respectively, which is comparable to SFDR achieved using phase randomization. In summary, I have shown that phase randomization techniques reduce cor- relation of harmonics in ADC arrays; however, a particular set of phase offsets, such as phase randomization Set 2, may not provide a substantial increase in SFDR. Further, I extended this approach to include phase cancellation of the high- est power harmonic, which results in a further increase in SFDR. The phase can- cellation offsets are trained at a particular frequency, and if the harmonic phases 161 Figure 6.16: Measured Pk and Pk;max for k = 2;3 using phase cancellation Set 1 phases. At 86.64 MHz, the second harmonic is not canceled due to the Nyquist zone difference with the training data. At 91.64 MHz, the second harmonic is well canceled. 162 Figure 6.17: Measured Pk and Pk;max for k = 2;3 using phase cancellation Set 1 phases. At 86.64 MHz, the second harmonic is largely correlated and the SFDR is reduced. At 91.64 MHz, the second harmonic cancels as expected. 163 change significantly from the initial conditions, the cancellation may become less effective; however, the SFDR with this less effective cancellation is still com- parable to that of the phase randomization techniques. Phase cancellation is an effective method to improve the total SFDR compared to phase randomization. 6.4 Frequency Decorrelation Techniques Besides proposing the use of phase offsets to decorrelate spurs, Howard et al. suggested an implementation using frequency offsets [20, 21]. Howard?s method causes the harmonics to be offset in frequency from channel to channel, so that when the channels are combined the harmonics do not add, resulting a SFDR improvement of M2. I discuss Howard?s method and introduce an exten- sion of this technique. In our extension, I apply frequency offsets to each sampling clock, which causes aliased harmonics to occur at different frequencies. Our ex- tension removes the need for the mixer (shown in Fig. 2.3) required for the phase decorrelation and frequency offset techniques, making it more appropriate for a wider range of systems. 6.4.1 Frequency Offset Measurements In order to experimentally verify the expected decorrelation, I applied the frequency offset technique to our test bed. 16 full scale signals were applied to the 16 ADCs, each 10 kHz apart from the previous channel. I then converted the digitized signal to complex baseband using the Hilbert transform. Next, I 164 Figure 6.18: Before realignment, each channel is offset by 10 kHz from the previous channel. After downconversion and realignment, the signals coincide in fre- quency and are correlated. multiplied each term by the opposite frequency offset to frequency align each channel. Finally, I measure and remove the constant phase error qm. Fig. 6.18 shows the input signal before and after frequency realignment, which verifies that before realignment the signals were offset by 10 kHz, and that after realignment they are realigned. Figures 6.19 and 6.20 show the second and third harmonics before and after realignment. The signal and second harmonic are both in even Nyquist zones, and the offset is 10 kHz (k 1), while the third harmonic is in an odd Nyquist zone and the offset is 40 kHz (k+1). The highest harmonic of a single channel is about -84.2 dBFS, so the system SFDR is 10log10(162)= 24:1 dB higher at about 108.2 dB. Frequency offsets provide a higher system SFDR than either phase 165 Figure 6.19: Prior to realignment, the second harmonics are spaced by 20 kHz. After realignment, though the fundamental signals coincide, the second harmonics remain offset by 10 kHz, and as a result do not sum. randomization, where the best was 101.5 dB, or phase cancellation, where the best was 103.9 dB. 6.4.2 Clock Offsets As an extension of the frequency offset approach, I also present an alter- native method, in which I adjust the frequency of the ADC clock rather than the frequency of an LO. This technique has the advantage that no mixer is required, making it useful in a larger range of systems, such as direct RF sampling systems [96, 97]. 166 Figure 6.20: Before realignment, the third harmonics are spaced by 30 kHz. After re- alignment, they are spaced by 40 kHz (k+1). 6.4.2.1 Theory of Operation Fig. 6.21 shows the clock offset technique. The basic concept is similar to frequency offsets; by driving each ADC clock at a slightly different frequency, the generated harmonics of each channel are offset in frequency, while the signal remains correlated. With this technique, all aliased harmonics and other spurious signals are offset in frequency. For illustration, consider a system with two clocks, 118 and 120 MHz, and a signal at 34 MHz. The second harmonic occurs at 68 MHz regardless of the sampling rate; however, the second harmonics alias to dif- ferent frequencies, 50 and 52 MHz within the first Nyquist zone. This frequency separation occurs for all signals that alias. This has a side benefit that even har- monics from the signal source are offset in frequency, and the anti-aliasing filter requirements may be able to be relaxed. The signal must still satisfy the Nyquist 167 Figure 6.21: Schematic of the clock offset technique. Each channel is sampled by a dif- ferent frequency and then digitally resampled to realign the signals. conditions for all clock frequencies. The signal w(t) from (2.39) is sampled by M independent (but phase locked) oscillators with sampling periods of Tm and sampling frequency fm = 1=Tm. The sampled signal is xm[nm]= A(nmTm)cos(wnmTm p(nmTm))+em(w(nmTm)) (6.5) where nm is a channel specific sample index, A(t) and p(t) are amplitude and phase modulation, and e is the harmonic distortion, as before. The signal is digi- tally downconverted to baseband by applying the Hilbert transform and multiply- ing by e jwnmTm. The resulting complex signal component is A(nmTm)e jp(nmTm) (6.6) and the harmonic component is H(em(w(nmTm)))e jwnmTm: (6.7) Finally, the signals are realigned by digital resampling to nT0. 168 I again assume that A(t)= A and p(t)= 0. The harmonics are akme jkwnmTme jwnmTm (6.8) which aliases to positive frequencies in the first Nyquist zone. The aliased fre- quency of the kth harmonic for an input frequency of fin is min((k 1)fin mod fm; fm (k 1)fin mod fm): (6.9) The aliasing ( mod operation) thus induces the frequency offset of the harmon- ics. 6.4.2.2 Clock Offset Measurements In order to test the clock offset technique, I reconfigured the experimental test bed, such that eight DDSs and amplifiers were connected as clocks to eight ADCs. A fourth-order lowpass filter was connected to the output of each amplifier to reduces the clock spurs. I used a laboratory signal generator as the common signal source. The signal generator was filtered using a bandpass filter described in Section II and split using a Wilkinson power divider. In order to first confirm the signal correlation of a complicated signal sam- pled at different rates, I applied a pseudorandom additive white Gaussian noise (AWGN) signal with 10 MHz of bandwidth centered at 91.6 MHz to the ADCs. I sampled the signal with the following clock frequencies, one on each channel: 118.6, 118.8, 119.0, 119.2, 119.4, 119.6, 119.8, and 120.0 MHz. Fig. 6.22 shows the sampled signal plotted in the second Nyquist zone. The white noise signal 169 Figure 6.22: The sampled signal appears very similar when plotted in the second Nyquist zone as expected. Each clock is offset from the previous channel by 200 kHz. There is insufficient isolation between clocks, so large spurs occur on the right hand side of the spectrum. in the center of the band appears similar between the eight channels, with small differences due to the different sampling rates. The spurs in the frequency range 115-120 MHz of Fig. 6.22 arose due to in- sufficient isolation between the clock lines, which resulted in significant crosstalk between them. Harmonics of the clocks, which may be significant on clock sig- nals, also appear in the spectrum due to insufficient isolation. The crosstalk is a limitation of our particular test bed and is not inherent in the decorrelation tech- nique; however, future implementations of this technique must ensure sufficient 170 Figure 6.23: Captured signals after downconversion and resampling. The AWGN signals are well correlated in the frequency domain. clock isolation. Following data capture, I digitally downconverted the recorded signal to complex baseband (using 90 MHz as the center frequency). I resampled the signal to a common 60 MHz sampling rate. Finally, I multiplied each channel by a single complex number to remove the gain and phase differences caused by the Wilkinson power splitter. Figures 6.23 and 6.24 show that the AWGN is correlated across all eight channels in both the frequency and time domains. Clearly, the fundamental signal was correlated after sampling at different rates. In order to assess the efficacy of clock offsets on harmonic decorrelation, I changed the input signal to a sinusoid with a frequency of about 94.6 MHz at full- 171 Figure 6.24: Real part of the eight captured signals after downconversion and resampling. The excellent overlap indicates that the signals are well correlated in the time domain. scale power. I captured this signal on four channels, with sampling clock rates of 119.7, 119.8, 119.9, and 120.0 MHz. Fig. 6.25 shows the signals prior to realign- ment. The spurs induced by clock crosstalk are more noticeable with a sinusoidal input. The spurs are a limitation of the test bed and should be disregarded in this analysis. After realignment, the harmonics are aliased to different frequencies. In this case, the aliased second harmonics are located, after digital downconversion, at -20.8, -20.7, -20.6, -20.5 MHz, as shown in Fig. 6.26. Clock offsets cause aliased harmonics to appear at different frequencies and, therefore, do not sum. Ik is approximately M2 and the same improvement is achieved as for the frequency offsets technique. The clock offset approach has 172 Figure 6.25: The captured sinusoidal input is correlated when plotted in the second Nyquist zone. Insufficient clock isolation cause the series of spurs around the signal. 173 Figure 6.26: Plot of the second harmonics from each of the four channels following down- conversion and resampling. For the sampling frequencies chosen, the result- ing second harmonics are offset by 100 kHz. 174 the benefit of not requiring a mixer and being appropriate for a wider range of systems. The technical challenges; however, lay in providing sufficient clock iso- lation and designing an appropriate resampler. 6.5 Summary and Conclusion In this paper, I have identified the key sources of harmonic generation in an ADC and shown through modeling and measurements that the harmonics in a parallel ADC array are largely, although not fully, correlated. In addition, I determined that the second and third harmonics generally have the highest power and are more likely than other harmonics to be correlated, indicating that efforts to improve system performance through harmonic decorrelation should focus on low-order harmonics. In order to decorrelate those harmonics, I first implemented the phase ran- domization approach first proposed by Howard et al. [18]. I confirmed that phase randomization reduces the correlation as expected, and that the harmonic volt- age gain follows a Rayleigh distribution. This statistical behavior causes phase randomization to be less effective for small arrays than the other techniques. As discussed in [18], there is a reasonable probability of strong correlation between channels after applying phase randomization, which may increase the total corre- lation coefficient by about 8 dB above M for all array sizes. I measured a harmonic decorrelation value Ik as high as -4 dB, even though the mean was approximately -12 dB (M 1 for our 16-channel test bed). System designers must consider this 175 statistical behavior in a design that uses phase randomization or cancellation. I then extended the phase randomization approach by introducing a phase cancellation technique to reduce the largest correlated harmonics. This improved the SFDR in both cases tested compared to phase randomization only. However, if the Nyquist zone of the harmonics changes compared to the training frequency, the effectiveness of the cancellation decreases. Phase cancellation provides a technique to overcome the strong correlation between channels for particular har- monics. Phase cancellation adds minimal complexity to phase randomization and yields significant improvements to SFDR compared to phase randomization, so there are few reasons not to implement this technique. As a result, I recommend using phase cancellation over phase randomization in all cases. Future work in this area could investigate implementing phase randomiza- tion and phase cancellation techniques on the clock rather than the input signal via a local oscillator. I believe that these techniques should work when applied to the clock only and enable the application of phase decorrelation techniques to systems without mixers. The focus of this paper was ADC arrays; however, these techniques may be applied to many analog components in parallel. Finally, I demonstrated that frequency and clock offsets induce frequency spreading of the channel harmonics, such that the spurs are no longer at the same frequency. As a result these harmonics do not sum, and the SFDR is increased by M2 as opposed to an average of M for phase decorrelation techniques. Clock offsets do not require a mixer and are, therefore, more appropriate for a wider va- riety of systems, such as direct sampling systems. Frequency and clock offsets are 176 more complex and potentially costly than phase randomization and cancellation, since different LO and clock frequencies are required. While these techniques pro- vide a further improvement in SFDR compared to phase decorrelation, they are most appropriate when harmonics are a significant concern and the improvements provided by the simpler phase-only techniques are insufficient. Table 6.1 provides a summary of the measured SFDR for each decorrela- tion technique. All four techniques provide a clear SFDR improvement over that resulting from the inherent correlation of harmonics. The techniques may be com- bined to tailor the level of harmonic decorrelation. If a total SFDR improvement of 4M were required, for example, four unique frequency or clock offsets could be used in conjunction with phase randomization or cancellation to achieve the total improvement. The four techniques represent a ?toolbox?, giving system designers the ability to tailor their cost, complexity, and dynamic range improvement to suit system requirements. 177 Table 6.1: Measured SFDR for Each Technique Decorrelation Technique SFDR Improvement over Fully Correlated No Decorrelation (Fully Correlated) 89.1 dB n/a No Decorrelation 91.2 dB 2.1 dB Phase Randomization Set 1 101.5 dB 12.4 dB Phase Randomization Set 2 95.5 dB 6.4 dB Phase Cancellation Set 1 (97.6 MHz) * 103.9 dB 14.8 dB Phase Cancellation Set 1 (91.64 MHz) 104.0 dB 14.9 dB Phase Cancellation Set 1 (86.64 MHz) 99.5 dB 10.4 dB Phase Cancellation Set 2 (97.6 MHz) * 103.4 dB 14.3 dB Phase Cancellation Set 2 (91.64 MHz) 99.3 dB 10.2 dB Phase Cancellation Set 2 (86.64 MHz) 96.2 dB 7.1 dB Frequency Offsets 85+24:1 dB 19 dB Clock Offsets 92+24:1 dB 26.1 dB * Training frequency 178 Chapter 7 Summary and Discussion I developed a 16-channel testbed to investigate the partial correlation of noise and harmonics in parallel ADC arrays. I successfully achieved my four design goals. Large number of channels Low noise and spur measurement system Excellent signal correlation Excellent isolation between channels The test bed had a large number of channels by design. I successfully measured an average correlation coefficient across 16 channels of 0.05. The signals were very well correlated between channels, allowing me to successfully investigate harmonic correlation with signals aligned to 170 rad. The signal source noise was lower than the ADC noise by design and the DDS harmonics were mostly fil- tered from the ADC input. The remaining harmonics are separable from the ADC harmonics with only one of the first 100 harmonics overlapping. After several key hardware modifications, the ADC?s digital buffers were brought to a very low level and the channels had excellent isolation. I verified that the thermal noise is completely uncorrelated, as expected. I then demonstrated that the sampling noise from a common clock is completely 179 correlated. Phase randomization (phase cancellation is a variant of phase random- ization) and frequency offsets are capable of reducing the correlated noise in half. This can lead to significant cost savings in many applications due to expense of high performance clocks. Next, I have identified the key sources of harmonic generation in an ADC and shown through modeling and measurements quantizer harmonics are, at most, partially correlated; however, harmonics from the sampler are largely correlated. The sampler and quantizer harmonics are largest for the second and third har- monics. From these observations, I determined that efforts to improve system performance through harmonic decorrelation should focus on low order harmon- ics. In order to decorrelate those harmonics, I implemented a phase randomiza- tion approach first proposed by Howard et al. I demonstrated that phase random- ization reduces the correlation as expected, and I confirmed that the total correla- tion coefficient is consistent with Rayleigh distribution statistics. It is important to note that the Rayleigh distribution includes a finite probability of significant correlation. I measured Ik as high as -4 dB, even thought the mean was approxi- mately 12 dB, or M 1. System designers must consider this statistical behavior in a design that uses phase randomization or cancellation. Furthermore, I extended the phase randomization approach by introducing a phase cancellation technique to reduce the largest correlated harmonics. This im- proved the SFDR in both cases tested compared to phase randomization. However, if the Nyquist zone of the harmonics changes compared to the training frequency, 180 the effectiveness of the cancellation is less effective. Phase cancellation adds min- imal complexity and yields significant improvements to SFDR. As a result, phase cancellation should be chosen over phase randomization in actual implementation. Finally, I demonstrated that frequency and clock offsets induce frequency spreading of the channel harmonics, such that the spurs are no longer at the same frequency. As a result, the harmonics do not sum, and the SFDR is increased by M2. Clock offsets do not require a mixer and are, therefore, more appropriate for a wider variety of systems, such as direct sampling systems, although clock offsets may still be used in systems with mixers. Table 6.1 provides a summary of the measured SFDR for each decorrela- tion technique. All four techniques provide a clear SFDR range improvement over no decorrelation. Phase cancellation has low overhead for implementation relative to randomization, so there are few reasons not to implement this tech- nique. Frequency and clock offsets are more complex (and potentially costly), since different LO or clock frequencies must be generated. While they provide further improvement in SFDR, they are most appropriate when harmonics are a significant concern and the improvements provided by the simpler phase decor- relation approaches are not sufficient. The benefits increase for frequency and clock offsets as the number of channels increases, but the complexity increases at the same rate. The four decorrelation techniques described here all provide substantial SFDR improvement over implementations in which no decorrelation is attempted. 181 7.1 Suggestions for Future Work This dissertation outlines a complete ?toolbox?, which enables the decor- relation of harmonics for various systems. This work did not address sources of other spurs and distortion, the worst of which is often intermodulation distortion. Rabideau and Howard discussed the use of frequency-dependent phase offsets (dispersion) to phase decorrelate the intermodulation distortion [18], but the re- quired dispersion increases as the bandwidth decreases. They further investigate nonlinear correction to reduce intermodulation [19]. Many others have investi- gated this area as well [98, 99, 100, 101], but, as far as I know, no clear solution has been developed. This remains an interesting area of research. There is a loose connection between sampling distortion and sampling noise. The sampling distortion is proportional to the clock fall time, which increases with bandwidth if the clock is harmonically rich. However, the sampling noise also in- creases with the bandwidth, so there is a trade-off in the design of sample-and-hold circuits. Little research has been conducted in this area. There is the potential for advanced filter designs to allow both rich harmonics and block the noise using comb filters. More directly, there is a strong relationship between the thermal noise, in- put bandwidth, and sampler distortion. The thermal noise and input bandwidth are inversely proportional to the input sampling capacitance, while the sampler distortion is proportional to the input capacitance. More research is necessary to overcome these fundamental limitations. Finally, additional investigations should 182 be conducted on the modifications to the clock to provide phase cancellation and randomization. 183 Appendix A Power of BLGN through Third-Order Nonlinearity The power of a BLGN signal through a third-order nonlinearity E (x3)2 has not previously been determined and is required for (4.21). In general, the power of an arbitrary cubed signal is not simply the signal power cubed, E (x3)2 6= E (x2) 3. The power spectral density (PSD) for a Gaussian noise source filtered from DC to bandwidth B through a third-order nonlinearity x3 in bandwidth B is [102] PSD(f)= N3 27 2 B 2 3 2 f 2 (A.1) where N is the PSD of the input noise source. We refer to this as the ?lowpass? case and it shown schematically in Fig. A.1a. We describe the ?lowpass? case because it is known in the literature, while the ?bandpass ? case is not. The total noise power in bandwidth B is found by integrating the PSD from 0 to B. The resulting total output power is 13P3in with Pin = NB. If the BLGN measurement signal is centered at a carrier frequency that is Figure A.1: ?Lowpass? and ?bandpass? Gaussian noise through a third-order nonlinearity. 184 much greater than B, as is the case here, then when the noise passes through the third-order nonlinearity, some of its energy occurs in the third harmonic. We refer to this as the ?bandpass? case and depict it schematically in Fig. A.1b. Through numerical simulations, we determined that the total power for the BLGN measure- ment signal through a third-order nonlinearity is 12P3in. The coefficient depends on the signal characteristics. For example, the power for an LFM signal through a third-order nonlinearity is 2:5P3in. Appendix B Matlab Code to Determine bopt This appendix describes the Matlab code to determine bopt. The basic algo- rithm forms N matrices, where the first matrix is one dimensional, the second is two dimensional, and so on, up to an N-dimensional matrix. The largest value of N is M=2, so for large ADC arrays this may be significant amount of data. In the code below, the maximum value of N is 4, although, clearly, it could be expanded to higher dimensions. Each matrix is first initialized to ?. Then, for each element of the matrix the ratio 6.4 is calculated, where the elements of b are the indices of the matrix. The diagonals, where one index is equal to another are ignored because the values have already been calculated in the previous array. From all M matrices, the minimum value is calculated and returned as bopt. function [best_channel total_min]= find_best_channel(a_km, N) M = length(a_km); 185 if nargin < 2 N = 1; end for n = 1:N switch n case 1 for m = 1:M not_m = find_not_m(m,M); amp_m(m) = abs(a_km(m)); amp_not_m(m) = abs(sum(a_km(not_m))); end ratio = max([amp_m;amp_not_m])./min([amp_m;amp_not_m]); [min_value(1) index1] = super_min(ratio); case 2 ratio = inf(M,M); for m1 = 1:M for m2 = 1:M m = [m1 m2]; if length(unique(m)) == length(m) not_m = find_not_m(m,M); amp_m = abs(sum(a_km(m))); amp_not_m = abs(sum(a_km(not_m))); ratio(m1,m2) = max([amp_m;amp_not_m])./... min([amp_m;amp_not_m]); end end end [min_value(2) index2] = super_min(ratio); case 3 ratio = inf(M,M,M); for m1 = 1:M for m2 = 1:M for m3 = 1:M m = [m1 m2 m3]; if length(unique(m)) == length(m) not_m = find_not_m(m,M); amp_m = abs(sum(a_km(m))); amp_not_m = abs(sum(a_km(not_m))); ratio(m1,m2,m3) = max([amp_m;amp_not_m])./... min([amp_m;amp_not_m]); end end 186 end end [min_value(3) index3] = super_min(ratio); case 4 ratio = inf(M,M,M,M); for m1 = 1:M for m2 = 1:M for m3 = 1:M for m4 = 1:M m = [m1 m2 m3 m4]; if length(unique(m)) == length(m) not_m = find_not_m(m,M); amp_m = abs(sum(a_km(m))); amp_not_m = abs(sum(a_km(not_m))); ratio(m1,m2,m3,m4) = max([amp_m;amp_not_m])./... min([amp_m;amp_not_m]); end end end end end [min_value(4) index4] = super_min(ratio); end end [total_min grouping] = min(min_value); switch grouping case 1 best_channel = index1; case 2 best_channel = index2; case 3 best_channel = index3; case 4 best_channel = index4; end The function above, find best channel, calls two other functions, find not m and super min. These functions are listed below for completeness. function not_m = find_not_m(m,M) % Returns the set of channels not in m 187 possible_m = 1:16; N = length(m); temp = m(1) == possible_m; for n=2:N temp2 = m(n) == possible_m; temp = or(temp, temp2); end not_m = sort(unique(possible_m.* ?temp)); not_m = not_m(2:end); The function super min is a recursive implementation of Matlab?s built-in function min to work on multi-dimensional matrices at the same time instead of over a single dimension. function [a r] = super_min(a) % PROTOTYPE [minimum index] = super_min(a) % Returns the minimum and index for % a multidimensional array, up to DIM =4; N = length(size(a)); if N == 2 temp = size(a); if temp(1) == 1 N = 1; a = a?; elseif temp(2) == 1 N=1; end end for n = N:-1:1 [a,I] = min(a,[],n); Index.([?I? num2str(n)]) = I; end r = Index.(?I1?); for n = 2:N 188 switch length(r) case 1 r = [r Index.([?I? num2str(n)])(r)]; case 2 r = [r Index.([?I? num2str(n)])(r(1),r(2))]; case 3 r = [r Index.([?I? num2str(n)])(r(1),r(2),r(3))]; case 4 r = [r Index.([?I? num2str(n)])(r(1),r(2),r(3),r(4))]; end end 189 Bibliography [1] W. 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